cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pd.c (2189B)

      1/*
      2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
      3 *
      4 * This software is available to you under a choice of one of two
      5 * licenses.  You may choose to be licensed under the terms of the GNU
      6 * General Public License (GPL) Version 2, available from the file
      7 * COPYING in the main directory of this source tree, or the
      8 * OpenIB.org BSD license below:
      9 *
     10 *     Redistribution and use in source and binary forms, with or
     11 *     without modification, are permitted provided that the following
     12 *     conditions are met:
     13 *
     14 *      - Redistributions of source code must retain the above
     15 *        copyright notice, this list of conditions and the following
     16 *        disclaimer.
     17 *
     18 *      - Redistributions in binary form must reproduce the above
     19 *        copyright notice, this list of conditions and the following
     20 *        disclaimer in the documentation and/or other materials
     21 *        provided with the distribution.
     22 *
     23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
     25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
     27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
     28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
     29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
     30 * SOFTWARE.
     31 */
     32
     33#include <linux/kernel.h>
     34#include <linux/mlx5/driver.h>
     35#include "mlx5_core.h"
     36
     37int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn)
     38{
     39	u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
     40	u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {};
     41	int err;
     42
     43	MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
     44	err = mlx5_cmd_exec_inout(dev, alloc_pd, in, out);
     45	if (!err)
     46		*pdn = MLX5_GET(alloc_pd_out, out, pd);
     47	return err;
     48}
     49EXPORT_SYMBOL(mlx5_core_alloc_pd);
     50
     51int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn)
     52{
     53	u32 in[MLX5_ST_SZ_DW(dealloc_pd_in)] = {};
     54
     55	MLX5_SET(dealloc_pd_in, in, opcode, MLX5_CMD_OP_DEALLOC_PD);
     56	MLX5_SET(dealloc_pd_in, in, pd, pdn);
     57	return mlx5_cmd_exec_in(dev, dealloc_pd, in);
     58}
     59EXPORT_SYMBOL(mlx5_core_dealloc_pd);