cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ocelot_police.h (1366B)


      1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
      2/* Microsemi Ocelot Switch driver
      3 *
      4 * Copyright (c) 2019 Microsemi Corporation
      5 */
      6
      7#ifndef _MSCC_OCELOT_POLICE_H_
      8#define _MSCC_OCELOT_POLICE_H_
      9
     10#include "ocelot.h"
     11#include <net/flow_offload.h>
     12
     13enum mscc_qos_rate_mode {
     14	MSCC_QOS_RATE_MODE_DISABLED, /* Policer/shaper disabled */
     15	MSCC_QOS_RATE_MODE_LINE, /* Measure line rate in kbps incl. IPG */
     16	MSCC_QOS_RATE_MODE_DATA, /* Measures data rate in kbps excl. IPG */
     17	MSCC_QOS_RATE_MODE_FRAME, /* Measures frame rate in fps */
     18	__MSCC_QOS_RATE_MODE_END,
     19	NUM_MSCC_QOS_RATE_MODE = __MSCC_QOS_RATE_MODE_END,
     20	MSCC_QOS_RATE_MODE_MAX = __MSCC_QOS_RATE_MODE_END - 1,
     21};
     22
     23struct qos_policer_conf {
     24	enum mscc_qos_rate_mode mode;
     25	bool dlb; /* Enable DLB (dual leaky bucket mode */
     26	bool cf;  /* Coupling flag (ignored in SLB mode) */
     27	u32  cir; /* CIR in kbps/fps (ignored in SLB mode) */
     28	u32  cbs; /* CBS in bytes/frames (ignored in SLB mode) */
     29	u32  pir; /* PIR in kbps/fps */
     30	u32  pbs; /* PBS in bytes/frames */
     31	u8   ipg; /* Size of IPG when MSCC_QOS_RATE_MODE_LINE is chosen */
     32};
     33
     34int qos_policer_conf_set(struct ocelot *ocelot, u32 pol_ix,
     35			 struct qos_policer_conf *conf);
     36
     37int ocelot_policer_validate(const struct flow_action *action,
     38			    const struct flow_action_entry *a,
     39			    struct netlink_ext_ack *extack);
     40
     41#endif /* _MSCC_OCELOT_POLICE_H_ */