cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

qed_int.h (12000B)


      1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
      2/* QLogic qed NIC Driver
      3 * Copyright (c) 2015-2017  QLogic Corporation
      4 * Copyright (c) 2019-2020 Marvell International Ltd.
      5 */
      6
      7#ifndef _QED_INT_H
      8#define _QED_INT_H
      9
     10#include <linux/types.h>
     11#include <linux/slab.h>
     12#include "qed.h"
     13
     14/* Fields of IGU PF CONFIGURATION REGISTER */
     15#define IGU_PF_CONF_FUNC_EN       (0x1 << 0)    /* function enable        */
     16#define IGU_PF_CONF_MSI_MSIX_EN   (0x1 << 1)    /* MSI/MSIX enable        */
     17#define IGU_PF_CONF_INT_LINE_EN   (0x1 << 2)    /* INT enable             */
     18#define IGU_PF_CONF_ATTN_BIT_EN   (0x1 << 3)    /* attention enable       */
     19#define IGU_PF_CONF_SINGLE_ISR_EN (0x1 << 4)    /* single ISR mode enable */
     20#define IGU_PF_CONF_SIMD_MODE     (0x1 << 5)    /* simd all ones mode     */
     21/* Fields of IGU VF CONFIGURATION REGISTER */
     22#define IGU_VF_CONF_FUNC_EN        (0x1 << 0)	/* function enable        */
     23#define IGU_VF_CONF_MSI_MSIX_EN    (0x1 << 1)	/* MSI/MSIX enable        */
     24#define IGU_VF_CONF_SINGLE_ISR_EN  (0x1 << 4)	/* single ISR mode enable */
     25#define IGU_VF_CONF_PARENT_MASK    (0xF)	/* Parent PF              */
     26#define IGU_VF_CONF_PARENT_SHIFT   5		/* Parent PF              */
     27
     28/* Igu control commands
     29 */
     30enum igu_ctrl_cmd {
     31	IGU_CTRL_CMD_TYPE_RD,
     32	IGU_CTRL_CMD_TYPE_WR,
     33	MAX_IGU_CTRL_CMD
     34};
     35
     36/* Control register for the IGU command register
     37 */
     38struct igu_ctrl_reg {
     39	u32 ctrl_data;
     40#define IGU_CTRL_REG_FID_MASK           0xFFFF  /* Opaque_FID	 */
     41#define IGU_CTRL_REG_FID_SHIFT          0
     42#define IGU_CTRL_REG_PXP_ADDR_MASK      0xFFF   /* Command address */
     43#define IGU_CTRL_REG_PXP_ADDR_SHIFT     16
     44#define IGU_CTRL_REG_RESERVED_MASK      0x1
     45#define IGU_CTRL_REG_RESERVED_SHIFT     28
     46#define IGU_CTRL_REG_TYPE_MASK          0x1 /* use enum igu_ctrl_cmd */
     47#define IGU_CTRL_REG_TYPE_SHIFT         31
     48};
     49
     50enum qed_coalescing_fsm {
     51	QED_COAL_RX_STATE_MACHINE,
     52	QED_COAL_TX_STATE_MACHINE
     53};
     54
     55/**
     56 * qed_int_igu_enable_int(): Enable device interrupts.
     57 *
     58 * @p_hwfn: HW device data.
     59 * @p_ptt: P_ptt.
     60 * @int_mode: Interrupt mode to use.
     61 *
     62 * Return: Void.
     63 */
     64void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn,
     65			    struct qed_ptt *p_ptt,
     66			    enum qed_int_mode int_mode);
     67
     68/**
     69 * qed_int_igu_disable_int():  Disable device interrupts.
     70 *
     71 * @p_hwfn: HW device data.
     72 * @p_ptt: P_ptt.
     73 *
     74 * Return: Void.
     75 */
     76void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn,
     77			     struct qed_ptt *p_ptt);
     78
     79/**
     80 * qed_int_igu_read_sisr_reg(): Reads the single isr multiple dpc
     81 *                             register from igu.
     82 *
     83 * @p_hwfn: HW device data.
     84 *
     85 * Return: u64.
     86 */
     87u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn);
     88
     89#define QED_SP_SB_ID 0xffff
     90/**
     91 * qed_int_sb_init(): Initializes the sb_info structure.
     92 *
     93 * @p_hwfn: HW device data.
     94 * @p_ptt: P_ptt.
     95 * @sb_info: points to an uninitialized (but allocated) sb_info structure
     96 * @sb_virt_addr: SB Virtual address.
     97 * @sb_phy_addr: SB Physial address.
     98 * @sb_id: the sb_id to be used (zero based in driver)
     99 *           should use QED_SP_SB_ID for SP Status block
    100 *
    101 * Return: int.
    102 *
    103 * Once the structure is initialized it can be passed to sb related functions.
    104 */
    105int qed_int_sb_init(struct qed_hwfn *p_hwfn,
    106		    struct qed_ptt *p_ptt,
    107		    struct qed_sb_info *sb_info,
    108		    void *sb_virt_addr,
    109		    dma_addr_t sb_phy_addr,
    110		    u16 sb_id);
    111/**
    112 * qed_int_sb_setup(): Setup the sb.
    113 *
    114 * @p_hwfn: HW device data.
    115 * @p_ptt: P_ptt.
    116 * @sb_info: Initialized sb_info structure.
    117 *
    118 * Return: Void.
    119 */
    120void qed_int_sb_setup(struct qed_hwfn *p_hwfn,
    121		      struct qed_ptt *p_ptt,
    122		      struct qed_sb_info *sb_info);
    123
    124/**
    125 * qed_int_sb_release(): Releases the sb_info structure.
    126 *
    127 * @p_hwfn: HW device data.
    128 * @sb_info: Points to an allocated sb_info structure.
    129 * @sb_id: The sb_id to be used (zero based in driver)
    130 *         should never be equal to QED_SP_SB_ID
    131 *         (SP Status block).
    132 *
    133 * Return: int.
    134 *
    135 * Once the structure is released, it's memory can be freed.
    136 */
    137int qed_int_sb_release(struct qed_hwfn *p_hwfn,
    138		       struct qed_sb_info *sb_info,
    139		       u16 sb_id);
    140
    141/**
    142 * qed_int_sp_dpc(): To be called when an interrupt is received on the
    143 *                   default status block.
    144 *
    145 * @t: Tasklet.
    146 *
    147 * Return: Void.
    148 *
    149 */
    150void qed_int_sp_dpc(struct tasklet_struct *t);
    151
    152/**
    153 * qed_int_get_num_sbs(): Get the number of status blocks configured
    154 *                        for this funciton in the igu.
    155 *
    156 * @p_hwfn: HW device data.
    157 * @p_sb_cnt_info: Pointer to SB count info.
    158 *
    159 * Return: Void.
    160 */
    161void qed_int_get_num_sbs(struct qed_hwfn	*p_hwfn,
    162			 struct qed_sb_cnt_info *p_sb_cnt_info);
    163
    164/**
    165 * qed_int_disable_post_isr_release(): Performs the cleanup post ISR
    166 *        release. The API need to be called after releasing all slowpath IRQs
    167 *        of the device.
    168 *
    169 * @cdev: Qed dev pointer.
    170 *
    171 * Return: Void.
    172 */
    173void qed_int_disable_post_isr_release(struct qed_dev *cdev);
    174
    175/**
    176 * qed_int_attn_clr_enable: Sets whether the general behavior is
    177 *        preventing attentions from being reasserted, or following the
    178 *        attributes of the specific attention.
    179 *
    180 * @cdev: Qed dev pointer.
    181 * @clr_enable: Clear enable
    182 *
    183 * Return: Void.
    184 *
    185 */
    186void qed_int_attn_clr_enable(struct qed_dev *cdev, bool clr_enable);
    187
    188/**
    189 * qed_int_get_sb_dbg: Read debug information regarding a given SB
    190 *
    191 * @p_hwfn: hw function pointer
    192 * @p_ptt: ptt resource
    193 * @p_sb: pointer to status block for which we want to get info
    194 * @p_info: pointer to struct to fill with information regarding SB
    195 *
    196 * Return: 0 with status block info filled on success, otherwise return error
    197 */
    198int qed_int_get_sb_dbg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
    199		       struct qed_sb_info *p_sb, struct qed_sb_info_dbg *p_info);
    200
    201/**
    202 * qed_db_rec_handler(): Doorbell Recovery handler.
    203 *          Run doorbell recovery in case of PF overflow (and flush DORQ if
    204 *          needed).
    205 *
    206 * @p_hwfn: HW device data.
    207 * @p_ptt: P_ptt.
    208 *
    209 * Return: Int.
    210 */
    211int qed_db_rec_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
    212
    213#define QED_CAU_DEF_RX_TIMER_RES 0
    214#define QED_CAU_DEF_TX_TIMER_RES 0
    215
    216#define QED_SB_ATT_IDX  0x0001
    217#define QED_SB_EVENT_MASK       0x0003
    218
    219#define SB_ALIGNED_SIZE(p_hwfn)	\
    220	ALIGNED_TYPE_SIZE(struct status_block, p_hwfn)
    221
    222#define QED_SB_INVALID_IDX      0xffff
    223
    224struct qed_igu_block {
    225	u8 status;
    226#define QED_IGU_STATUS_FREE     0x01
    227#define QED_IGU_STATUS_VALID    0x02
    228#define QED_IGU_STATUS_PF       0x04
    229#define QED_IGU_STATUS_DSB      0x08
    230
    231	u8 vector_number;
    232	u8 function_id;
    233	u8 is_pf;
    234
    235	/* Index inside IGU [meant for back reference] */
    236	u16 igu_sb_id;
    237
    238	struct qed_sb_info *sb_info;
    239};
    240
    241struct qed_igu_info {
    242	struct qed_igu_block entry[MAX_TOT_SB_PER_PATH];
    243	u16 igu_dsb_id;
    244
    245	struct qed_sb_cnt_info usage;
    246
    247	bool b_allow_pf_vf_change;
    248};
    249
    250/**
    251 * qed_int_igu_reset_cam(): Make sure the IGU CAM reflects the resources
    252 *                          provided by MFW.
    253 *
    254 * @p_hwfn: HW device data.
    255 * @p_ptt: P_ptt.
    256 *
    257 * Return: Void.
    258 */
    259int qed_int_igu_reset_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
    260
    261/**
    262 * qed_get_igu_sb_id(): Translate the weakly-defined client sb-id into
    263 *                      an IGU sb-id
    264 *
    265 * @p_hwfn: HW device data.
    266 * @sb_id: user provided sb_id.
    267 *
    268 * Return: An index inside IGU CAM where the SB resides.
    269 */
    270u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id);
    271
    272/**
    273 * qed_get_igu_free_sb(): Return a pointer to an unused valid SB
    274 *
    275 * @p_hwfn: HW device data.
    276 * @b_is_pf: True iff we want a SB belonging to a PF.
    277 *
    278 * Return: Point to an igu_block, NULL if none is available.
    279 */
    280struct qed_igu_block *qed_get_igu_free_sb(struct qed_hwfn *p_hwfn,
    281					  bool b_is_pf);
    282
    283void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn,
    284			      struct qed_ptt *p_ptt,
    285			      bool b_set,
    286			      bool b_slowpath);
    287
    288void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn);
    289
    290/**
    291 * qed_int_igu_read_cam():  Reads the IGU CAM.
    292 *	This function needs to be called during hardware
    293 *	prepare. It reads the info from igu cam to know which
    294 *	status block is the default / base status block etc.
    295 *
    296 * @p_hwfn: HW device data.
    297 * @p_ptt: P_ptt.
    298 *
    299 * Return: Int.
    300 */
    301int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn,
    302			 struct qed_ptt *p_ptt);
    303
    304typedef int (*qed_int_comp_cb_t)(struct qed_hwfn *p_hwfn,
    305				 void *cookie);
    306/**
    307 * qed_int_register_cb(): Register callback func for slowhwfn statusblock.
    308 *
    309 * @p_hwfn: HW device data.
    310 * @comp_cb: Function to be called when there is an
    311 *           interrupt on the sp sb
    312 * @cookie: Passed to the callback function
    313 * @sb_idx: (OUT) parameter which gives the chosen index
    314 *           for this protocol.
    315 * @p_fw_cons: Pointer to the actual address of the
    316 *             consumer for this protocol.
    317 *
    318 * Return: Int.
    319 *
    320 * Every protocol that uses the slowhwfn status block
    321 * should register a callback function that will be called
    322 * once there is an update of the sp status block.
    323 */
    324int qed_int_register_cb(struct qed_hwfn *p_hwfn,
    325			qed_int_comp_cb_t comp_cb,
    326			void *cookie,
    327			u8 *sb_idx,
    328			__le16 **p_fw_cons);
    329
    330/**
    331 * qed_int_unregister_cb(): Unregisters callback function from sp sb.
    332 *
    333 * @p_hwfn: HW device data.
    334 * @pi: Producer Index.
    335 *
    336 * Return: Int.
    337 *
    338 * Partner of qed_int_register_cb -> should be called
    339 * when no longer required.
    340 */
    341int qed_int_unregister_cb(struct qed_hwfn *p_hwfn,
    342			  u8 pi);
    343
    344/**
    345 * qed_int_get_sp_sb_id(): Get the slowhwfn sb id.
    346 *
    347 * @p_hwfn: HW device data.
    348 *
    349 * Return: u16.
    350 */
    351u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn);
    352
    353/**
    354 * qed_int_igu_init_pure_rt_single(): Status block cleanup.
    355 *                                    Should be called for each status
    356 *                                    block that will be used -> both PF / VF.
    357 *
    358 * @p_hwfn: HW device data.
    359 * @p_ptt: P_ptt.
    360 * @igu_sb_id: IGU status block id.
    361 * @opaque: Opaque fid of the sb owner.
    362 * @b_set: Set(1) / Clear(0).
    363 *
    364 * Return: Void.
    365 */
    366void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn,
    367				     struct qed_ptt *p_ptt,
    368				     u16 igu_sb_id,
    369				     u16 opaque,
    370				     bool b_set);
    371
    372/**
    373 * qed_int_cau_conf_sb(): Configure cau for a given status block.
    374 *
    375 * @p_hwfn: HW device data.
    376 * @p_ptt: P_ptt.
    377 * @sb_phys: SB Physical.
    378 * @igu_sb_id: IGU status block id.
    379 * @vf_number: VF number
    380 * @vf_valid: VF valid or not.
    381 *
    382 * Return: Void.
    383 */
    384void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn,
    385			 struct qed_ptt *p_ptt,
    386			 dma_addr_t sb_phys,
    387			 u16 igu_sb_id,
    388			 u16 vf_number,
    389			 u8 vf_valid);
    390
    391/**
    392 * qed_int_alloc(): QED interrupt alloc.
    393 *
    394 * @p_hwfn: HW device data.
    395 * @p_ptt: P_ptt.
    396 *
    397 * Return: Int.
    398 */
    399int qed_int_alloc(struct qed_hwfn *p_hwfn,
    400		  struct qed_ptt *p_ptt);
    401
    402/**
    403 * qed_int_free(): QED interrupt free.
    404 *
    405 * @p_hwfn: HW device data.
    406 *
    407 * Return: Void.
    408 */
    409void qed_int_free(struct qed_hwfn *p_hwfn);
    410
    411/**
    412 * qed_int_setup(): QED interrupt setup.
    413 *
    414 * @p_hwfn: HW device data.
    415 * @p_ptt: P_ptt.
    416 *
    417 * Return: Void.
    418 */
    419void qed_int_setup(struct qed_hwfn *p_hwfn,
    420		   struct qed_ptt *p_ptt);
    421
    422/**
    423 * qed_int_igu_enable(): Enable Interrupt & Attention for hw function.
    424 *
    425 * @p_hwfn: HW device data.
    426 * @p_ptt: P_ptt.
    427 * @int_mode: Interrut mode
    428 *
    429 * Return: Int.
    430 */
    431int qed_int_igu_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
    432		       enum qed_int_mode int_mode);
    433
    434/**
    435 * qed_init_cau_sb_entry(): Initialize CAU status block entry.
    436 *
    437 * @p_hwfn: HW device data.
    438 * @p_sb_entry: Pointer SB entry.
    439 * @pf_id: PF number
    440 * @vf_number: VF number
    441 * @vf_valid: VF valid or not.
    442 *
    443 * Return: Void.
    444 */
    445void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn,
    446			   struct cau_sb_entry *p_sb_entry,
    447			   u8 pf_id,
    448			   u16 vf_number,
    449			   u8 vf_valid);
    450
    451int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
    452			  u8 timer_res, u16 sb_id, bool tx);
    453
    454#define QED_MAPPING_MEMORY_SIZE(dev)	(NUM_OF_SBS(dev))
    455
    456int qed_pglueb_rbc_attn_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
    457				bool hw_init);
    458
    459#endif