ravb.h (25895B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Renesas Ethernet AVB device driver 3 * 4 * Copyright (C) 2014-2015 Renesas Electronics Corporation 5 * Copyright (C) 2015 Renesas Solutions Corp. 6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * Based on the SuperH Ethernet driver 9 */ 10 11#ifndef __RAVB_H__ 12#define __RAVB_H__ 13 14#include <linux/interrupt.h> 15#include <linux/io.h> 16#include <linux/kernel.h> 17#include <linux/mdio-bitbang.h> 18#include <linux/netdevice.h> 19#include <linux/phy.h> 20#include <linux/platform_device.h> 21#include <linux/ptp_clock_kernel.h> 22 23#define BE_TX_RING_SIZE 64 /* TX ring size for Best Effort */ 24#define BE_RX_RING_SIZE 1024 /* RX ring size for Best Effort */ 25#define NC_TX_RING_SIZE 64 /* TX ring size for Network Control */ 26#define NC_RX_RING_SIZE 64 /* RX ring size for Network Control */ 27#define BE_TX_RING_MIN 64 28#define BE_RX_RING_MIN 64 29#define BE_TX_RING_MAX 1024 30#define BE_RX_RING_MAX 2048 31 32#define PKT_BUF_SZ 1538 33 34/* Driver's parameters */ 35#define RAVB_ALIGN 128 36 37/* Hardware time stamp */ 38#define RAVB_TXTSTAMP_VALID 0x00000001 /* TX timestamp valid */ 39#define RAVB_TXTSTAMP_ENABLED 0x00000010 /* Enable TX timestamping */ 40 41#define RAVB_RXTSTAMP_VALID 0x00000001 /* RX timestamp valid */ 42#define RAVB_RXTSTAMP_TYPE 0x00000006 /* RX type mask */ 43#define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002 44#define RAVB_RXTSTAMP_TYPE_ALL 0x00000006 45#define RAVB_RXTSTAMP_ENABLED 0x00000010 /* Enable RX timestamping */ 46 47enum ravb_reg { 48 /* AVB-DMAC registers */ 49 CCC = 0x0000, 50 DBAT = 0x0004, 51 DLR = 0x0008, 52 CSR = 0x000C, 53 CDAR0 = 0x0010, 54 CDAR1 = 0x0014, 55 CDAR2 = 0x0018, 56 CDAR3 = 0x001C, 57 CDAR4 = 0x0020, 58 CDAR5 = 0x0024, 59 CDAR6 = 0x0028, 60 CDAR7 = 0x002C, 61 CDAR8 = 0x0030, 62 CDAR9 = 0x0034, 63 CDAR10 = 0x0038, 64 CDAR11 = 0x003C, 65 CDAR12 = 0x0040, 66 CDAR13 = 0x0044, 67 CDAR14 = 0x0048, 68 CDAR15 = 0x004C, 69 CDAR16 = 0x0050, 70 CDAR17 = 0x0054, 71 CDAR18 = 0x0058, 72 CDAR19 = 0x005C, 73 CDAR20 = 0x0060, 74 CDAR21 = 0x0064, 75 ESR = 0x0088, 76 APSR = 0x008C, /* R-Car Gen3 only */ 77 RCR = 0x0090, 78 RQC0 = 0x0094, 79 RQC1 = 0x0098, 80 RQC2 = 0x009C, 81 RQC3 = 0x00A0, 82 RQC4 = 0x00A4, 83 RPC = 0x00B0, 84 RTC = 0x00B4, /* R-Car Gen3 and RZ/G2L only */ 85 UFCW = 0x00BC, 86 UFCS = 0x00C0, 87 UFCV0 = 0x00C4, 88 UFCV1 = 0x00C8, 89 UFCV2 = 0x00CC, 90 UFCV3 = 0x00D0, 91 UFCV4 = 0x00D4, 92 UFCD0 = 0x00E0, 93 UFCD1 = 0x00E4, 94 UFCD2 = 0x00E8, 95 UFCD3 = 0x00EC, 96 UFCD4 = 0x00F0, 97 SFO = 0x00FC, 98 SFP0 = 0x0100, 99 SFP1 = 0x0104, 100 SFP2 = 0x0108, 101 SFP3 = 0x010C, 102 SFP4 = 0x0110, 103 SFP5 = 0x0114, 104 SFP6 = 0x0118, 105 SFP7 = 0x011C, 106 SFP8 = 0x0120, 107 SFP9 = 0x0124, 108 SFP10 = 0x0128, 109 SFP11 = 0x012C, 110 SFP12 = 0x0130, 111 SFP13 = 0x0134, 112 SFP14 = 0x0138, 113 SFP15 = 0x013C, 114 SFP16 = 0x0140, 115 SFP17 = 0x0144, 116 SFP18 = 0x0148, 117 SFP19 = 0x014C, 118 SFP20 = 0x0150, 119 SFP21 = 0x0154, 120 SFP22 = 0x0158, 121 SFP23 = 0x015C, 122 SFP24 = 0x0160, 123 SFP25 = 0x0164, 124 SFP26 = 0x0168, 125 SFP27 = 0x016C, 126 SFP28 = 0x0170, 127 SFP29 = 0x0174, 128 SFP30 = 0x0178, 129 SFP31 = 0x017C, 130 SFM0 = 0x01C0, 131 SFM1 = 0x01C4, 132 TGC = 0x0300, 133 TCCR = 0x0304, 134 TSR = 0x0308, 135 TFA0 = 0x0310, 136 TFA1 = 0x0314, 137 TFA2 = 0x0318, 138 CIVR0 = 0x0320, 139 CIVR1 = 0x0324, 140 CDVR0 = 0x0328, 141 CDVR1 = 0x032C, 142 CUL0 = 0x0330, 143 CUL1 = 0x0334, 144 CLL0 = 0x0338, 145 CLL1 = 0x033C, 146 DIC = 0x0350, 147 DIS = 0x0354, 148 EIC = 0x0358, 149 EIS = 0x035C, 150 RIC0 = 0x0360, 151 RIS0 = 0x0364, 152 RIC1 = 0x0368, 153 RIS1 = 0x036C, 154 RIC2 = 0x0370, 155 RIS2 = 0x0374, 156 TIC = 0x0378, 157 TIS = 0x037C, 158 ISS = 0x0380, 159 CIE = 0x0384, /* R-Car Gen3 only */ 160 GCCR = 0x0390, 161 GMTT = 0x0394, 162 GPTC = 0x0398, 163 GTI = 0x039C, 164 GTO0 = 0x03A0, 165 GTO1 = 0x03A4, 166 GTO2 = 0x03A8, 167 GIC = 0x03AC, 168 GIS = 0x03B0, 169 GCPT = 0x03B4, /* Documented for R-Car Gen3 only */ 170 GCT0 = 0x03B8, 171 GCT1 = 0x03BC, 172 GCT2 = 0x03C0, 173 GIE = 0x03CC, /* R-Car Gen3 only */ 174 GID = 0x03D0, /* R-Car Gen3 only */ 175 DIL = 0x0440, /* R-Car Gen3 only */ 176 RIE0 = 0x0460, /* R-Car Gen3 only */ 177 RID0 = 0x0464, /* R-Car Gen3 only */ 178 RIE2 = 0x0470, /* R-Car Gen3 only */ 179 RID2 = 0x0474, /* R-Car Gen3 only */ 180 TIE = 0x0478, /* R-Car Gen3 only */ 181 TID = 0x047c, /* R-Car Gen3 only */ 182 183 /* E-MAC registers */ 184 ECMR = 0x0500, 185 RFLR = 0x0508, 186 ECSR = 0x0510, 187 ECSIPR = 0x0518, 188 PIR = 0x0520, 189 PSR = 0x0528, 190 PIPR = 0x052c, 191 CXR31 = 0x0530, /* RZ/G2L only */ 192 MPR = 0x0558, 193 PFTCR = 0x055c, 194 PFRCR = 0x0560, 195 GECMR = 0x05b0, 196 MAHR = 0x05c0, 197 MALR = 0x05c8, 198 TROCR = 0x0700, /* R-Car Gen3 and RZ/G2L only */ 199 CXR41 = 0x0708, /* RZ/G2L only */ 200 CXR42 = 0x0710, /* RZ/G2L only */ 201 CEFCR = 0x0740, 202 FRECR = 0x0748, 203 TSFRCR = 0x0750, 204 TLFRCR = 0x0758, 205 RFCR = 0x0760, 206 MAFCR = 0x0778, 207 CSR0 = 0x0800, /* RZ/G2L only */ 208}; 209 210 211/* Register bits of the Ethernet AVB */ 212/* CCC */ 213enum CCC_BIT { 214 CCC_OPC = 0x00000003, 215 CCC_OPC_RESET = 0x00000000, 216 CCC_OPC_CONFIG = 0x00000001, 217 CCC_OPC_OPERATION = 0x00000002, 218 CCC_GAC = 0x00000080, 219 CCC_DTSR = 0x00000100, 220 CCC_CSEL = 0x00030000, 221 CCC_CSEL_HPB = 0x00010000, 222 CCC_CSEL_ETH_TX = 0x00020000, 223 CCC_CSEL_GMII_REF = 0x00030000, 224 CCC_LBME = 0x01000000, 225}; 226 227/* CSR */ 228enum CSR_BIT { 229 CSR_OPS = 0x0000000F, 230 CSR_OPS_RESET = 0x00000001, 231 CSR_OPS_CONFIG = 0x00000002, 232 CSR_OPS_OPERATION = 0x00000004, 233 CSR_OPS_STANDBY = 0x00000008, /* Documented for R-Car Gen3 only */ 234 CSR_DTS = 0x00000100, 235 CSR_TPO0 = 0x00010000, 236 CSR_TPO1 = 0x00020000, 237 CSR_TPO2 = 0x00040000, 238 CSR_TPO3 = 0x00080000, 239 CSR_RPO = 0x00100000, 240}; 241 242/* ESR */ 243enum ESR_BIT { 244 ESR_EQN = 0x0000001F, 245 ESR_ET = 0x00000F00, 246 ESR_EIL = 0x00001000, 247}; 248 249/* APSR (R-Car Gen3 only) */ 250enum APSR_BIT { 251 APSR_MEMS = 0x00000002, /* Undocumented */ 252 APSR_CMSW = 0x00000010, 253 APSR_RDM = 0x00002000, 254 APSR_TDM = 0x00004000, 255}; 256 257/* RCR */ 258enum RCR_BIT { 259 RCR_EFFS = 0x00000001, 260 RCR_ENCF = 0x00000002, 261 RCR_ESF = 0x0000000C, 262 RCR_ETS0 = 0x00000010, 263 RCR_ETS2 = 0x00000020, 264 RCR_RFCL = 0x1FFF0000, 265}; 266 267/* RQC0/1/2/3/4 */ 268enum RQC_BIT { 269 RQC_RSM0 = 0x00000003, 270 RQC_UFCC0 = 0x00000030, 271 RQC_RSM1 = 0x00000300, 272 RQC_UFCC1 = 0x00003000, 273 RQC_RSM2 = 0x00030000, 274 RQC_UFCC2 = 0x00300000, 275 RQC_RSM3 = 0x03000000, 276 RQC_UFCC3 = 0x30000000, 277}; 278 279/* RPC */ 280enum RPC_BIT { 281 RPC_PCNT = 0x00000700, 282 RPC_DCNT = 0x00FF0000, 283}; 284 285/* UFCW */ 286enum UFCW_BIT { 287 UFCW_WL0 = 0x0000003F, 288 UFCW_WL1 = 0x00003F00, 289 UFCW_WL2 = 0x003F0000, 290 UFCW_WL3 = 0x3F000000, 291}; 292 293/* UFCS */ 294enum UFCS_BIT { 295 UFCS_SL0 = 0x0000003F, 296 UFCS_SL1 = 0x00003F00, 297 UFCS_SL2 = 0x003F0000, 298 UFCS_SL3 = 0x3F000000, 299}; 300 301/* UFCV0/1/2/3/4 */ 302enum UFCV_BIT { 303 UFCV_CV0 = 0x0000003F, 304 UFCV_CV1 = 0x00003F00, 305 UFCV_CV2 = 0x003F0000, 306 UFCV_CV3 = 0x3F000000, 307}; 308 309/* UFCD0/1/2/3/4 */ 310enum UFCD_BIT { 311 UFCD_DV0 = 0x0000003F, 312 UFCD_DV1 = 0x00003F00, 313 UFCD_DV2 = 0x003F0000, 314 UFCD_DV3 = 0x3F000000, 315}; 316 317/* SFO */ 318enum SFO_BIT { 319 SFO_FBP = 0x0000003F, 320}; 321 322/* RTC */ 323enum RTC_BIT { 324 RTC_MFL0 = 0x00000FFF, 325 RTC_MFL1 = 0x0FFF0000, 326}; 327 328/* TGC */ 329enum TGC_BIT { 330 TGC_TSM0 = 0x00000001, 331 TGC_TSM1 = 0x00000002, 332 TGC_TSM2 = 0x00000004, 333 TGC_TSM3 = 0x00000008, 334 TGC_TQP = 0x00000030, 335 TGC_TQP_NONAVB = 0x00000000, 336 TGC_TQP_AVBMODE1 = 0x00000010, 337 TGC_TQP_AVBMODE2 = 0x00000030, 338 TGC_TBD0 = 0x00000300, 339 TGC_TBD1 = 0x00003000, 340 TGC_TBD2 = 0x00030000, 341 TGC_TBD3 = 0x00300000, 342}; 343 344/* TCCR */ 345enum TCCR_BIT { 346 TCCR_TSRQ0 = 0x00000001, 347 TCCR_TSRQ1 = 0x00000002, 348 TCCR_TSRQ2 = 0x00000004, 349 TCCR_TSRQ3 = 0x00000008, 350 TCCR_TFEN = 0x00000100, 351 TCCR_TFR = 0x00000200, 352}; 353 354/* TSR */ 355enum TSR_BIT { 356 TSR_CCS0 = 0x00000003, 357 TSR_CCS1 = 0x0000000C, 358 TSR_TFFL = 0x00000700, 359}; 360 361/* TFA2 */ 362enum TFA2_BIT { 363 TFA2_TSV = 0x0000FFFF, 364 TFA2_TST = 0x03FF0000, 365}; 366 367/* DIC */ 368enum DIC_BIT { 369 DIC_DPE1 = 0x00000002, 370 DIC_DPE2 = 0x00000004, 371 DIC_DPE3 = 0x00000008, 372 DIC_DPE4 = 0x00000010, 373 DIC_DPE5 = 0x00000020, 374 DIC_DPE6 = 0x00000040, 375 DIC_DPE7 = 0x00000080, 376 DIC_DPE8 = 0x00000100, 377 DIC_DPE9 = 0x00000200, 378 DIC_DPE10 = 0x00000400, 379 DIC_DPE11 = 0x00000800, 380 DIC_DPE12 = 0x00001000, 381 DIC_DPE13 = 0x00002000, 382 DIC_DPE14 = 0x00004000, 383 DIC_DPE15 = 0x00008000, 384}; 385 386/* DIS */ 387enum DIS_BIT { 388 DIS_DPF1 = 0x00000002, 389 DIS_DPF2 = 0x00000004, 390 DIS_DPF3 = 0x00000008, 391 DIS_DPF4 = 0x00000010, 392 DIS_DPF5 = 0x00000020, 393 DIS_DPF6 = 0x00000040, 394 DIS_DPF7 = 0x00000080, 395 DIS_DPF8 = 0x00000100, 396 DIS_DPF9 = 0x00000200, 397 DIS_DPF10 = 0x00000400, 398 DIS_DPF11 = 0x00000800, 399 DIS_DPF12 = 0x00001000, 400 DIS_DPF13 = 0x00002000, 401 DIS_DPF14 = 0x00004000, 402 DIS_DPF15 = 0x00008000, 403}; 404 405/* EIC */ 406enum EIC_BIT { 407 EIC_MREE = 0x00000001, 408 EIC_MTEE = 0x00000002, 409 EIC_QEE = 0x00000004, 410 EIC_SEE = 0x00000008, 411 EIC_CLLE0 = 0x00000010, 412 EIC_CLLE1 = 0x00000020, 413 EIC_CULE0 = 0x00000040, 414 EIC_CULE1 = 0x00000080, 415 EIC_TFFE = 0x00000100, 416}; 417 418/* EIS */ 419enum EIS_BIT { 420 EIS_MREF = 0x00000001, 421 EIS_MTEF = 0x00000002, 422 EIS_QEF = 0x00000004, 423 EIS_SEF = 0x00000008, 424 EIS_CLLF0 = 0x00000010, 425 EIS_CLLF1 = 0x00000020, 426 EIS_CULF0 = 0x00000040, 427 EIS_CULF1 = 0x00000080, 428 EIS_TFFF = 0x00000100, 429 EIS_QFS = 0x00010000, 430 EIS_RESERVED = (GENMASK(31, 17) | GENMASK(15, 11)), 431}; 432 433/* RIC0 */ 434enum RIC0_BIT { 435 RIC0_FRE0 = 0x00000001, 436 RIC0_FRE1 = 0x00000002, 437 RIC0_FRE2 = 0x00000004, 438 RIC0_FRE3 = 0x00000008, 439 RIC0_FRE4 = 0x00000010, 440 RIC0_FRE5 = 0x00000020, 441 RIC0_FRE6 = 0x00000040, 442 RIC0_FRE7 = 0x00000080, 443 RIC0_FRE8 = 0x00000100, 444 RIC0_FRE9 = 0x00000200, 445 RIC0_FRE10 = 0x00000400, 446 RIC0_FRE11 = 0x00000800, 447 RIC0_FRE12 = 0x00001000, 448 RIC0_FRE13 = 0x00002000, 449 RIC0_FRE14 = 0x00004000, 450 RIC0_FRE15 = 0x00008000, 451 RIC0_FRE16 = 0x00010000, 452 RIC0_FRE17 = 0x00020000, 453}; 454 455/* RIC0 */ 456enum RIS0_BIT { 457 RIS0_FRF0 = 0x00000001, 458 RIS0_FRF1 = 0x00000002, 459 RIS0_FRF2 = 0x00000004, 460 RIS0_FRF3 = 0x00000008, 461 RIS0_FRF4 = 0x00000010, 462 RIS0_FRF5 = 0x00000020, 463 RIS0_FRF6 = 0x00000040, 464 RIS0_FRF7 = 0x00000080, 465 RIS0_FRF8 = 0x00000100, 466 RIS0_FRF9 = 0x00000200, 467 RIS0_FRF10 = 0x00000400, 468 RIS0_FRF11 = 0x00000800, 469 RIS0_FRF12 = 0x00001000, 470 RIS0_FRF13 = 0x00002000, 471 RIS0_FRF14 = 0x00004000, 472 RIS0_FRF15 = 0x00008000, 473 RIS0_FRF16 = 0x00010000, 474 RIS0_FRF17 = 0x00020000, 475 RIS0_RESERVED = GENMASK(31, 18), 476}; 477 478/* RIC1 */ 479enum RIC1_BIT { 480 RIC1_RFWE = 0x80000000, 481}; 482 483/* RIS1 */ 484enum RIS1_BIT { 485 RIS1_RFWF = 0x80000000, 486}; 487 488/* RIC2 */ 489enum RIC2_BIT { 490 RIC2_QFE0 = 0x00000001, 491 RIC2_QFE1 = 0x00000002, 492 RIC2_QFE2 = 0x00000004, 493 RIC2_QFE3 = 0x00000008, 494 RIC2_QFE4 = 0x00000010, 495 RIC2_QFE5 = 0x00000020, 496 RIC2_QFE6 = 0x00000040, 497 RIC2_QFE7 = 0x00000080, 498 RIC2_QFE8 = 0x00000100, 499 RIC2_QFE9 = 0x00000200, 500 RIC2_QFE10 = 0x00000400, 501 RIC2_QFE11 = 0x00000800, 502 RIC2_QFE12 = 0x00001000, 503 RIC2_QFE13 = 0x00002000, 504 RIC2_QFE14 = 0x00004000, 505 RIC2_QFE15 = 0x00008000, 506 RIC2_QFE16 = 0x00010000, 507 RIC2_QFE17 = 0x00020000, 508 RIC2_RFFE = 0x80000000, 509}; 510 511/* RIS2 */ 512enum RIS2_BIT { 513 RIS2_QFF0 = 0x00000001, 514 RIS2_QFF1 = 0x00000002, 515 RIS2_QFF2 = 0x00000004, 516 RIS2_QFF3 = 0x00000008, 517 RIS2_QFF4 = 0x00000010, 518 RIS2_QFF5 = 0x00000020, 519 RIS2_QFF6 = 0x00000040, 520 RIS2_QFF7 = 0x00000080, 521 RIS2_QFF8 = 0x00000100, 522 RIS2_QFF9 = 0x00000200, 523 RIS2_QFF10 = 0x00000400, 524 RIS2_QFF11 = 0x00000800, 525 RIS2_QFF12 = 0x00001000, 526 RIS2_QFF13 = 0x00002000, 527 RIS2_QFF14 = 0x00004000, 528 RIS2_QFF15 = 0x00008000, 529 RIS2_QFF16 = 0x00010000, 530 RIS2_QFF17 = 0x00020000, 531 RIS2_RFFF = 0x80000000, 532 RIS2_RESERVED = GENMASK(30, 18), 533}; 534 535/* TIC */ 536enum TIC_BIT { 537 TIC_FTE0 = 0x00000001, /* Documented for R-Car Gen3 only */ 538 TIC_FTE1 = 0x00000002, /* Documented for R-Car Gen3 only */ 539 TIC_TFUE = 0x00000100, 540 TIC_TFWE = 0x00000200, 541}; 542 543/* TIS */ 544enum TIS_BIT { 545 TIS_FTF0 = 0x00000001, /* Documented for R-Car Gen3 only */ 546 TIS_FTF1 = 0x00000002, /* Documented for R-Car Gen3 only */ 547 TIS_TFUF = 0x00000100, 548 TIS_TFWF = 0x00000200, 549 TIS_RESERVED = (GENMASK(31, 20) | GENMASK(15, 12) | GENMASK(7, 4)) 550}; 551 552/* ISS */ 553enum ISS_BIT { 554 ISS_FRS = 0x00000001, /* Documented for R-Car Gen3 only */ 555 ISS_FTS = 0x00000004, /* Documented for R-Car Gen3 only */ 556 ISS_ES = 0x00000040, 557 ISS_MS = 0x00000080, 558 ISS_TFUS = 0x00000100, 559 ISS_TFWS = 0x00000200, 560 ISS_RFWS = 0x00001000, 561 ISS_CGIS = 0x00002000, 562 ISS_DPS1 = 0x00020000, 563 ISS_DPS2 = 0x00040000, 564 ISS_DPS3 = 0x00080000, 565 ISS_DPS4 = 0x00100000, 566 ISS_DPS5 = 0x00200000, 567 ISS_DPS6 = 0x00400000, 568 ISS_DPS7 = 0x00800000, 569 ISS_DPS8 = 0x01000000, 570 ISS_DPS9 = 0x02000000, 571 ISS_DPS10 = 0x04000000, 572 ISS_DPS11 = 0x08000000, 573 ISS_DPS12 = 0x10000000, 574 ISS_DPS13 = 0x20000000, 575 ISS_DPS14 = 0x40000000, 576 ISS_DPS15 = 0x80000000, 577}; 578 579/* CIE (R-Car Gen3 only) */ 580enum CIE_BIT { 581 CIE_CRIE = 0x00000001, 582 CIE_CTIE = 0x00000100, 583 CIE_RQFM = 0x00010000, 584 CIE_CL0M = 0x00020000, 585 CIE_RFWL = 0x00040000, 586 CIE_RFFL = 0x00080000, 587}; 588 589/* GCCR */ 590enum GCCR_BIT { 591 GCCR_TCR = 0x00000003, 592 GCCR_TCR_NOREQ = 0x00000000, /* No request */ 593 GCCR_TCR_RESET = 0x00000001, /* gPTP/AVTP presentation timer reset */ 594 GCCR_TCR_CAPTURE = 0x00000003, /* Capture value set in GCCR.TCSS */ 595 GCCR_LTO = 0x00000004, 596 GCCR_LTI = 0x00000008, 597 GCCR_LPTC = 0x00000010, 598 GCCR_LMTT = 0x00000020, 599 GCCR_TCSS = 0x00000300, 600 GCCR_TCSS_GPTP = 0x00000000, /* gPTP timer value */ 601 GCCR_TCSS_ADJGPTP = 0x00000100, /* Adjusted gPTP timer value */ 602 GCCR_TCSS_AVTP = 0x00000200, /* AVTP presentation time value */ 603}; 604 605/* GTI */ 606enum GTI_BIT { 607 GTI_TIV = 0x0FFFFFFF, 608}; 609 610#define GTI_TIV_MAX GTI_TIV 611#define GTI_TIV_MIN 0x20 612 613/* GIC */ 614enum GIC_BIT { 615 GIC_PTCE = 0x00000001, /* Documented for R-Car Gen3 only */ 616 GIC_PTME = 0x00000004, 617}; 618 619/* GIS */ 620enum GIS_BIT { 621 GIS_PTCF = 0x00000001, /* Documented for R-Car Gen3 only */ 622 GIS_PTMF = 0x00000004, 623 GIS_RESERVED = GENMASK(15, 10), 624}; 625 626/* GIE (R-Car Gen3 only) */ 627enum GIE_BIT { 628 GIE_PTCS = 0x00000001, 629 GIE_PTOS = 0x00000002, 630 GIE_PTMS0 = 0x00000004, 631 GIE_PTMS1 = 0x00000008, 632 GIE_PTMS2 = 0x00000010, 633 GIE_PTMS3 = 0x00000020, 634 GIE_PTMS4 = 0x00000040, 635 GIE_PTMS5 = 0x00000080, 636 GIE_PTMS6 = 0x00000100, 637 GIE_PTMS7 = 0x00000200, 638 GIE_ATCS0 = 0x00010000, 639 GIE_ATCS1 = 0x00020000, 640 GIE_ATCS2 = 0x00040000, 641 GIE_ATCS3 = 0x00080000, 642 GIE_ATCS4 = 0x00100000, 643 GIE_ATCS5 = 0x00200000, 644 GIE_ATCS6 = 0x00400000, 645 GIE_ATCS7 = 0x00800000, 646 GIE_ATCS8 = 0x01000000, 647 GIE_ATCS9 = 0x02000000, 648 GIE_ATCS10 = 0x04000000, 649 GIE_ATCS11 = 0x08000000, 650 GIE_ATCS12 = 0x10000000, 651 GIE_ATCS13 = 0x20000000, 652 GIE_ATCS14 = 0x40000000, 653 GIE_ATCS15 = 0x80000000, 654}; 655 656/* GID (R-Car Gen3 only) */ 657enum GID_BIT { 658 GID_PTCD = 0x00000001, 659 GID_PTOD = 0x00000002, 660 GID_PTMD0 = 0x00000004, 661 GID_PTMD1 = 0x00000008, 662 GID_PTMD2 = 0x00000010, 663 GID_PTMD3 = 0x00000020, 664 GID_PTMD4 = 0x00000040, 665 GID_PTMD5 = 0x00000080, 666 GID_PTMD6 = 0x00000100, 667 GID_PTMD7 = 0x00000200, 668 GID_ATCD0 = 0x00010000, 669 GID_ATCD1 = 0x00020000, 670 GID_ATCD2 = 0x00040000, 671 GID_ATCD3 = 0x00080000, 672 GID_ATCD4 = 0x00100000, 673 GID_ATCD5 = 0x00200000, 674 GID_ATCD6 = 0x00400000, 675 GID_ATCD7 = 0x00800000, 676 GID_ATCD8 = 0x01000000, 677 GID_ATCD9 = 0x02000000, 678 GID_ATCD10 = 0x04000000, 679 GID_ATCD11 = 0x08000000, 680 GID_ATCD12 = 0x10000000, 681 GID_ATCD13 = 0x20000000, 682 GID_ATCD14 = 0x40000000, 683 GID_ATCD15 = 0x80000000, 684}; 685 686/* RIE0 (R-Car Gen3 only) */ 687enum RIE0_BIT { 688 RIE0_FRS0 = 0x00000001, 689 RIE0_FRS1 = 0x00000002, 690 RIE0_FRS2 = 0x00000004, 691 RIE0_FRS3 = 0x00000008, 692 RIE0_FRS4 = 0x00000010, 693 RIE0_FRS5 = 0x00000020, 694 RIE0_FRS6 = 0x00000040, 695 RIE0_FRS7 = 0x00000080, 696 RIE0_FRS8 = 0x00000100, 697 RIE0_FRS9 = 0x00000200, 698 RIE0_FRS10 = 0x00000400, 699 RIE0_FRS11 = 0x00000800, 700 RIE0_FRS12 = 0x00001000, 701 RIE0_FRS13 = 0x00002000, 702 RIE0_FRS14 = 0x00004000, 703 RIE0_FRS15 = 0x00008000, 704 RIE0_FRS16 = 0x00010000, 705 RIE0_FRS17 = 0x00020000, 706}; 707 708/* RID0 (R-Car Gen3 only) */ 709enum RID0_BIT { 710 RID0_FRD0 = 0x00000001, 711 RID0_FRD1 = 0x00000002, 712 RID0_FRD2 = 0x00000004, 713 RID0_FRD3 = 0x00000008, 714 RID0_FRD4 = 0x00000010, 715 RID0_FRD5 = 0x00000020, 716 RID0_FRD6 = 0x00000040, 717 RID0_FRD7 = 0x00000080, 718 RID0_FRD8 = 0x00000100, 719 RID0_FRD9 = 0x00000200, 720 RID0_FRD10 = 0x00000400, 721 RID0_FRD11 = 0x00000800, 722 RID0_FRD12 = 0x00001000, 723 RID0_FRD13 = 0x00002000, 724 RID0_FRD14 = 0x00004000, 725 RID0_FRD15 = 0x00008000, 726 RID0_FRD16 = 0x00010000, 727 RID0_FRD17 = 0x00020000, 728}; 729 730/* RIE2 (R-Car Gen3 only) */ 731enum RIE2_BIT { 732 RIE2_QFS0 = 0x00000001, 733 RIE2_QFS1 = 0x00000002, 734 RIE2_QFS2 = 0x00000004, 735 RIE2_QFS3 = 0x00000008, 736 RIE2_QFS4 = 0x00000010, 737 RIE2_QFS5 = 0x00000020, 738 RIE2_QFS6 = 0x00000040, 739 RIE2_QFS7 = 0x00000080, 740 RIE2_QFS8 = 0x00000100, 741 RIE2_QFS9 = 0x00000200, 742 RIE2_QFS10 = 0x00000400, 743 RIE2_QFS11 = 0x00000800, 744 RIE2_QFS12 = 0x00001000, 745 RIE2_QFS13 = 0x00002000, 746 RIE2_QFS14 = 0x00004000, 747 RIE2_QFS15 = 0x00008000, 748 RIE2_QFS16 = 0x00010000, 749 RIE2_QFS17 = 0x00020000, 750 RIE2_RFFS = 0x80000000, 751}; 752 753/* RID2 (R-Car Gen3 only) */ 754enum RID2_BIT { 755 RID2_QFD0 = 0x00000001, 756 RID2_QFD1 = 0x00000002, 757 RID2_QFD2 = 0x00000004, 758 RID2_QFD3 = 0x00000008, 759 RID2_QFD4 = 0x00000010, 760 RID2_QFD5 = 0x00000020, 761 RID2_QFD6 = 0x00000040, 762 RID2_QFD7 = 0x00000080, 763 RID2_QFD8 = 0x00000100, 764 RID2_QFD9 = 0x00000200, 765 RID2_QFD10 = 0x00000400, 766 RID2_QFD11 = 0x00000800, 767 RID2_QFD12 = 0x00001000, 768 RID2_QFD13 = 0x00002000, 769 RID2_QFD14 = 0x00004000, 770 RID2_QFD15 = 0x00008000, 771 RID2_QFD16 = 0x00010000, 772 RID2_QFD17 = 0x00020000, 773 RID2_RFFD = 0x80000000, 774}; 775 776/* TIE (R-Car Gen3 only) */ 777enum TIE_BIT { 778 TIE_FTS0 = 0x00000001, 779 TIE_FTS1 = 0x00000002, 780 TIE_FTS2 = 0x00000004, 781 TIE_FTS3 = 0x00000008, 782 TIE_TFUS = 0x00000100, 783 TIE_TFWS = 0x00000200, 784 TIE_MFUS = 0x00000400, 785 TIE_MFWS = 0x00000800, 786 TIE_TDPS0 = 0x00010000, 787 TIE_TDPS1 = 0x00020000, 788 TIE_TDPS2 = 0x00040000, 789 TIE_TDPS3 = 0x00080000, 790}; 791 792/* TID (R-Car Gen3 only) */ 793enum TID_BIT { 794 TID_FTD0 = 0x00000001, 795 TID_FTD1 = 0x00000002, 796 TID_FTD2 = 0x00000004, 797 TID_FTD3 = 0x00000008, 798 TID_TFUD = 0x00000100, 799 TID_TFWD = 0x00000200, 800 TID_MFUD = 0x00000400, 801 TID_MFWD = 0x00000800, 802 TID_TDPD0 = 0x00010000, 803 TID_TDPD1 = 0x00020000, 804 TID_TDPD2 = 0x00040000, 805 TID_TDPD3 = 0x00080000, 806}; 807 808/* ECMR */ 809enum ECMR_BIT { 810 ECMR_PRM = 0x00000001, 811 ECMR_DM = 0x00000002, 812 ECMR_TE = 0x00000020, 813 ECMR_RE = 0x00000040, 814 ECMR_MPDE = 0x00000200, 815 ECMR_TXF = 0x00010000, /* Documented for R-Car Gen3 only */ 816 ECMR_RXF = 0x00020000, 817 ECMR_PFR = 0x00040000, 818 ECMR_ZPF = 0x00080000, /* Documented for R-Car Gen3 and RZ/G2L */ 819 ECMR_RZPF = 0x00100000, 820 ECMR_DPAD = 0x00200000, 821 ECMR_RCSC = 0x00800000, 822 ECMR_RCPT = 0x02000000, /* Documented for RZ/G2L only */ 823 ECMR_TRCCM = 0x04000000, 824}; 825 826/* ECSR */ 827enum ECSR_BIT { 828 ECSR_ICD = 0x00000001, 829 ECSR_MPD = 0x00000002, 830 ECSR_LCHNG = 0x00000004, 831 ECSR_PHYI = 0x00000008, 832 ECSR_PFRI = 0x00000010, /* Documented for R-Car Gen3 and RZ/G2L */ 833}; 834 835/* ECSIPR */ 836enum ECSIPR_BIT { 837 ECSIPR_ICDIP = 0x00000001, 838 ECSIPR_MPDIP = 0x00000002, 839 ECSIPR_LCHNGIP = 0x00000004, 840}; 841 842/* PIR */ 843enum PIR_BIT { 844 PIR_MDC = 0x00000001, 845 PIR_MMD = 0x00000002, 846 PIR_MDO = 0x00000004, 847 PIR_MDI = 0x00000008, 848}; 849 850/* PSR */ 851enum PSR_BIT { 852 PSR_LMON = 0x00000001, 853}; 854 855/* PIPR */ 856enum PIPR_BIT { 857 PIPR_PHYIP = 0x00000001, 858}; 859 860/* MPR */ 861enum MPR_BIT { 862 MPR_MP = 0x0000ffff, 863}; 864 865/* GECMR */ 866enum GECMR_BIT { 867 GECMR_SPEED = 0x00000001, 868 GECMR_SPEED_100 = 0x00000000, 869 GECMR_SPEED_1000 = 0x00000001, 870 GBETH_GECMR_SPEED = 0x00000030, 871 GBETH_GECMR_SPEED_10 = 0x00000000, 872 GBETH_GECMR_SPEED_100 = 0x00000010, 873 GBETH_GECMR_SPEED_1000 = 0x00000020, 874}; 875 876/* The Ethernet AVB descriptor definitions. */ 877struct ravb_desc { 878 __le16 ds; /* Descriptor size */ 879 u8 cc; /* Content control MSBs (reserved) */ 880 u8 die_dt; /* Descriptor interrupt enable and type */ 881 __le32 dptr; /* Descriptor pointer */ 882}; 883 884#define DPTR_ALIGN 4 /* Required descriptor pointer alignment */ 885 886enum DIE_DT { 887 /* Frame data */ 888 DT_FMID = 0x40, 889 DT_FSTART = 0x50, 890 DT_FEND = 0x60, 891 DT_FSINGLE = 0x70, 892 /* Chain control */ 893 DT_LINK = 0x80, 894 DT_LINKFIX = 0x90, 895 DT_EOS = 0xa0, 896 /* HW/SW arbitration */ 897 DT_FEMPTY = 0xc0, 898 DT_FEMPTY_IS = 0xd0, 899 DT_FEMPTY_IC = 0xe0, 900 DT_FEMPTY_ND = 0xf0, 901 DT_LEMPTY = 0x20, 902 DT_EEMPTY = 0x30, 903}; 904 905struct ravb_rx_desc { 906 __le16 ds_cc; /* Descriptor size and content control LSBs */ 907 u8 msc; /* MAC status code */ 908 u8 die_dt; /* Descriptor interrupt enable and type */ 909 __le32 dptr; /* Descpriptor pointer */ 910}; 911 912struct ravb_ex_rx_desc { 913 __le16 ds_cc; /* Descriptor size and content control lower bits */ 914 u8 msc; /* MAC status code */ 915 u8 die_dt; /* Descriptor interrupt enable and type */ 916 __le32 dptr; /* Descpriptor pointer */ 917 __le32 ts_n; /* Timestampe nsec */ 918 __le32 ts_sl; /* Timestamp low */ 919 __le16 ts_sh; /* Timestamp high */ 920 __le16 res; /* Reserved bits */ 921}; 922 923enum RX_DS_CC_BIT { 924 RX_DS = 0x0fff, /* Data size */ 925 RX_TR = 0x1000, /* Truncation indication */ 926 RX_EI = 0x2000, /* Error indication */ 927 RX_PS = 0xc000, /* Padding selection */ 928}; 929 930/* E-MAC status code */ 931enum MSC_BIT { 932 MSC_CRC = 0x01, /* Frame CRC error */ 933 MSC_RFE = 0x02, /* Frame reception error (flagged by PHY) */ 934 MSC_RTSF = 0x04, /* Frame length error (frame too short) */ 935 MSC_RTLF = 0x08, /* Frame length error (frame too long) */ 936 MSC_FRE = 0x10, /* Fraction error (not a multiple of 8 bits) */ 937 MSC_CRL = 0x20, /* Carrier lost */ 938 MSC_CEEF = 0x40, /* Carrier extension error */ 939 MSC_MC = 0x80, /* Multicast frame reception */ 940}; 941 942struct ravb_tx_desc { 943 __le16 ds_tagl; /* Descriptor size and frame tag LSBs */ 944 u8 tagh_tsr; /* Frame tag MSBs and timestamp storage request bit */ 945 u8 die_dt; /* Descriptor interrupt enable and type */ 946 __le32 dptr; /* Descpriptor pointer */ 947}; 948 949enum TX_DS_TAGL_BIT { 950 TX_DS = 0x0fff, /* Data size */ 951 TX_TAGL = 0xf000, /* Frame tag LSBs */ 952}; 953 954enum TX_TAGH_TSR_BIT { 955 TX_TAGH = 0x3f, /* Frame tag MSBs */ 956 TX_TSR = 0x40, /* Timestamp storage request */ 957}; 958enum RAVB_QUEUE { 959 RAVB_BE = 0, /* Best Effort Queue */ 960 RAVB_NC, /* Network Control Queue */ 961}; 962 963enum CXR31_BIT { 964 CXR31_SEL_LINK0 = 0x00000001, 965 CXR31_SEL_LINK1 = 0x00000008, 966}; 967 968enum CSR0_BIT { 969 CSR0_TPE = 0x00000010, 970 CSR0_RPE = 0x00000020, 971}; 972 973#define DBAT_ENTRY_NUM 22 974#define RX_QUEUE_OFFSET 4 975#define NUM_RX_QUEUE 2 976#define NUM_TX_QUEUE 2 977 978#define RX_BUF_SZ (2048 - ETH_FCS_LEN + sizeof(__sum16)) 979 980#define GBETH_RX_BUFF_MAX 8192 981#define GBETH_RX_DESC_DATA_SIZE 4080 982 983struct ravb_tstamp_skb { 984 struct list_head list; 985 struct sk_buff *skb; 986 u16 tag; 987}; 988 989struct ravb_ptp_perout { 990 u32 target; 991 u32 period; 992}; 993 994#define N_EXT_TS 1 995#define N_PER_OUT 1 996 997struct ravb_ptp { 998 struct ptp_clock *clock; 999 struct ptp_clock_info info; 1000 u32 default_addend; 1001 u32 current_addend; 1002 int extts[N_EXT_TS]; 1003 struct ravb_ptp_perout perout[N_PER_OUT]; 1004}; 1005 1006struct ravb_hw_info { 1007 void (*rx_ring_free)(struct net_device *ndev, int q); 1008 void (*rx_ring_format)(struct net_device *ndev, int q); 1009 void *(*alloc_rx_desc)(struct net_device *ndev, int q); 1010 bool (*receive)(struct net_device *ndev, int *quota, int q); 1011 void (*set_rate)(struct net_device *ndev); 1012 int (*set_feature)(struct net_device *ndev, netdev_features_t features); 1013 int (*dmac_init)(struct net_device *ndev); 1014 void (*emac_init)(struct net_device *ndev); 1015 const char (*gstrings_stats)[ETH_GSTRING_LEN]; 1016 size_t gstrings_size; 1017 netdev_features_t net_hw_features; 1018 netdev_features_t net_features; 1019 int stats_len; 1020 size_t max_rx_len; 1021 u32 tccr_mask; 1022 u32 rx_max_buf_size; 1023 unsigned aligned_tx: 1; 1024 1025 /* hardware features */ 1026 unsigned internal_delay:1; /* AVB-DMAC has internal delays */ 1027 unsigned tx_counters:1; /* E-MAC has TX counters */ 1028 unsigned carrier_counters:1; /* E-MAC has carrier counters */ 1029 unsigned multi_irqs:1; /* AVB-DMAC and E-MAC has multiple irqs */ 1030 unsigned irq_en_dis:1; /* Has separate irq enable and disable regs */ 1031 unsigned err_mgmt_irqs:1; /* Line1 (Err) and Line2 (Mgmt) irqs are separate */ 1032 unsigned gptp:1; /* AVB-DMAC has gPTP support */ 1033 unsigned ccc_gac:1; /* AVB-DMAC has gPTP support active in config mode */ 1034 unsigned gptp_ref_clk:1; /* gPTP has separate reference clock */ 1035 unsigned nc_queues:1; /* AVB-DMAC has RX and TX NC queues */ 1036 unsigned magic_pkt:1; /* E-MAC supports magic packet detection */ 1037 unsigned half_duplex:1; /* E-MAC supports half duplex mode */ 1038}; 1039 1040struct ravb_private { 1041 struct net_device *ndev; 1042 struct platform_device *pdev; 1043 void __iomem *addr; 1044 struct clk *clk; 1045 struct clk *refclk; 1046 struct clk *gptp_clk; 1047 struct mdiobb_ctrl mdiobb; 1048 u32 num_rx_ring[NUM_RX_QUEUE]; 1049 u32 num_tx_ring[NUM_TX_QUEUE]; 1050 u32 desc_bat_size; 1051 dma_addr_t desc_bat_dma; 1052 struct ravb_desc *desc_bat; 1053 dma_addr_t rx_desc_dma[NUM_RX_QUEUE]; 1054 dma_addr_t tx_desc_dma[NUM_TX_QUEUE]; 1055 struct ravb_rx_desc *gbeth_rx_ring; 1056 struct ravb_ex_rx_desc *rx_ring[NUM_RX_QUEUE]; 1057 struct ravb_tx_desc *tx_ring[NUM_TX_QUEUE]; 1058 void *tx_align[NUM_TX_QUEUE]; 1059 struct sk_buff *rx_1st_skb; 1060 struct sk_buff **rx_skb[NUM_RX_QUEUE]; 1061 struct sk_buff **tx_skb[NUM_TX_QUEUE]; 1062 u32 rx_over_errors; 1063 u32 rx_fifo_errors; 1064 struct net_device_stats stats[NUM_RX_QUEUE]; 1065 u32 tstamp_tx_ctrl; 1066 u32 tstamp_rx_ctrl; 1067 struct list_head ts_skb_list; 1068 u32 ts_skb_tag; 1069 struct ravb_ptp ptp; 1070 spinlock_t lock; /* Register access lock */ 1071 u32 cur_rx[NUM_RX_QUEUE]; /* Consumer ring indices */ 1072 u32 dirty_rx[NUM_RX_QUEUE]; /* Producer ring indices */ 1073 u32 cur_tx[NUM_TX_QUEUE]; 1074 u32 dirty_tx[NUM_TX_QUEUE]; 1075 struct napi_struct napi[NUM_RX_QUEUE]; 1076 struct work_struct work; 1077 /* MII transceiver section. */ 1078 struct mii_bus *mii_bus; /* MDIO bus control */ 1079 int link; 1080 phy_interface_t phy_interface; 1081 int msg_enable; 1082 int speed; 1083 int emac_irq; 1084 int erra_irq; 1085 int mgmta_irq; 1086 int rx_irqs[NUM_RX_QUEUE]; 1087 int tx_irqs[NUM_TX_QUEUE]; 1088 1089 unsigned no_avb_link:1; 1090 unsigned avb_link_active_low:1; 1091 unsigned wol_enabled:1; 1092 unsigned rxcidm:1; /* RX Clock Internal Delay Mode */ 1093 unsigned txcidm:1; /* TX Clock Internal Delay Mode */ 1094 unsigned rgmii_override:1; /* Deprecated rgmii-*id behavior */ 1095 unsigned int num_tx_desc; /* TX descriptors per packet */ 1096 1097 int duplex; 1098 1099 const struct ravb_hw_info *info; 1100 struct reset_control *rstc; 1101}; 1102 1103static inline u32 ravb_read(struct net_device *ndev, enum ravb_reg reg) 1104{ 1105 struct ravb_private *priv = netdev_priv(ndev); 1106 1107 return ioread32(priv->addr + reg); 1108} 1109 1110static inline void ravb_write(struct net_device *ndev, u32 data, 1111 enum ravb_reg reg) 1112{ 1113 struct ravb_private *priv = netdev_priv(ndev); 1114 1115 iowrite32(data, priv->addr + reg); 1116} 1117 1118void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 1119 u32 set); 1120int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value); 1121 1122void ravb_ptp_interrupt(struct net_device *ndev); 1123void ravb_ptp_init(struct net_device *ndev, struct platform_device *pdev); 1124void ravb_ptp_stop(struct net_device *ndev); 1125 1126#endif /* #ifndef __RAVB_H__ */