common.h (16495B)
1/* SPDX-License-Identifier: GPL-2.0-only */ 2/******************************************************************************* 3 STMMAC Common Header File 4 5 Copyright (C) 2007-2009 STMicroelectronics Ltd 6 7 8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 9*******************************************************************************/ 10 11#ifndef __COMMON_H__ 12#define __COMMON_H__ 13 14#include <linux/etherdevice.h> 15#include <linux/netdevice.h> 16#include <linux/stmmac.h> 17#include <linux/phy.h> 18#include <linux/pcs/pcs-xpcs.h> 19#include <linux/module.h> 20#if IS_ENABLED(CONFIG_VLAN_8021Q) 21#define STMMAC_VLAN_TAG_USED 22#include <linux/if_vlan.h> 23#endif 24 25#include "descs.h" 26#include "hwif.h" 27#include "mmc.h" 28 29/* Synopsys Core versions */ 30#define DWMAC_CORE_3_40 0x34 31#define DWMAC_CORE_3_50 0x35 32#define DWMAC_CORE_4_00 0x40 33#define DWMAC_CORE_4_10 0x41 34#define DWMAC_CORE_5_00 0x50 35#define DWMAC_CORE_5_10 0x51 36#define DWMAC_CORE_5_20 0x52 37#define DWXGMAC_CORE_2_10 0x21 38#define DWXLGMAC_CORE_2_00 0x20 39 40/* Device ID */ 41#define DWXGMAC_ID 0x76 42#define DWXLGMAC_ID 0x27 43 44#define STMMAC_CHAN0 0 /* Always supported and default for all chips */ 45 46/* TX and RX Descriptor Length, these need to be power of two. 47 * TX descriptor length less than 64 may cause transmit queue timed out error. 48 * RX descriptor length less than 64 may cause inconsistent Rx chain error. 49 */ 50#define DMA_MIN_TX_SIZE 64 51#define DMA_MAX_TX_SIZE 1024 52#define DMA_DEFAULT_TX_SIZE 512 53#define DMA_MIN_RX_SIZE 64 54#define DMA_MAX_RX_SIZE 1024 55#define DMA_DEFAULT_RX_SIZE 512 56#define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1)) 57 58#undef FRAME_FILTER_DEBUG 59/* #define FRAME_FILTER_DEBUG */ 60 61struct stmmac_txq_stats { 62 unsigned long tx_pkt_n; 63 unsigned long tx_normal_irq_n; 64}; 65 66struct stmmac_rxq_stats { 67 unsigned long rx_pkt_n; 68 unsigned long rx_normal_irq_n; 69}; 70 71/* Extra statistic and debug information exposed by ethtool */ 72struct stmmac_extra_stats { 73 /* Transmit errors */ 74 unsigned long tx_underflow ____cacheline_aligned; 75 unsigned long tx_carrier; 76 unsigned long tx_losscarrier; 77 unsigned long vlan_tag; 78 unsigned long tx_deferred; 79 unsigned long tx_vlan; 80 unsigned long tx_jabber; 81 unsigned long tx_frame_flushed; 82 unsigned long tx_payload_error; 83 unsigned long tx_ip_header_error; 84 /* Receive errors */ 85 unsigned long rx_desc; 86 unsigned long sa_filter_fail; 87 unsigned long overflow_error; 88 unsigned long ipc_csum_error; 89 unsigned long rx_collision; 90 unsigned long rx_crc_errors; 91 unsigned long dribbling_bit; 92 unsigned long rx_length; 93 unsigned long rx_mii; 94 unsigned long rx_multicast; 95 unsigned long rx_gmac_overflow; 96 unsigned long rx_watchdog; 97 unsigned long da_rx_filter_fail; 98 unsigned long sa_rx_filter_fail; 99 unsigned long rx_missed_cntr; 100 unsigned long rx_overflow_cntr; 101 unsigned long rx_vlan; 102 unsigned long rx_split_hdr_pkt_n; 103 /* Tx/Rx IRQ error info */ 104 unsigned long tx_undeflow_irq; 105 unsigned long tx_process_stopped_irq; 106 unsigned long tx_jabber_irq; 107 unsigned long rx_overflow_irq; 108 unsigned long rx_buf_unav_irq; 109 unsigned long rx_process_stopped_irq; 110 unsigned long rx_watchdog_irq; 111 unsigned long tx_early_irq; 112 unsigned long fatal_bus_error_irq; 113 /* Tx/Rx IRQ Events */ 114 unsigned long rx_early_irq; 115 unsigned long threshold; 116 unsigned long tx_pkt_n; 117 unsigned long rx_pkt_n; 118 unsigned long normal_irq_n; 119 unsigned long rx_normal_irq_n; 120 unsigned long napi_poll; 121 unsigned long tx_normal_irq_n; 122 unsigned long tx_clean; 123 unsigned long tx_set_ic_bit; 124 unsigned long irq_receive_pmt_irq_n; 125 /* MMC info */ 126 unsigned long mmc_tx_irq_n; 127 unsigned long mmc_rx_irq_n; 128 unsigned long mmc_rx_csum_offload_irq_n; 129 /* EEE */ 130 unsigned long irq_tx_path_in_lpi_mode_n; 131 unsigned long irq_tx_path_exit_lpi_mode_n; 132 unsigned long irq_rx_path_in_lpi_mode_n; 133 unsigned long irq_rx_path_exit_lpi_mode_n; 134 unsigned long phy_eee_wakeup_error_n; 135 /* Extended RDES status */ 136 unsigned long ip_hdr_err; 137 unsigned long ip_payload_err; 138 unsigned long ip_csum_bypassed; 139 unsigned long ipv4_pkt_rcvd; 140 unsigned long ipv6_pkt_rcvd; 141 unsigned long no_ptp_rx_msg_type_ext; 142 unsigned long ptp_rx_msg_type_sync; 143 unsigned long ptp_rx_msg_type_follow_up; 144 unsigned long ptp_rx_msg_type_delay_req; 145 unsigned long ptp_rx_msg_type_delay_resp; 146 unsigned long ptp_rx_msg_type_pdelay_req; 147 unsigned long ptp_rx_msg_type_pdelay_resp; 148 unsigned long ptp_rx_msg_type_pdelay_follow_up; 149 unsigned long ptp_rx_msg_type_announce; 150 unsigned long ptp_rx_msg_type_management; 151 unsigned long ptp_rx_msg_pkt_reserved_type; 152 unsigned long ptp_frame_type; 153 unsigned long ptp_ver; 154 unsigned long timestamp_dropped; 155 unsigned long av_pkt_rcvd; 156 unsigned long av_tagged_pkt_rcvd; 157 unsigned long vlan_tag_priority_val; 158 unsigned long l3_filter_match; 159 unsigned long l4_filter_match; 160 unsigned long l3_l4_filter_no_match; 161 /* PCS */ 162 unsigned long irq_pcs_ane_n; 163 unsigned long irq_pcs_link_n; 164 unsigned long irq_rgmii_n; 165 unsigned long pcs_link; 166 unsigned long pcs_duplex; 167 unsigned long pcs_speed; 168 /* debug register */ 169 unsigned long mtl_tx_status_fifo_full; 170 unsigned long mtl_tx_fifo_not_empty; 171 unsigned long mmtl_fifo_ctrl; 172 unsigned long mtl_tx_fifo_read_ctrl_write; 173 unsigned long mtl_tx_fifo_read_ctrl_wait; 174 unsigned long mtl_tx_fifo_read_ctrl_read; 175 unsigned long mtl_tx_fifo_read_ctrl_idle; 176 unsigned long mac_tx_in_pause; 177 unsigned long mac_tx_frame_ctrl_xfer; 178 unsigned long mac_tx_frame_ctrl_idle; 179 unsigned long mac_tx_frame_ctrl_wait; 180 unsigned long mac_tx_frame_ctrl_pause; 181 unsigned long mac_gmii_tx_proto_engine; 182 unsigned long mtl_rx_fifo_fill_level_full; 183 unsigned long mtl_rx_fifo_fill_above_thresh; 184 unsigned long mtl_rx_fifo_fill_below_thresh; 185 unsigned long mtl_rx_fifo_fill_level_empty; 186 unsigned long mtl_rx_fifo_read_ctrl_flush; 187 unsigned long mtl_rx_fifo_read_ctrl_read_data; 188 unsigned long mtl_rx_fifo_read_ctrl_status; 189 unsigned long mtl_rx_fifo_read_ctrl_idle; 190 unsigned long mtl_rx_fifo_ctrl_active; 191 unsigned long mac_rx_frame_ctrl_fifo; 192 unsigned long mac_gmii_rx_proto_engine; 193 /* TSO */ 194 unsigned long tx_tso_frames; 195 unsigned long tx_tso_nfrags; 196 /* EST */ 197 unsigned long mtl_est_cgce; 198 unsigned long mtl_est_hlbs; 199 unsigned long mtl_est_hlbf; 200 unsigned long mtl_est_btre; 201 unsigned long mtl_est_btrlm; 202 /* per queue statistics */ 203 struct stmmac_txq_stats txq_stats[MTL_MAX_TX_QUEUES]; 204 struct stmmac_rxq_stats rxq_stats[MTL_MAX_RX_QUEUES]; 205}; 206 207/* Safety Feature statistics exposed by ethtool */ 208struct stmmac_safety_stats { 209 unsigned long mac_errors[32]; 210 unsigned long mtl_errors[32]; 211 unsigned long dma_errors[32]; 212}; 213 214/* Number of fields in Safety Stats */ 215#define STMMAC_SAFETY_FEAT_SIZE \ 216 (sizeof(struct stmmac_safety_stats) / sizeof(unsigned long)) 217 218/* CSR Frequency Access Defines*/ 219#define CSR_F_35M 35000000 220#define CSR_F_60M 60000000 221#define CSR_F_100M 100000000 222#define CSR_F_150M 150000000 223#define CSR_F_250M 250000000 224#define CSR_F_300M 300000000 225 226#define MAC_CSR_H_FRQ_MASK 0x20 227 228#define HASH_TABLE_SIZE 64 229#define PAUSE_TIME 0xffff 230 231/* Flow Control defines */ 232#define FLOW_OFF 0 233#define FLOW_RX 1 234#define FLOW_TX 2 235#define FLOW_AUTO (FLOW_TX | FLOW_RX) 236 237/* PCS defines */ 238#define STMMAC_PCS_RGMII (1 << 0) 239#define STMMAC_PCS_SGMII (1 << 1) 240#define STMMAC_PCS_TBI (1 << 2) 241#define STMMAC_PCS_RTBI (1 << 3) 242 243#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */ 244 245/* DAM HW feature register fields */ 246#define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */ 247#define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */ 248#define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */ 249#define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */ 250#define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */ 251#define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */ 252#define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */ 253#define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */ 254#define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */ 255#define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */ 256#define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */ 257#define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */ 258#define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */ 259#define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */ 260#define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */ 261#define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */ 262#define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */ 263#define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */ 264#define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */ 265#define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */ 266#define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */ 267#define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */ 268#define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */ 269/* Timestamping with Internal System Time */ 270#define DMA_HW_FEAT_INTTSEN 0x02000000 271#define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */ 272#define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */ 273#define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */ 274#define DEFAULT_DMA_PBL 8 275 276/* MSI defines */ 277#define STMMAC_MSI_VEC_MAX 32 278 279/* PCS status and mask defines */ 280#define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */ 281#define PCS_LINK_IRQ BIT(1) /* PCS Link */ 282#define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */ 283 284/* Max/Min RI Watchdog Timer count value */ 285#define MAX_DMA_RIWT 0xff 286#define MIN_DMA_RIWT 0x10 287#define DEF_DMA_RIWT 0xa0 288/* Tx coalesce parameters */ 289#define STMMAC_COAL_TX_TIMER 1000 290#define STMMAC_MAX_COAL_TX_TICK 100000 291#define STMMAC_TX_MAX_FRAMES 256 292#define STMMAC_TX_FRAMES 25 293#define STMMAC_RX_FRAMES 0 294 295/* Packets types */ 296enum packets_types { 297 PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */ 298 PACKET_PTPQ = 0x2, /* PTP Packets */ 299 PACKET_DCBCPQ = 0x3, /* DCB Control Packets */ 300 PACKET_UPQ = 0x4, /* Untagged Packets */ 301 PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */ 302}; 303 304/* Rx IPC status */ 305enum rx_frame_status { 306 good_frame = 0x0, 307 discard_frame = 0x1, 308 csum_none = 0x2, 309 llc_snap = 0x4, 310 dma_own = 0x8, 311 rx_not_ls = 0x10, 312}; 313 314/* Tx status */ 315enum tx_frame_status { 316 tx_done = 0x0, 317 tx_not_ls = 0x1, 318 tx_err = 0x2, 319 tx_dma_own = 0x4, 320 tx_err_bump_tc = 0x8, 321}; 322 323enum dma_irq_status { 324 tx_hard_error = 0x1, 325 tx_hard_error_bump_tc = 0x2, 326 handle_rx = 0x4, 327 handle_tx = 0x8, 328}; 329 330enum dma_irq_dir { 331 DMA_DIR_RX = 0x1, 332 DMA_DIR_TX = 0x2, 333 DMA_DIR_RXTX = 0x3, 334}; 335 336enum request_irq_err { 337 REQ_IRQ_ERR_ALL, 338 REQ_IRQ_ERR_TX, 339 REQ_IRQ_ERR_RX, 340 REQ_IRQ_ERR_SFTY_UE, 341 REQ_IRQ_ERR_SFTY_CE, 342 REQ_IRQ_ERR_LPI, 343 REQ_IRQ_ERR_WOL, 344 REQ_IRQ_ERR_MAC, 345 REQ_IRQ_ERR_NO, 346}; 347 348/* EEE and LPI defines */ 349#define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0) 350#define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1) 351#define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2) 352#define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3) 353 354/* FPE defines */ 355#define FPE_EVENT_UNKNOWN 0 356#define FPE_EVENT_TRSP BIT(0) 357#define FPE_EVENT_TVER BIT(1) 358#define FPE_EVENT_RRSP BIT(2) 359#define FPE_EVENT_RVER BIT(3) 360 361#define CORE_IRQ_MTL_RX_OVERFLOW BIT(8) 362 363/* Physical Coding Sublayer */ 364struct rgmii_adv { 365 unsigned int pause; 366 unsigned int duplex; 367 unsigned int lp_pause; 368 unsigned int lp_duplex; 369}; 370 371#define STMMAC_PCS_PAUSE 1 372#define STMMAC_PCS_ASYM_PAUSE 2 373 374/* DMA HW capabilities */ 375struct dma_features { 376 unsigned int mbps_10_100; 377 unsigned int mbps_1000; 378 unsigned int half_duplex; 379 unsigned int hash_filter; 380 unsigned int multi_addr; 381 unsigned int pcs; 382 unsigned int sma_mdio; 383 unsigned int pmt_remote_wake_up; 384 unsigned int pmt_magic_frame; 385 unsigned int rmon; 386 /* IEEE 1588-2002 */ 387 unsigned int time_stamp; 388 /* IEEE 1588-2008 */ 389 unsigned int atime_stamp; 390 /* 802.3az - Energy-Efficient Ethernet (EEE) */ 391 unsigned int eee; 392 unsigned int av; 393 unsigned int hash_tb_sz; 394 unsigned int tsoen; 395 /* TX and RX csum */ 396 unsigned int tx_coe; 397 unsigned int rx_coe; 398 unsigned int rx_coe_type1; 399 unsigned int rx_coe_type2; 400 unsigned int rxfifo_over_2048; 401 /* TX and RX number of channels */ 402 unsigned int number_rx_channel; 403 unsigned int number_tx_channel; 404 /* TX and RX number of queues */ 405 unsigned int number_rx_queues; 406 unsigned int number_tx_queues; 407 /* PPS output */ 408 unsigned int pps_out_num; 409 /* Alternate (enhanced) DESC mode */ 410 unsigned int enh_desc; 411 /* TX and RX FIFO sizes */ 412 unsigned int tx_fifo_size; 413 unsigned int rx_fifo_size; 414 /* Automotive Safety Package */ 415 unsigned int asp; 416 /* RX Parser */ 417 unsigned int frpsel; 418 unsigned int frpbs; 419 unsigned int frpes; 420 unsigned int addr64; 421 unsigned int rssen; 422 unsigned int vlhash; 423 unsigned int sphen; 424 unsigned int vlins; 425 unsigned int dvlan; 426 unsigned int l3l4fnum; 427 unsigned int arpoffsel; 428 /* TSN Features */ 429 unsigned int estwid; 430 unsigned int estdep; 431 unsigned int estsel; 432 unsigned int fpesel; 433 unsigned int tbssel; 434 /* Numbers of Auxiliary Snapshot Inputs */ 435 unsigned int aux_snapshot_n; 436}; 437 438/* RX Buffer size must be multiple of 4/8/16 bytes */ 439#define BUF_SIZE_16KiB 16368 440#define BUF_SIZE_8KiB 8188 441#define BUF_SIZE_4KiB 4096 442#define BUF_SIZE_2KiB 2048 443 444/* Power Down and WOL */ 445#define PMT_NOT_SUPPORTED 0 446#define PMT_SUPPORTED 1 447 448/* Common MAC defines */ 449#define MAC_CTRL_REG 0x00000000 /* MAC Control */ 450#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */ 451#define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */ 452 453/* Default LPI timers */ 454#define STMMAC_DEFAULT_LIT_LS 0x3E8 455#define STMMAC_DEFAULT_TWT_LS 0x1E 456#define STMMAC_ET_MAX 0xFFFFF 457 458#define STMMAC_CHAIN_MODE 0x1 459#define STMMAC_RING_MODE 0x2 460 461#define JUMBO_LEN 9000 462 463/* Receive Side Scaling */ 464#define STMMAC_RSS_HASH_KEY_SIZE 40 465#define STMMAC_RSS_MAX_TABLE_SIZE 256 466 467/* VLAN */ 468#define STMMAC_VLAN_NONE 0x0 469#define STMMAC_VLAN_REMOVE 0x1 470#define STMMAC_VLAN_INSERT 0x2 471#define STMMAC_VLAN_REPLACE 0x3 472 473extern const struct stmmac_desc_ops enh_desc_ops; 474extern const struct stmmac_desc_ops ndesc_ops; 475 476struct mac_device_info; 477 478extern const struct stmmac_hwtimestamp stmmac_ptp; 479extern const struct stmmac_mode_ops dwmac4_ring_mode_ops; 480 481struct mac_link { 482 u32 speed_mask; 483 u32 speed10; 484 u32 speed100; 485 u32 speed1000; 486 u32 speed2500; 487 u32 duplex; 488 struct { 489 u32 speed2500; 490 u32 speed5000; 491 u32 speed10000; 492 } xgmii; 493 struct { 494 u32 speed25000; 495 u32 speed40000; 496 u32 speed50000; 497 u32 speed100000; 498 } xlgmii; 499}; 500 501struct mii_regs { 502 unsigned int addr; /* MII Address */ 503 unsigned int data; /* MII Data */ 504 unsigned int addr_shift; /* MII address shift */ 505 unsigned int reg_shift; /* MII reg shift */ 506 unsigned int addr_mask; /* MII address mask */ 507 unsigned int reg_mask; /* MII reg mask */ 508 unsigned int clk_csr_shift; 509 unsigned int clk_csr_mask; 510}; 511 512struct mac_device_info { 513 const struct stmmac_ops *mac; 514 const struct stmmac_desc_ops *desc; 515 const struct stmmac_dma_ops *dma; 516 const struct stmmac_mode_ops *mode; 517 const struct stmmac_hwtimestamp *ptp; 518 const struct stmmac_tc_ops *tc; 519 const struct stmmac_mmc_ops *mmc; 520 struct dw_xpcs *xpcs; 521 struct mii_regs mii; /* MII register Addresses */ 522 struct mac_link link; 523 void __iomem *pcsr; /* vpointer to device CSRs */ 524 unsigned int multicast_filter_bins; 525 unsigned int unicast_filter_entries; 526 unsigned int mcast_bits_log2; 527 unsigned int rx_csum; 528 unsigned int pcs; 529 unsigned int pmt; 530 unsigned int ps; 531 unsigned int xlgmac; 532 unsigned int num_vlan; 533 u32 vlan_filter[32]; 534 unsigned int promisc; 535 bool vlan_fail_q_en; 536 u8 vlan_fail_q; 537}; 538 539struct stmmac_rx_routing { 540 u32 reg_mask; 541 u32 reg_shift; 542}; 543 544int dwmac100_setup(struct stmmac_priv *priv); 545int dwmac1000_setup(struct stmmac_priv *priv); 546int dwmac4_setup(struct stmmac_priv *priv); 547int dwxgmac2_setup(struct stmmac_priv *priv); 548int dwxlgmac2_setup(struct stmmac_priv *priv); 549 550void stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6], 551 unsigned int high, unsigned int low); 552void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, 553 unsigned int high, unsigned int low); 554void stmmac_set_mac(void __iomem *ioaddr, bool enable); 555 556void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, const u8 addr[6], 557 unsigned int high, unsigned int low); 558void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, 559 unsigned int high, unsigned int low); 560void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable); 561 562void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr); 563 564extern const struct stmmac_mode_ops ring_mode_ops; 565extern const struct stmmac_mode_ops chain_mode_ops; 566extern const struct stmmac_desc_ops dwmac4_desc_ops; 567 568#endif /* __COMMON_H__ */