cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dwmac5.h (5123B)


      1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
      2// Copyright (c) 2017 Synopsys, Inc. and/or its affiliates.
      3// stmmac Support for 5.xx Ethernet QoS cores
      4
      5#ifndef __DWMAC5_H__
      6#define __DWMAC5_H__
      7
      8#define MAC_DPP_FSM_INT_STATUS		0x00000140
      9#define MAC_AXI_SLV_DPE_ADDR_STATUS	0x00000144
     10#define MAC_FSM_CONTROL			0x00000148
     11#define PRTYEN				BIT(1)
     12#define TMOUTEN				BIT(0)
     13
     14#define MAC_FPE_CTRL_STS		0x00000234
     15#define TRSP				BIT(19)
     16#define TVER				BIT(18)
     17#define RRSP				BIT(17)
     18#define RVER				BIT(16)
     19#define SRSP				BIT(2)
     20#define SVER				BIT(1)
     21#define EFPE				BIT(0)
     22
     23#define MAC_PPS_CONTROL			0x00000b70
     24#define PPS_MAXIDX(x)			((((x) + 1) * 8) - 1)
     25#define PPS_MINIDX(x)			((x) * 8)
     26#define PPSx_MASK(x)			GENMASK(PPS_MAXIDX(x), PPS_MINIDX(x))
     27#define MCGRENx(x)			BIT(PPS_MAXIDX(x))
     28#define TRGTMODSELx(x, val)		\
     29	GENMASK(PPS_MAXIDX(x) - 1, PPS_MAXIDX(x) - 2) & \
     30	((val) << (PPS_MAXIDX(x) - 2))
     31#define PPSCMDx(x, val)			\
     32	GENMASK(PPS_MINIDX(x) + 3, PPS_MINIDX(x)) & \
     33	((val) << PPS_MINIDX(x))
     34#define PPSEN0				BIT(4)
     35#define MAC_PPSx_TARGET_TIME_SEC(x)	(0x00000b80 + ((x) * 0x10))
     36#define MAC_PPSx_TARGET_TIME_NSEC(x)	(0x00000b84 + ((x) * 0x10))
     37#define TRGTBUSY0			BIT(31)
     38#define TTSL0				GENMASK(30, 0)
     39#define MAC_PPSx_INTERVAL(x)		(0x00000b88 + ((x) * 0x10))
     40#define MAC_PPSx_WIDTH(x)		(0x00000b8c + ((x) * 0x10))
     41
     42#define MTL_EST_CONTROL			0x00000c50
     43#define PTOV				GENMASK(31, 24)
     44#define PTOV_SHIFT			24
     45#define SSWL				BIT(1)
     46#define EEST				BIT(0)
     47
     48#define MTL_EST_STATUS			0x00000c58
     49#define BTRL				GENMASK(11, 8)
     50#define BTRL_SHIFT			8
     51#define BTRL_MAX			(0xF << BTRL_SHIFT)
     52#define SWOL				BIT(7)
     53#define SWOL_SHIFT			7
     54#define CGCE				BIT(4)
     55#define HLBS				BIT(3)
     56#define HLBF				BIT(2)
     57#define BTRE				BIT(1)
     58#define SWLC				BIT(0)
     59
     60#define MTL_EST_SCH_ERR			0x00000c60
     61#define MTL_EST_FRM_SZ_ERR		0x00000c64
     62#define MTL_EST_FRM_SZ_CAP		0x00000c68
     63#define SZ_CAP_HBFS_MASK		GENMASK(14, 0)
     64#define SZ_CAP_HBFQ_SHIFT		16
     65#define SZ_CAP_HBFQ_MASK(_val)		({ typeof(_val) (val) = (_val);	\
     66					((val) > 4 ? GENMASK(18, 16) :	\
     67					 (val) > 2 ? GENMASK(17, 16) :	\
     68					 BIT(16)); })
     69
     70#define MTL_EST_INT_EN			0x00000c70
     71#define IECGCE				CGCE
     72#define IEHS				HLBS
     73#define IEHF				HLBF
     74#define IEBE				BTRE
     75#define IECC				SWLC
     76
     77#define MTL_EST_GCL_CONTROL		0x00000c80
     78#define BTR_LOW				0x0
     79#define BTR_HIGH			0x1
     80#define CTR_LOW				0x2
     81#define CTR_HIGH			0x3
     82#define TER				0x4
     83#define LLR				0x5
     84#define ADDR_SHIFT			8
     85#define GCRR				BIT(2)
     86#define SRWO				BIT(0)
     87#define MTL_EST_GCL_DATA		0x00000c84
     88
     89#define MTL_RXP_CONTROL_STATUS		0x00000ca0
     90#define RXPI				BIT(31)
     91#define NPE				GENMASK(23, 16)
     92#define NVE				GENMASK(7, 0)
     93#define MTL_RXP_IACC_CTRL_STATUS	0x00000cb0
     94#define STARTBUSY			BIT(31)
     95#define RXPEIEC				GENMASK(22, 21)
     96#define RXPEIEE				BIT(20)
     97#define WRRDN				BIT(16)
     98#define ADDR				GENMASK(15, 0)
     99#define MTL_RXP_IACC_DATA		0x00000cb4
    100#define MTL_ECC_CONTROL			0x00000cc0
    101#define MEEAO				BIT(8)
    102#define TSOEE				BIT(4)
    103#define MRXPEE				BIT(3)
    104#define MESTEE				BIT(2)
    105#define MRXEE				BIT(1)
    106#define MTXEE				BIT(0)
    107
    108#define MTL_SAFETY_INT_STATUS		0x00000cc4
    109#define MCSIS				BIT(31)
    110#define MEUIS				BIT(1)
    111#define MECIS				BIT(0)
    112#define MTL_ECC_INT_ENABLE		0x00000cc8
    113#define RPCEIE				BIT(12)
    114#define ECEIE				BIT(8)
    115#define RXCEIE				BIT(4)
    116#define TXCEIE				BIT(0)
    117#define MTL_ECC_INT_STATUS		0x00000ccc
    118#define MTL_DPP_CONTROL			0x00000ce0
    119#define EPSI				BIT(2)
    120#define OPE				BIT(1)
    121#define EDPP				BIT(0)
    122
    123#define DMA_SAFETY_INT_STATUS		0x00001080
    124#define MSUIS				BIT(29)
    125#define MSCIS				BIT(28)
    126#define DEUIS				BIT(1)
    127#define DECIS				BIT(0)
    128#define DMA_ECC_INT_ENABLE		0x00001084
    129#define TCEIE				BIT(0)
    130#define DMA_ECC_INT_STATUS		0x00001088
    131
    132/* EQoS version 5.xx VLAN Tag Filter Fail Packets Queuing */
    133#define GMAC_RXQ_CTRL4			0x00000094
    134#define GMAC_RXQCTRL_VFFQ_MASK		GENMASK(19, 17)
    135#define GMAC_RXQCTRL_VFFQ_SHIFT		17
    136#define GMAC_RXQCTRL_VFFQE		BIT(16)
    137
    138#define GMAC_INT_FPE_EN			BIT(17)
    139
    140int dwmac5_safety_feat_config(void __iomem *ioaddr, unsigned int asp,
    141			      struct stmmac_safety_feature_cfg *safety_cfg);
    142int dwmac5_safety_feat_irq_status(struct net_device *ndev,
    143		void __iomem *ioaddr, unsigned int asp,
    144		struct stmmac_safety_stats *stats);
    145int dwmac5_safety_feat_dump(struct stmmac_safety_stats *stats,
    146			int index, unsigned long *count, const char **desc);
    147int dwmac5_rxp_config(void __iomem *ioaddr, struct stmmac_tc_entry *entries,
    148		      unsigned int count);
    149int dwmac5_flex_pps_config(void __iomem *ioaddr, int index,
    150			   struct stmmac_pps_cfg *cfg, bool enable,
    151			   u32 sub_second_inc, u32 systime_flags);
    152int dwmac5_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg,
    153			 unsigned int ptp_rate);
    154void dwmac5_est_irq_status(void __iomem *ioaddr, struct net_device *dev,
    155			   struct stmmac_extra_stats *x, u32 txqcnt);
    156void dwmac5_fpe_configure(void __iomem *ioaddr, u32 num_txq, u32 num_rxq,
    157			  bool enable);
    158void dwmac5_fpe_send_mpacket(void __iomem *ioaddr,
    159			     enum stmmac_mpacket_type type);
    160int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev);
    161
    162#endif /* __DWMAC5_H__ */