ll_temac.h (13769B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2 3#ifndef XILINX_LL_TEMAC_H 4#define XILINX_LL_TEMAC_H 5 6#include <linux/netdevice.h> 7#include <linux/of.h> 8#include <linux/spinlock.h> 9 10#ifdef CONFIG_PPC_DCR 11#include <asm/dcr.h> 12#include <asm/dcr-regs.h> 13#endif 14 15/* packet size info */ 16#define XTE_HDR_SIZE 14 /* size of Ethernet header */ 17#define XTE_TRL_SIZE 4 /* size of Ethernet trailer (FCS) */ 18#define XTE_JUMBO_MTU 9000 19#define XTE_MAX_JUMBO_FRAME_SIZE (XTE_JUMBO_MTU + XTE_HDR_SIZE + XTE_TRL_SIZE) 20 21/* Configuration options */ 22 23/* Accept all incoming packets. 24 * This option defaults to disabled (cleared) */ 25#define XTE_OPTION_PROMISC (1 << 0) 26/* Jumbo frame support for Tx & Rx. 27 * This option defaults to disabled (cleared) */ 28#define XTE_OPTION_JUMBO (1 << 1) 29/* VLAN Rx & Tx frame support. 30 * This option defaults to disabled (cleared) */ 31#define XTE_OPTION_VLAN (1 << 2) 32/* Enable recognition of flow control frames on Rx 33 * This option defaults to enabled (set) */ 34#define XTE_OPTION_FLOW_CONTROL (1 << 4) 35/* Strip FCS and PAD from incoming frames. 36 * Note: PAD from VLAN frames is not stripped. 37 * This option defaults to disabled (set) */ 38#define XTE_OPTION_FCS_STRIP (1 << 5) 39/* Generate FCS field and add PAD automatically for outgoing frames. 40 * This option defaults to enabled (set) */ 41#define XTE_OPTION_FCS_INSERT (1 << 6) 42/* Enable Length/Type error checking for incoming frames. When this option is 43set, the MAC will filter frames that have a mismatched type/length field 44and if XTE_OPTION_REPORT_RXERR is set, the user is notified when these 45types of frames are encountered. When this option is cleared, the MAC will 46allow these types of frames to be received. 47This option defaults to enabled (set) */ 48#define XTE_OPTION_LENTYPE_ERR (1 << 7) 49/* Enable the transmitter. 50 * This option defaults to enabled (set) */ 51#define XTE_OPTION_TXEN (1 << 11) 52/* Enable the receiver 53* This option defaults to enabled (set) */ 54#define XTE_OPTION_RXEN (1 << 12) 55 56/* Default options set when device is initialized or reset */ 57#define XTE_OPTION_DEFAULTS \ 58 (XTE_OPTION_TXEN | \ 59 XTE_OPTION_FLOW_CONTROL | \ 60 XTE_OPTION_RXEN) 61 62/* XPS_LL_TEMAC SDMA registers definition */ 63 64#define TX_NXTDESC_PTR 0x00 /* r */ 65#define TX_CURBUF_ADDR 0x01 /* r */ 66#define TX_CURBUF_LENGTH 0x02 /* r */ 67#define TX_CURDESC_PTR 0x03 /* rw */ 68#define TX_TAILDESC_PTR 0x04 /* rw */ 69#define TX_CHNL_CTRL 0x05 /* rw */ 70/* 71 0:7 24:31 IRQTimeout 72 8:15 16:23 IRQCount 73 16:20 11:15 Reserved 74 21 10 0 75 22 9 UseIntOnEnd 76 23 8 LdIRQCnt 77 24 7 IRQEn 78 25:28 3:6 Reserved 79 29 2 IrqErrEn 80 30 1 IrqDlyEn 81 31 0 IrqCoalEn 82*/ 83#define CHNL_CTRL_IRQ_IOE (1 << 9) 84#define CHNL_CTRL_IRQ_EN (1 << 7) 85#define CHNL_CTRL_IRQ_ERR_EN (1 << 2) 86#define CHNL_CTRL_IRQ_DLY_EN (1 << 1) 87#define CHNL_CTRL_IRQ_COAL_EN (1 << 0) 88#define TX_IRQ_REG 0x06 /* rw */ 89/* 90 0:7 24:31 DltTmrValue 91 8:15 16:23 ClscCntrValue 92 16:17 14:15 Reserved 93 18:21 10:13 ClscCnt 94 22:23 8:9 DlyCnt 95 24:28 3::7 Reserved 96 29 2 ErrIrq 97 30 1 DlyIrq 98 31 0 CoalIrq 99 */ 100#define TX_CHNL_STS 0x07 /* r */ 101/* 102 0:9 22:31 Reserved 103 10 21 TailPErr 104 11 20 CmpErr 105 12 19 AddrErr 106 13 18 NxtPErr 107 14 17 CurPErr 108 15 16 BsyWr 109 16:23 8:15 Reserved 110 24 7 Error 111 25 6 IOE 112 26 5 SOE 113 27 4 Cmplt 114 28 3 SOP 115 29 2 EOP 116 30 1 EngBusy 117 31 0 Reserved 118*/ 119 120#define RX_NXTDESC_PTR 0x08 /* r */ 121#define RX_CURBUF_ADDR 0x09 /* r */ 122#define RX_CURBUF_LENGTH 0x0a /* r */ 123#define RX_CURDESC_PTR 0x0b /* rw */ 124#define RX_TAILDESC_PTR 0x0c /* rw */ 125#define RX_CHNL_CTRL 0x0d /* rw */ 126/* 127 0:7 24:31 IRQTimeout 128 8:15 16:23 IRQCount 129 16:20 11:15 Reserved 130 21 10 0 131 22 9 UseIntOnEnd 132 23 8 LdIRQCnt 133 24 7 IRQEn 134 25:28 3:6 Reserved 135 29 2 IrqErrEn 136 30 1 IrqDlyEn 137 31 0 IrqCoalEn 138 */ 139#define RX_IRQ_REG 0x0e /* rw */ 140#define IRQ_COAL (1 << 0) 141#define IRQ_DLY (1 << 1) 142#define IRQ_ERR (1 << 2) 143#define IRQ_DMAERR (1 << 7) /* this is not documented ??? */ 144/* 145 0:7 24:31 DltTmrValue 146 8:15 16:23 ClscCntrValue 147 16:17 14:15 Reserved 148 18:21 10:13 ClscCnt 149 22:23 8:9 DlyCnt 150 24:28 3::7 Reserved 151*/ 152#define RX_CHNL_STS 0x0f /* r */ 153#define CHNL_STS_ENGBUSY (1 << 1) 154#define CHNL_STS_EOP (1 << 2) 155#define CHNL_STS_SOP (1 << 3) 156#define CHNL_STS_CMPLT (1 << 4) 157#define CHNL_STS_SOE (1 << 5) 158#define CHNL_STS_IOE (1 << 6) 159#define CHNL_STS_ERR (1 << 7) 160 161#define CHNL_STS_BSYWR (1 << 16) 162#define CHNL_STS_CURPERR (1 << 17) 163#define CHNL_STS_NXTPERR (1 << 18) 164#define CHNL_STS_ADDRERR (1 << 19) 165#define CHNL_STS_CMPERR (1 << 20) 166#define CHNL_STS_TAILERR (1 << 21) 167/* 168 0:9 22:31 Reserved 169 10 21 TailPErr 170 11 20 CmpErr 171 12 19 AddrErr 172 13 18 NxtPErr 173 14 17 CurPErr 174 15 16 BsyWr 175 16:23 8:15 Reserved 176 24 7 Error 177 25 6 IOE 178 26 5 SOE 179 27 4 Cmplt 180 28 3 SOP 181 29 2 EOP 182 30 1 EngBusy 183 31 0 Reserved 184*/ 185 186#define DMA_CONTROL_REG 0x10 /* rw */ 187#define DMA_CONTROL_RST (1 << 0) 188#define DMA_TAIL_ENABLE (1 << 2) 189 190/* XPS_LL_TEMAC direct registers definition */ 191 192#define XTE_RAF0_OFFSET 0x00 193#define RAF0_RST (1 << 0) 194#define RAF0_MCSTREJ (1 << 1) 195#define RAF0_BCSTREJ (1 << 2) 196#define XTE_TPF0_OFFSET 0x04 197#define XTE_IFGP0_OFFSET 0x08 198#define XTE_ISR0_OFFSET 0x0c 199#define ISR0_HARDACSCMPLT (1 << 0) 200#define ISR0_AUTONEG (1 << 1) 201#define ISR0_RXCMPLT (1 << 2) 202#define ISR0_RXREJ (1 << 3) 203#define ISR0_RXFIFOOVR (1 << 4) 204#define ISR0_TXCMPLT (1 << 5) 205#define ISR0_RXDCMLCK (1 << 6) 206 207#define XTE_IPR0_OFFSET 0x10 208#define XTE_IER0_OFFSET 0x14 209 210#define XTE_MSW0_OFFSET 0x20 211#define XTE_LSW0_OFFSET 0x24 212#define XTE_CTL0_OFFSET 0x28 213#define XTE_RDY0_OFFSET 0x2c 214 215#define XTE_RSE_MIIM_RR_MASK 0x0002 216#define XTE_RSE_MIIM_WR_MASK 0x0004 217#define XTE_RSE_CFG_RR_MASK 0x0020 218#define XTE_RSE_CFG_WR_MASK 0x0040 219#define XTE_RDY0_HARD_ACS_RDY_MASK (0x10000) 220 221/* XPS_LL_TEMAC indirect registers offset definition */ 222 223#define XTE_RXC0_OFFSET 0x00000200 /* Rx configuration word 0 */ 224#define XTE_RXC1_OFFSET 0x00000240 /* Rx configuration word 1 */ 225#define XTE_RXC1_RXRST_MASK (1 << 31) /* Receiver reset */ 226#define XTE_RXC1_RXJMBO_MASK (1 << 30) /* Jumbo frame enable */ 227#define XTE_RXC1_RXFCS_MASK (1 << 29) /* FCS not stripped */ 228#define XTE_RXC1_RXEN_MASK (1 << 28) /* Receiver enable */ 229#define XTE_RXC1_RXVLAN_MASK (1 << 27) /* VLAN enable */ 230#define XTE_RXC1_RXHD_MASK (1 << 26) /* Half duplex */ 231#define XTE_RXC1_RXLT_MASK (1 << 25) /* Length/type check disable */ 232 233#define XTE_TXC_OFFSET 0x00000280 /* Tx configuration */ 234#define XTE_TXC_TXRST_MASK (1 << 31) /* Transmitter reset */ 235#define XTE_TXC_TXJMBO_MASK (1 << 30) /* Jumbo frame enable */ 236#define XTE_TXC_TXFCS_MASK (1 << 29) /* Generate FCS */ 237#define XTE_TXC_TXEN_MASK (1 << 28) /* Transmitter enable */ 238#define XTE_TXC_TXVLAN_MASK (1 << 27) /* VLAN enable */ 239#define XTE_TXC_TXHD_MASK (1 << 26) /* Half duplex */ 240 241#define XTE_FCC_OFFSET 0x000002C0 /* Flow control config */ 242#define XTE_FCC_RXFLO_MASK (1 << 29) /* Rx flow control enable */ 243#define XTE_FCC_TXFLO_MASK (1 << 30) /* Tx flow control enable */ 244 245#define XTE_EMCFG_OFFSET 0x00000300 /* EMAC configuration */ 246#define XTE_EMCFG_LINKSPD_MASK 0xC0000000 /* Link speed */ 247#define XTE_EMCFG_HOSTEN_MASK (1 << 26) /* Host interface enable */ 248#define XTE_EMCFG_LINKSPD_10 0x00000000 /* 10 Mbit LINKSPD_MASK */ 249#define XTE_EMCFG_LINKSPD_100 (1 << 30) /* 100 Mbit LINKSPD_MASK */ 250#define XTE_EMCFG_LINKSPD_1000 (1 << 31) /* 1000 Mbit LINKSPD_MASK */ 251 252#define XTE_GMIC_OFFSET 0x00000320 /* RGMII/SGMII config */ 253#define XTE_MC_OFFSET 0x00000340 /* MDIO configuration */ 254#define XTE_UAW0_OFFSET 0x00000380 /* Unicast address word 0 */ 255#define XTE_UAW1_OFFSET 0x00000384 /* Unicast address word 1 */ 256 257#define XTE_MAW0_OFFSET 0x00000388 /* Multicast addr word 0 */ 258#define XTE_MAW1_OFFSET 0x0000038C /* Multicast addr word 1 */ 259#define XTE_AFM_OFFSET 0x00000390 /* Promiscuous mode */ 260#define XTE_AFM_EPPRM_MASK (1 << 31) /* Promiscuous mode enable */ 261 262/* Interrupt Request status */ 263#define XTE_TIS_OFFSET 0x000003A0 264#define TIS_FRIS (1 << 0) 265#define TIS_MRIS (1 << 1) 266#define TIS_MWIS (1 << 2) 267#define TIS_ARIS (1 << 3) 268#define TIS_AWIS (1 << 4) 269#define TIS_CRIS (1 << 5) 270#define TIS_CWIS (1 << 6) 271 272#define XTE_TIE_OFFSET 0x000003A4 /* Interrupt enable */ 273 274/* MII Management Control register (MGTCR) */ 275#define XTE_MGTDR_OFFSET 0x000003B0 /* MII data */ 276#define XTE_MIIMAI_OFFSET 0x000003B4 /* MII control */ 277 278#define CNTLREG_WRITE_ENABLE_MASK 0x8000 279#define CNTLREG_EMAC1SEL_MASK 0x0400 280#define CNTLREG_ADDRESSCODE_MASK 0x03ff 281 282/* CDMAC descriptor status bit definitions */ 283 284#define STS_CTRL_APP0_ERR (1 << 31) 285#define STS_CTRL_APP0_IRQONEND (1 << 30) 286/* undocumented */ 287#define STS_CTRL_APP0_STOPONEND (1 << 29) 288#define STS_CTRL_APP0_CMPLT (1 << 28) 289#define STS_CTRL_APP0_SOP (1 << 27) 290#define STS_CTRL_APP0_EOP (1 << 26) 291#define STS_CTRL_APP0_ENGBUSY (1 << 25) 292/* undocumented */ 293#define STS_CTRL_APP0_ENGRST (1 << 24) 294 295#define TX_CONTROL_CALC_CSUM_MASK 1 296 297#define MULTICAST_CAM_TABLE_NUM 4 298 299/* TEMAC Synthesis features */ 300#define TEMAC_FEATURE_RX_CSUM (1 << 0) 301#define TEMAC_FEATURE_TX_CSUM (1 << 1) 302 303/* TX/RX CURDESC_PTR points to first descriptor */ 304/* TX/RX TAILDESC_PTR points to last descriptor in linked list */ 305 306/** 307 * struct cdmac_bd - LocalLink buffer descriptor format 308 * 309 * app0 bits: 310 * 0 Error 311 * 1 IrqOnEnd generate an interrupt at completion of DMA op 312 * 2 reserved 313 * 3 completed Current descriptor completed 314 * 4 SOP TX - marks first desc/ RX marks first desct 315 * 5 EOP TX marks last desc/RX marks last desc 316 * 6 EngBusy DMA is processing 317 * 7 reserved 318 * 8:31 application specific 319 */ 320struct cdmac_bd { 321 u32 next; /* Physical address of next buffer descriptor */ 322 u32 phys; 323 u32 len; 324 u32 app0; 325 u32 app1; /* TX start << 16 | insert */ 326 u32 app2; /* TX csum */ 327 u32 app3; 328 u32 app4; /* skb for TX length for RX */ 329}; 330 331struct temac_local { 332 struct net_device *ndev; 333 struct device *dev; 334 335 /* Connection to PHY device */ 336 struct device_node *phy_node; 337 /* For non-device-tree devices */ 338 char phy_name[MII_BUS_ID_SIZE + 3]; 339 phy_interface_t phy_interface; 340 341 /* MDIO bus data */ 342 struct mii_bus *mii_bus; /* MII bus reference */ 343 344 /* IO registers, dma functions and IRQs */ 345 void __iomem *regs; 346 void __iomem *sdma_regs; 347#ifdef CONFIG_PPC_DCR 348 dcr_host_t sdma_dcrs; 349#endif 350 u32 (*temac_ior)(struct temac_local *lp, int offset); 351 void (*temac_iow)(struct temac_local *lp, int offset, u32 value); 352 u32 (*dma_in)(struct temac_local *lp, int reg); 353 void (*dma_out)(struct temac_local *lp, int reg, u32 value); 354 355 int tx_irq; 356 int rx_irq; 357 int emac_num; 358 359 struct sk_buff **rx_skb; 360 spinlock_t rx_lock; 361 /* For synchronization of indirect register access. Must be 362 * shared mutex between interfaces in same TEMAC block. 363 */ 364 spinlock_t *indirect_lock; 365 u32 options; /* Current options word */ 366 int last_link; 367 unsigned int temac_features; 368 369 /* Buffer descriptors */ 370 struct cdmac_bd *tx_bd_v; 371 dma_addr_t tx_bd_p; 372 u32 tx_bd_num; 373 struct cdmac_bd *rx_bd_v; 374 dma_addr_t rx_bd_p; 375 u32 rx_bd_num; 376 int tx_bd_ci; 377 int tx_bd_tail; 378 int rx_bd_ci; 379 int rx_bd_tail; 380 381 /* DMA channel control setup */ 382 u8 coalesce_count_tx; 383 u8 coalesce_delay_tx; 384 u8 coalesce_count_rx; 385 u8 coalesce_delay_rx; 386 387 struct delayed_work restart_work; 388}; 389 390/* Wrappers for temac_ior()/temac_iow() function pointers above */ 391#define temac_ior(lp, o) ((lp)->temac_ior(lp, o)) 392#define temac_iow(lp, o, v) ((lp)->temac_iow(lp, o, v)) 393 394/* xilinx_temac.c */ 395int temac_indirect_busywait(struct temac_local *lp); 396u32 temac_indirect_in32(struct temac_local *lp, int reg); 397u32 temac_indirect_in32_locked(struct temac_local *lp, int reg); 398void temac_indirect_out32(struct temac_local *lp, int reg, u32 value); 399void temac_indirect_out32_locked(struct temac_local *lp, int reg, u32 value); 400 401/* xilinx_temac_mdio.c */ 402int temac_mdio_setup(struct temac_local *lp, struct platform_device *pdev); 403void temac_mdio_teardown(struct temac_local *lp); 404 405#endif /* XILINX_LL_TEMAC_H */