dp83822.c (17187B)
1// SPDX-License-Identifier: GPL-2.0 2/* Driver for the Texas Instruments DP83822, DP83825 and DP83826 PHYs. 3 * 4 * Copyright (C) 2017 Texas Instruments Inc. 5 */ 6 7#include <linux/ethtool.h> 8#include <linux/etherdevice.h> 9#include <linux/kernel.h> 10#include <linux/mii.h> 11#include <linux/module.h> 12#include <linux/of.h> 13#include <linux/phy.h> 14#include <linux/netdevice.h> 15 16#define DP83822_PHY_ID 0x2000a240 17#define DP83825S_PHY_ID 0x2000a140 18#define DP83825I_PHY_ID 0x2000a150 19#define DP83825CM_PHY_ID 0x2000a160 20#define DP83825CS_PHY_ID 0x2000a170 21#define DP83826C_PHY_ID 0x2000a130 22#define DP83826NC_PHY_ID 0x2000a110 23 24#define DP83822_DEVADDR 0x1f 25 26#define MII_DP83822_CTRL_2 0x0a 27#define MII_DP83822_PHYSTS 0x10 28#define MII_DP83822_PHYSCR 0x11 29#define MII_DP83822_MISR1 0x12 30#define MII_DP83822_MISR2 0x13 31#define MII_DP83822_FCSCR 0x14 32#define MII_DP83822_RCSR 0x17 33#define MII_DP83822_RESET_CTRL 0x1f 34#define MII_DP83822_GENCFG 0x465 35#define MII_DP83822_SOR1 0x467 36 37/* GENCFG */ 38#define DP83822_SIG_DET_LOW BIT(0) 39 40/* Control Register 2 bits */ 41#define DP83822_FX_ENABLE BIT(14) 42 43#define DP83822_HW_RESET BIT(15) 44#define DP83822_SW_RESET BIT(14) 45 46/* PHY STS bits */ 47#define DP83822_PHYSTS_DUPLEX BIT(2) 48#define DP83822_PHYSTS_10 BIT(1) 49#define DP83822_PHYSTS_LINK BIT(0) 50 51/* PHYSCR Register Fields */ 52#define DP83822_PHYSCR_INT_OE BIT(0) /* Interrupt Output Enable */ 53#define DP83822_PHYSCR_INTEN BIT(1) /* Interrupt Enable */ 54 55/* MISR1 bits */ 56#define DP83822_RX_ERR_HF_INT_EN BIT(0) 57#define DP83822_FALSE_CARRIER_HF_INT_EN BIT(1) 58#define DP83822_ANEG_COMPLETE_INT_EN BIT(2) 59#define DP83822_DUP_MODE_CHANGE_INT_EN BIT(3) 60#define DP83822_SPEED_CHANGED_INT_EN BIT(4) 61#define DP83822_LINK_STAT_INT_EN BIT(5) 62#define DP83822_ENERGY_DET_INT_EN BIT(6) 63#define DP83822_LINK_QUAL_INT_EN BIT(7) 64 65/* MISR2 bits */ 66#define DP83822_JABBER_DET_INT_EN BIT(0) 67#define DP83822_WOL_PKT_INT_EN BIT(1) 68#define DP83822_SLEEP_MODE_INT_EN BIT(2) 69#define DP83822_MDI_XOVER_INT_EN BIT(3) 70#define DP83822_LB_FIFO_INT_EN BIT(4) 71#define DP83822_PAGE_RX_INT_EN BIT(5) 72#define DP83822_ANEG_ERR_INT_EN BIT(6) 73#define DP83822_EEE_ERROR_CHANGE_INT_EN BIT(7) 74 75/* INT_STAT1 bits */ 76#define DP83822_WOL_INT_EN BIT(4) 77#define DP83822_WOL_INT_STAT BIT(12) 78 79#define MII_DP83822_RXSOP1 0x04a5 80#define MII_DP83822_RXSOP2 0x04a6 81#define MII_DP83822_RXSOP3 0x04a7 82 83/* WoL Registers */ 84#define MII_DP83822_WOL_CFG 0x04a0 85#define MII_DP83822_WOL_STAT 0x04a1 86#define MII_DP83822_WOL_DA1 0x04a2 87#define MII_DP83822_WOL_DA2 0x04a3 88#define MII_DP83822_WOL_DA3 0x04a4 89 90/* WoL bits */ 91#define DP83822_WOL_MAGIC_EN BIT(0) 92#define DP83822_WOL_SECURE_ON BIT(5) 93#define DP83822_WOL_EN BIT(7) 94#define DP83822_WOL_INDICATION_SEL BIT(8) 95#define DP83822_WOL_CLR_INDICATION BIT(11) 96 97/* RCSR bits */ 98#define DP83822_RGMII_MODE_EN BIT(9) 99#define DP83822_RX_CLK_SHIFT BIT(12) 100#define DP83822_TX_CLK_SHIFT BIT(11) 101 102/* SOR1 mode */ 103#define DP83822_STRAP_MODE1 0 104#define DP83822_STRAP_MODE2 BIT(0) 105#define DP83822_STRAP_MODE3 BIT(1) 106#define DP83822_STRAP_MODE4 GENMASK(1, 0) 107 108#define DP83822_COL_STRAP_MASK GENMASK(11, 10) 109#define DP83822_COL_SHIFT 10 110#define DP83822_RX_ER_STR_MASK GENMASK(9, 8) 111#define DP83822_RX_ER_SHIFT 8 112 113#define MII_DP83822_FIBER_ADVERTISE (ADVERTISED_TP | ADVERTISED_MII | \ 114 ADVERTISED_FIBRE | \ 115 ADVERTISED_Pause | ADVERTISED_Asym_Pause) 116 117struct dp83822_private { 118 bool fx_signal_det_low; 119 int fx_enabled; 120 u16 fx_sd_enable; 121}; 122 123static int dp83822_set_wol(struct phy_device *phydev, 124 struct ethtool_wolinfo *wol) 125{ 126 struct net_device *ndev = phydev->attached_dev; 127 u16 value; 128 const u8 *mac; 129 130 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) { 131 mac = (const u8 *)ndev->dev_addr; 132 133 if (!is_valid_ether_addr(mac)) 134 return -EINVAL; 135 136 /* MAC addresses start with byte 5, but stored in mac[0]. 137 * 822 PHYs store bytes 4|5, 2|3, 0|1 138 */ 139 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA1, 140 (mac[1] << 8) | mac[0]); 141 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA2, 142 (mac[3] << 8) | mac[2]); 143 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA3, 144 (mac[5] << 8) | mac[4]); 145 146 value = phy_read_mmd(phydev, DP83822_DEVADDR, 147 MII_DP83822_WOL_CFG); 148 if (wol->wolopts & WAKE_MAGIC) 149 value |= DP83822_WOL_MAGIC_EN; 150 else 151 value &= ~DP83822_WOL_MAGIC_EN; 152 153 if (wol->wolopts & WAKE_MAGICSECURE) { 154 phy_write_mmd(phydev, DP83822_DEVADDR, 155 MII_DP83822_RXSOP1, 156 (wol->sopass[1] << 8) | wol->sopass[0]); 157 phy_write_mmd(phydev, DP83822_DEVADDR, 158 MII_DP83822_RXSOP2, 159 (wol->sopass[3] << 8) | wol->sopass[2]); 160 phy_write_mmd(phydev, DP83822_DEVADDR, 161 MII_DP83822_RXSOP3, 162 (wol->sopass[5] << 8) | wol->sopass[4]); 163 value |= DP83822_WOL_SECURE_ON; 164 } else { 165 value &= ~DP83822_WOL_SECURE_ON; 166 } 167 168 /* Clear any pending WoL interrupt */ 169 phy_read(phydev, MII_DP83822_MISR2); 170 171 value |= DP83822_WOL_EN | DP83822_WOL_INDICATION_SEL | 172 DP83822_WOL_CLR_INDICATION; 173 174 return phy_write_mmd(phydev, DP83822_DEVADDR, 175 MII_DP83822_WOL_CFG, value); 176 } else { 177 return phy_clear_bits_mmd(phydev, DP83822_DEVADDR, 178 MII_DP83822_WOL_CFG, DP83822_WOL_EN); 179 } 180} 181 182static void dp83822_get_wol(struct phy_device *phydev, 183 struct ethtool_wolinfo *wol) 184{ 185 int value; 186 u16 sopass_val; 187 188 wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE); 189 wol->wolopts = 0; 190 191 value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG); 192 193 if (value & DP83822_WOL_MAGIC_EN) 194 wol->wolopts |= WAKE_MAGIC; 195 196 if (value & DP83822_WOL_SECURE_ON) { 197 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR, 198 MII_DP83822_RXSOP1); 199 wol->sopass[0] = (sopass_val & 0xff); 200 wol->sopass[1] = (sopass_val >> 8); 201 202 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR, 203 MII_DP83822_RXSOP2); 204 wol->sopass[2] = (sopass_val & 0xff); 205 wol->sopass[3] = (sopass_val >> 8); 206 207 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR, 208 MII_DP83822_RXSOP3); 209 wol->sopass[4] = (sopass_val & 0xff); 210 wol->sopass[5] = (sopass_val >> 8); 211 212 wol->wolopts |= WAKE_MAGICSECURE; 213 } 214 215 /* WoL is not enabled so set wolopts to 0 */ 216 if (!(value & DP83822_WOL_EN)) 217 wol->wolopts = 0; 218} 219 220static int dp83822_config_intr(struct phy_device *phydev) 221{ 222 struct dp83822_private *dp83822 = phydev->priv; 223 int misr_status; 224 int physcr_status; 225 int err; 226 227 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 228 misr_status = phy_read(phydev, MII_DP83822_MISR1); 229 if (misr_status < 0) 230 return misr_status; 231 232 misr_status |= (DP83822_LINK_STAT_INT_EN | 233 DP83822_ENERGY_DET_INT_EN | 234 DP83822_LINK_QUAL_INT_EN); 235 236 if (!dp83822->fx_enabled) 237 misr_status |= DP83822_ANEG_COMPLETE_INT_EN | 238 DP83822_DUP_MODE_CHANGE_INT_EN | 239 DP83822_SPEED_CHANGED_INT_EN; 240 241 242 err = phy_write(phydev, MII_DP83822_MISR1, misr_status); 243 if (err < 0) 244 return err; 245 246 misr_status = phy_read(phydev, MII_DP83822_MISR2); 247 if (misr_status < 0) 248 return misr_status; 249 250 misr_status |= (DP83822_JABBER_DET_INT_EN | 251 DP83822_SLEEP_MODE_INT_EN | 252 DP83822_LB_FIFO_INT_EN | 253 DP83822_PAGE_RX_INT_EN | 254 DP83822_EEE_ERROR_CHANGE_INT_EN); 255 256 if (!dp83822->fx_enabled) 257 misr_status |= DP83822_MDI_XOVER_INT_EN | 258 DP83822_ANEG_ERR_INT_EN | 259 DP83822_WOL_PKT_INT_EN; 260 261 err = phy_write(phydev, MII_DP83822_MISR2, misr_status); 262 if (err < 0) 263 return err; 264 265 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR); 266 if (physcr_status < 0) 267 return physcr_status; 268 269 physcr_status |= DP83822_PHYSCR_INT_OE | DP83822_PHYSCR_INTEN; 270 271 } else { 272 err = phy_write(phydev, MII_DP83822_MISR1, 0); 273 if (err < 0) 274 return err; 275 276 err = phy_write(phydev, MII_DP83822_MISR2, 0); 277 if (err < 0) 278 return err; 279 280 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR); 281 if (physcr_status < 0) 282 return physcr_status; 283 284 physcr_status &= ~DP83822_PHYSCR_INTEN; 285 } 286 287 return phy_write(phydev, MII_DP83822_PHYSCR, physcr_status); 288} 289 290static irqreturn_t dp83822_handle_interrupt(struct phy_device *phydev) 291{ 292 bool trigger_machine = false; 293 int irq_status; 294 295 /* The MISR1 and MISR2 registers are holding the interrupt status in 296 * the upper half (15:8), while the lower half (7:0) is used for 297 * controlling the interrupt enable state of those individual interrupt 298 * sources. To determine the possible interrupt sources, just read the 299 * MISR* register and use it directly to know which interrupts have 300 * been enabled previously or not. 301 */ 302 irq_status = phy_read(phydev, MII_DP83822_MISR1); 303 if (irq_status < 0) { 304 phy_error(phydev); 305 return IRQ_NONE; 306 } 307 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8)) 308 trigger_machine = true; 309 310 irq_status = phy_read(phydev, MII_DP83822_MISR2); 311 if (irq_status < 0) { 312 phy_error(phydev); 313 return IRQ_NONE; 314 } 315 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8)) 316 trigger_machine = true; 317 318 if (!trigger_machine) 319 return IRQ_NONE; 320 321 phy_trigger_machine(phydev); 322 323 return IRQ_HANDLED; 324} 325 326static int dp8382x_disable_wol(struct phy_device *phydev) 327{ 328 return phy_clear_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, 329 DP83822_WOL_EN | DP83822_WOL_MAGIC_EN | 330 DP83822_WOL_SECURE_ON); 331} 332 333static int dp83822_read_status(struct phy_device *phydev) 334{ 335 struct dp83822_private *dp83822 = phydev->priv; 336 int status = phy_read(phydev, MII_DP83822_PHYSTS); 337 int ctrl2; 338 int ret; 339 340 if (dp83822->fx_enabled) { 341 if (status & DP83822_PHYSTS_LINK) { 342 phydev->speed = SPEED_UNKNOWN; 343 phydev->duplex = DUPLEX_UNKNOWN; 344 } else { 345 ctrl2 = phy_read(phydev, MII_DP83822_CTRL_2); 346 if (ctrl2 < 0) 347 return ctrl2; 348 349 if (!(ctrl2 & DP83822_FX_ENABLE)) { 350 ret = phy_write(phydev, MII_DP83822_CTRL_2, 351 DP83822_FX_ENABLE | ctrl2); 352 if (ret < 0) 353 return ret; 354 } 355 } 356 } 357 358 ret = genphy_read_status(phydev); 359 if (ret) 360 return ret; 361 362 if (status < 0) 363 return status; 364 365 if (status & DP83822_PHYSTS_DUPLEX) 366 phydev->duplex = DUPLEX_FULL; 367 else 368 phydev->duplex = DUPLEX_HALF; 369 370 if (status & DP83822_PHYSTS_10) 371 phydev->speed = SPEED_10; 372 else 373 phydev->speed = SPEED_100; 374 375 return 0; 376} 377 378static int dp83822_config_init(struct phy_device *phydev) 379{ 380 struct dp83822_private *dp83822 = phydev->priv; 381 struct device *dev = &phydev->mdio.dev; 382 int rgmii_delay; 383 s32 rx_int_delay; 384 s32 tx_int_delay; 385 int err = 0; 386 int bmcr; 387 388 if (phy_interface_is_rgmii(phydev)) { 389 rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, 390 true); 391 392 if (rx_int_delay <= 0) 393 rgmii_delay = 0; 394 else 395 rgmii_delay = DP83822_RX_CLK_SHIFT; 396 397 tx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, 398 false); 399 if (tx_int_delay <= 0) 400 rgmii_delay &= ~DP83822_TX_CLK_SHIFT; 401 else 402 rgmii_delay |= DP83822_TX_CLK_SHIFT; 403 404 if (rgmii_delay) { 405 err = phy_set_bits_mmd(phydev, DP83822_DEVADDR, 406 MII_DP83822_RCSR, rgmii_delay); 407 if (err) 408 return err; 409 } 410 411 phy_set_bits_mmd(phydev, DP83822_DEVADDR, 412 MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); 413 } else { 414 phy_clear_bits_mmd(phydev, DP83822_DEVADDR, 415 MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); 416 } 417 418 if (dp83822->fx_enabled) { 419 err = phy_modify(phydev, MII_DP83822_CTRL_2, 420 DP83822_FX_ENABLE, 1); 421 if (err < 0) 422 return err; 423 424 /* Only allow advertising what this PHY supports */ 425 linkmode_and(phydev->advertising, phydev->advertising, 426 phydev->supported); 427 428 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 429 phydev->supported); 430 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 431 phydev->advertising); 432 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, 433 phydev->supported); 434 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT, 435 phydev->supported); 436 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, 437 phydev->advertising); 438 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT, 439 phydev->advertising); 440 441 /* Auto neg is not supported in fiber mode */ 442 bmcr = phy_read(phydev, MII_BMCR); 443 if (bmcr < 0) 444 return bmcr; 445 446 if (bmcr & BMCR_ANENABLE) { 447 err = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); 448 if (err < 0) 449 return err; 450 } 451 phydev->autoneg = AUTONEG_DISABLE; 452 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 453 phydev->supported); 454 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 455 phydev->advertising); 456 457 /* Setup fiber advertisement */ 458 err = phy_modify_changed(phydev, MII_ADVERTISE, 459 MII_DP83822_FIBER_ADVERTISE, 460 MII_DP83822_FIBER_ADVERTISE); 461 462 if (err < 0) 463 return err; 464 465 if (dp83822->fx_signal_det_low) { 466 err = phy_set_bits_mmd(phydev, DP83822_DEVADDR, 467 MII_DP83822_GENCFG, 468 DP83822_SIG_DET_LOW); 469 if (err) 470 return err; 471 } 472 } 473 return dp8382x_disable_wol(phydev); 474} 475 476static int dp8382x_config_init(struct phy_device *phydev) 477{ 478 return dp8382x_disable_wol(phydev); 479} 480 481static int dp83822_phy_reset(struct phy_device *phydev) 482{ 483 int err; 484 485 err = phy_write(phydev, MII_DP83822_RESET_CTRL, DP83822_SW_RESET); 486 if (err < 0) 487 return err; 488 489 return phydev->drv->config_init(phydev); 490} 491 492#ifdef CONFIG_OF_MDIO 493static int dp83822_of_init(struct phy_device *phydev) 494{ 495 struct dp83822_private *dp83822 = phydev->priv; 496 struct device *dev = &phydev->mdio.dev; 497 498 /* Signal detection for the PHY is only enabled if the FX_EN and the 499 * SD_EN pins are strapped. Signal detection can only enabled if FX_EN 500 * is strapped otherwise signal detection is disabled for the PHY. 501 */ 502 if (dp83822->fx_enabled && dp83822->fx_sd_enable) 503 dp83822->fx_signal_det_low = device_property_present(dev, 504 "ti,link-loss-low"); 505 if (!dp83822->fx_enabled) 506 dp83822->fx_enabled = device_property_present(dev, 507 "ti,fiber-mode"); 508 509 return 0; 510} 511#else 512static int dp83822_of_init(struct phy_device *phydev) 513{ 514 return 0; 515} 516#endif /* CONFIG_OF_MDIO */ 517 518static int dp83822_read_straps(struct phy_device *phydev) 519{ 520 struct dp83822_private *dp83822 = phydev->priv; 521 int fx_enabled, fx_sd_enable; 522 int val; 523 524 val = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_SOR1); 525 if (val < 0) 526 return val; 527 528 fx_enabled = (val & DP83822_COL_STRAP_MASK) >> DP83822_COL_SHIFT; 529 if (fx_enabled == DP83822_STRAP_MODE2 || 530 fx_enabled == DP83822_STRAP_MODE3) 531 dp83822->fx_enabled = 1; 532 533 if (dp83822->fx_enabled) { 534 fx_sd_enable = (val & DP83822_RX_ER_STR_MASK) >> DP83822_RX_ER_SHIFT; 535 if (fx_sd_enable == DP83822_STRAP_MODE3 || 536 fx_sd_enable == DP83822_STRAP_MODE4) 537 dp83822->fx_sd_enable = 1; 538 } 539 540 return 0; 541} 542 543static int dp83822_probe(struct phy_device *phydev) 544{ 545 struct dp83822_private *dp83822; 546 int ret; 547 548 dp83822 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83822), 549 GFP_KERNEL); 550 if (!dp83822) 551 return -ENOMEM; 552 553 phydev->priv = dp83822; 554 555 ret = dp83822_read_straps(phydev); 556 if (ret) 557 return ret; 558 559 dp83822_of_init(phydev); 560 561 if (dp83822->fx_enabled) 562 phydev->port = PORT_FIBRE; 563 564 return 0; 565} 566 567static int dp83822_suspend(struct phy_device *phydev) 568{ 569 int value; 570 571 value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG); 572 573 if (!(value & DP83822_WOL_EN)) 574 genphy_suspend(phydev); 575 576 return 0; 577} 578 579static int dp83822_resume(struct phy_device *phydev) 580{ 581 int value; 582 583 genphy_resume(phydev); 584 585 value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG); 586 587 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, value | 588 DP83822_WOL_CLR_INDICATION); 589 590 return 0; 591} 592 593#define DP83822_PHY_DRIVER(_id, _name) \ 594 { \ 595 PHY_ID_MATCH_MODEL(_id), \ 596 .name = (_name), \ 597 /* PHY_BASIC_FEATURES */ \ 598 .probe = dp83822_probe, \ 599 .soft_reset = dp83822_phy_reset, \ 600 .config_init = dp83822_config_init, \ 601 .read_status = dp83822_read_status, \ 602 .get_wol = dp83822_get_wol, \ 603 .set_wol = dp83822_set_wol, \ 604 .config_intr = dp83822_config_intr, \ 605 .handle_interrupt = dp83822_handle_interrupt, \ 606 .suspend = dp83822_suspend, \ 607 .resume = dp83822_resume, \ 608 } 609 610#define DP8382X_PHY_DRIVER(_id, _name) \ 611 { \ 612 PHY_ID_MATCH_MODEL(_id), \ 613 .name = (_name), \ 614 /* PHY_BASIC_FEATURES */ \ 615 .soft_reset = dp83822_phy_reset, \ 616 .config_init = dp8382x_config_init, \ 617 .get_wol = dp83822_get_wol, \ 618 .set_wol = dp83822_set_wol, \ 619 .config_intr = dp83822_config_intr, \ 620 .handle_interrupt = dp83822_handle_interrupt, \ 621 .suspend = dp83822_suspend, \ 622 .resume = dp83822_resume, \ 623 } 624 625static struct phy_driver dp83822_driver[] = { 626 DP83822_PHY_DRIVER(DP83822_PHY_ID, "TI DP83822"), 627 DP8382X_PHY_DRIVER(DP83825I_PHY_ID, "TI DP83825I"), 628 DP8382X_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"), 629 DP8382X_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"), 630 DP8382X_PHY_DRIVER(DP83825S_PHY_ID, "TI DP83825S"), 631 DP8382X_PHY_DRIVER(DP83825CM_PHY_ID, "TI DP83825M"), 632 DP8382X_PHY_DRIVER(DP83825CS_PHY_ID, "TI DP83825CS"), 633}; 634module_phy_driver(dp83822_driver); 635 636static struct mdio_device_id __maybe_unused dp83822_tbl[] = { 637 { DP83822_PHY_ID, 0xfffffff0 }, 638 { DP83825I_PHY_ID, 0xfffffff0 }, 639 { DP83826C_PHY_ID, 0xfffffff0 }, 640 { DP83826NC_PHY_ID, 0xfffffff0 }, 641 { DP83825S_PHY_ID, 0xfffffff0 }, 642 { DP83825CM_PHY_ID, 0xfffffff0 }, 643 { DP83825CS_PHY_ID, 0xfffffff0 }, 644 { }, 645}; 646MODULE_DEVICE_TABLE(mdio, dp83822_tbl); 647 648MODULE_DESCRIPTION("Texas Instruments DP83822 PHY driver"); 649MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); 650MODULE_LICENSE("GPL v2");