cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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et1011c.c (2433B)

      1// SPDX-License-Identifier: GPL-2.0+
      2/*
      3 * drivers/net/phy/et1011c.c
      4 *
      5 * Driver for LSI ET1011C PHYs
      6 *
      7 * Author: Chaithrika U S
      8 *
      9 * Copyright (c) 2008 Texas Instruments
     10 */
     11#include <linux/kernel.h>
     12#include <linux/string.h>
     13#include <linux/errno.h>
     14#include <linux/unistd.h>
     15#include <linux/interrupt.h>
     16#include <linux/init.h>
     17#include <linux/delay.h>
     18#include <linux/netdevice.h>
     19#include <linux/etherdevice.h>
     20#include <linux/skbuff.h>
     21#include <linux/spinlock.h>
     22#include <linux/mm.h>
     23#include <linux/module.h>
     24#include <linux/mii.h>
     25#include <linux/ethtool.h>
     26#include <linux/phy.h>
     27#include <linux/io.h>
     28#include <linux/uaccess.h>
     29#include <asm/irq.h>
     30
     31#define ET1011C_STATUS_REG	(0x1A)
     32#define ET1011C_CONFIG_REG	(0x16)
     33#define ET1011C_SPEED_MASK		(0x0300)
     34#define ET1011C_GIGABIT_SPEED		(0x0200)
     35#define ET1011C_TX_FIFO_MASK		(0x3000)
     36#define ET1011C_TX_FIFO_DEPTH_8		(0x0000)
     37#define ET1011C_TX_FIFO_DEPTH_16	(0x1000)
     38#define ET1011C_INTERFACE_MASK		(0x0007)
     39#define ET1011C_GMII_INTERFACE		(0x0002)
     40#define ET1011C_SYS_CLK_EN		(0x01 << 4)
     41
     42
     43MODULE_DESCRIPTION("LSI ET1011C PHY driver");
     44MODULE_AUTHOR("Chaithrika U S");
     45MODULE_LICENSE("GPL");
     46
     47static int et1011c_config_aneg(struct phy_device *phydev)
     48{
     49	int ctl = phy_read(phydev, MII_BMCR);
     50
     51	if (ctl < 0)
     52		return ctl;
     53	ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 |
     54		 BMCR_ANENABLE);
     55	/* First clear the PHY */
     56	phy_write(phydev, MII_BMCR, ctl | BMCR_RESET);
     57
     58	return genphy_config_aneg(phydev);
     59}
     60
     61static int et1011c_read_status(struct phy_device *phydev)
     62{
     63	static int speed;
     64	int ret;
     65	u32 val;
     66
     67	ret = genphy_read_status(phydev);
     68
     69	if (speed != phydev->speed) {
     70		speed = phydev->speed;
     71		val = phy_read(phydev, ET1011C_STATUS_REG);
     72		if ((val & ET1011C_SPEED_MASK) ==
     73					ET1011C_GIGABIT_SPEED) {
     74			val = phy_read(phydev, ET1011C_CONFIG_REG);
     75			val &= ~ET1011C_TX_FIFO_MASK;
     76			phy_write(phydev, ET1011C_CONFIG_REG, val |
     77					  ET1011C_GMII_INTERFACE |
     78					  ET1011C_SYS_CLK_EN |
     79					  ET1011C_TX_FIFO_DEPTH_16);
     80
     81		}
     82	}
     83	return ret;
     84}
     85
     86static struct phy_driver et1011c_driver[] = { {
     87	.phy_id		= 0x0282f014,
     88	.name		= "ET1011C",
     89	.phy_id_mask	= 0xfffffff0,
     90	/* PHY_GBIT_FEATURES */
     91	.config_aneg	= et1011c_config_aneg,
     92	.read_status	= et1011c_read_status,
     93} };
     94
     95module_phy_driver(et1011c_driver);
     96
     97static struct mdio_device_id __maybe_unused et1011c_tbl[] = {
     98	{ 0x0282f014, 0xfffffff0 },
     99	{ }
    100};
    101
    102MODULE_DEVICE_TABLE(mdio, et1011c_tbl);