realtek.c (25833B)
1// SPDX-License-Identifier: GPL-2.0+ 2/* drivers/net/phy/realtek.c 3 * 4 * Driver for Realtek PHYs 5 * 6 * Author: Johnson Leung <r58129@freescale.com> 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 */ 10#include <linux/bitops.h> 11#include <linux/of.h> 12#include <linux/phy.h> 13#include <linux/module.h> 14#include <linux/delay.h> 15 16#define RTL821x_PHYSR 0x11 17#define RTL821x_PHYSR_DUPLEX BIT(13) 18#define RTL821x_PHYSR_SPEED GENMASK(15, 14) 19 20#define RTL821x_INER 0x12 21#define RTL8211B_INER_INIT 0x6400 22#define RTL8211E_INER_LINK_STATUS BIT(10) 23#define RTL8211F_INER_LINK_STATUS BIT(4) 24 25#define RTL821x_INSR 0x13 26 27#define RTL821x_EXT_PAGE_SELECT 0x1e 28#define RTL821x_PAGE_SELECT 0x1f 29 30#define RTL8211F_PHYCR1 0x18 31#define RTL8211F_PHYCR2 0x19 32#define RTL8211F_INSR 0x1d 33 34#define RTL8211F_TX_DELAY BIT(8) 35#define RTL8211F_RX_DELAY BIT(3) 36 37#define RTL8211F_ALDPS_PLL_OFF BIT(1) 38#define RTL8211F_ALDPS_ENABLE BIT(2) 39#define RTL8211F_ALDPS_XTAL_OFF BIT(12) 40 41#define RTL8211E_CTRL_DELAY BIT(13) 42#define RTL8211E_TX_DELAY BIT(12) 43#define RTL8211E_RX_DELAY BIT(11) 44 45#define RTL8211F_CLKOUT_EN BIT(0) 46 47#define RTL8201F_ISR 0x1e 48#define RTL8201F_ISR_ANERR BIT(15) 49#define RTL8201F_ISR_DUPLEX BIT(13) 50#define RTL8201F_ISR_LINK BIT(11) 51#define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \ 52 RTL8201F_ISR_DUPLEX | \ 53 RTL8201F_ISR_LINK) 54#define RTL8201F_IER 0x13 55 56#define RTL8366RB_POWER_SAVE 0x15 57#define RTL8366RB_POWER_SAVE_ON BIT(12) 58 59#define RTL_SUPPORTS_5000FULL BIT(14) 60#define RTL_SUPPORTS_2500FULL BIT(13) 61#define RTL_SUPPORTS_10000FULL BIT(0) 62#define RTL_ADV_2500FULL BIT(7) 63#define RTL_LPADV_10000FULL BIT(11) 64#define RTL_LPADV_5000FULL BIT(6) 65#define RTL_LPADV_2500FULL BIT(5) 66 67#define RTL9000A_GINMR 0x14 68#define RTL9000A_GINMR_LINK_STATUS BIT(4) 69 70#define RTLGEN_SPEED_MASK 0x0630 71 72#define RTL_GENERIC_PHYID 0x001cc800 73 74MODULE_DESCRIPTION("Realtek PHY driver"); 75MODULE_AUTHOR("Johnson Leung"); 76MODULE_LICENSE("GPL"); 77 78struct rtl821x_priv { 79 u16 phycr1; 80 u16 phycr2; 81}; 82 83static int rtl821x_read_page(struct phy_device *phydev) 84{ 85 return __phy_read(phydev, RTL821x_PAGE_SELECT); 86} 87 88static int rtl821x_write_page(struct phy_device *phydev, int page) 89{ 90 return __phy_write(phydev, RTL821x_PAGE_SELECT, page); 91} 92 93static int rtl821x_probe(struct phy_device *phydev) 94{ 95 struct device *dev = &phydev->mdio.dev; 96 struct rtl821x_priv *priv; 97 int ret; 98 99 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 100 if (!priv) 101 return -ENOMEM; 102 103 ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR1); 104 if (ret < 0) 105 return ret; 106 107 priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF); 108 if (of_property_read_bool(dev->of_node, "realtek,aldps-enable")) 109 priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF; 110 111 ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR2); 112 if (ret < 0) 113 return ret; 114 115 priv->phycr2 = ret & RTL8211F_CLKOUT_EN; 116 if (of_property_read_bool(dev->of_node, "realtek,clkout-disable")) 117 priv->phycr2 &= ~RTL8211F_CLKOUT_EN; 118 119 phydev->priv = priv; 120 121 return 0; 122} 123 124static int rtl8201_ack_interrupt(struct phy_device *phydev) 125{ 126 int err; 127 128 err = phy_read(phydev, RTL8201F_ISR); 129 130 return (err < 0) ? err : 0; 131} 132 133static int rtl821x_ack_interrupt(struct phy_device *phydev) 134{ 135 int err; 136 137 err = phy_read(phydev, RTL821x_INSR); 138 139 return (err < 0) ? err : 0; 140} 141 142static int rtl8211f_ack_interrupt(struct phy_device *phydev) 143{ 144 int err; 145 146 err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR); 147 148 return (err < 0) ? err : 0; 149} 150 151static int rtl8201_config_intr(struct phy_device *phydev) 152{ 153 u16 val; 154 int err; 155 156 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 157 err = rtl8201_ack_interrupt(phydev); 158 if (err) 159 return err; 160 161 val = BIT(13) | BIT(12) | BIT(11); 162 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 163 } else { 164 val = 0; 165 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val); 166 if (err) 167 return err; 168 169 err = rtl8201_ack_interrupt(phydev); 170 } 171 172 return err; 173} 174 175static int rtl8211b_config_intr(struct phy_device *phydev) 176{ 177 int err; 178 179 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 180 err = rtl821x_ack_interrupt(phydev); 181 if (err) 182 return err; 183 184 err = phy_write(phydev, RTL821x_INER, 185 RTL8211B_INER_INIT); 186 } else { 187 err = phy_write(phydev, RTL821x_INER, 0); 188 if (err) 189 return err; 190 191 err = rtl821x_ack_interrupt(phydev); 192 } 193 194 return err; 195} 196 197static int rtl8211e_config_intr(struct phy_device *phydev) 198{ 199 int err; 200 201 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 202 err = rtl821x_ack_interrupt(phydev); 203 if (err) 204 return err; 205 206 err = phy_write(phydev, RTL821x_INER, 207 RTL8211E_INER_LINK_STATUS); 208 } else { 209 err = phy_write(phydev, RTL821x_INER, 0); 210 if (err) 211 return err; 212 213 err = rtl821x_ack_interrupt(phydev); 214 } 215 216 return err; 217} 218 219static int rtl8211f_config_intr(struct phy_device *phydev) 220{ 221 u16 val; 222 int err; 223 224 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 225 err = rtl8211f_ack_interrupt(phydev); 226 if (err) 227 return err; 228 229 val = RTL8211F_INER_LINK_STATUS; 230 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 231 } else { 232 val = 0; 233 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val); 234 if (err) 235 return err; 236 237 err = rtl8211f_ack_interrupt(phydev); 238 } 239 240 return err; 241} 242 243static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev) 244{ 245 int irq_status; 246 247 irq_status = phy_read(phydev, RTL8201F_ISR); 248 if (irq_status < 0) { 249 phy_error(phydev); 250 return IRQ_NONE; 251 } 252 253 if (!(irq_status & RTL8201F_ISR_MASK)) 254 return IRQ_NONE; 255 256 phy_trigger_machine(phydev); 257 258 return IRQ_HANDLED; 259} 260 261static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev) 262{ 263 int irq_status, irq_enabled; 264 265 irq_status = phy_read(phydev, RTL821x_INSR); 266 if (irq_status < 0) { 267 phy_error(phydev); 268 return IRQ_NONE; 269 } 270 271 irq_enabled = phy_read(phydev, RTL821x_INER); 272 if (irq_enabled < 0) { 273 phy_error(phydev); 274 return IRQ_NONE; 275 } 276 277 if (!(irq_status & irq_enabled)) 278 return IRQ_NONE; 279 280 phy_trigger_machine(phydev); 281 282 return IRQ_HANDLED; 283} 284 285static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev) 286{ 287 int irq_status; 288 289 irq_status = phy_read_paged(phydev, 0xa43, RTL8211F_INSR); 290 if (irq_status < 0) { 291 phy_error(phydev); 292 return IRQ_NONE; 293 } 294 295 if (!(irq_status & RTL8211F_INER_LINK_STATUS)) 296 return IRQ_NONE; 297 298 phy_trigger_machine(phydev); 299 300 return IRQ_HANDLED; 301} 302 303static int rtl8211_config_aneg(struct phy_device *phydev) 304{ 305 int ret; 306 307 ret = genphy_config_aneg(phydev); 308 if (ret < 0) 309 return ret; 310 311 /* Quirk was copied from vendor driver. Unfortunately it includes no 312 * description of the magic numbers. 313 */ 314 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) { 315 phy_write(phydev, 0x17, 0x2138); 316 phy_write(phydev, 0x0e, 0x0260); 317 } else { 318 phy_write(phydev, 0x17, 0x2108); 319 phy_write(phydev, 0x0e, 0x0000); 320 } 321 322 return 0; 323} 324 325static int rtl8211c_config_init(struct phy_device *phydev) 326{ 327 /* RTL8211C has an issue when operating in Gigabit slave mode */ 328 return phy_set_bits(phydev, MII_CTRL1000, 329 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); 330} 331 332static int rtl8211f_config_init(struct phy_device *phydev) 333{ 334 struct rtl821x_priv *priv = phydev->priv; 335 struct device *dev = &phydev->mdio.dev; 336 u16 val_txdly, val_rxdly; 337 int ret; 338 339 ret = phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1, 340 RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF, 341 priv->phycr1); 342 if (ret < 0) { 343 dev_err(dev, "aldps mode configuration failed: %pe\n", 344 ERR_PTR(ret)); 345 return ret; 346 } 347 348 switch (phydev->interface) { 349 case PHY_INTERFACE_MODE_RGMII: 350 val_txdly = 0; 351 val_rxdly = 0; 352 break; 353 354 case PHY_INTERFACE_MODE_RGMII_RXID: 355 val_txdly = 0; 356 val_rxdly = RTL8211F_RX_DELAY; 357 break; 358 359 case PHY_INTERFACE_MODE_RGMII_TXID: 360 val_txdly = RTL8211F_TX_DELAY; 361 val_rxdly = 0; 362 break; 363 364 case PHY_INTERFACE_MODE_RGMII_ID: 365 val_txdly = RTL8211F_TX_DELAY; 366 val_rxdly = RTL8211F_RX_DELAY; 367 break; 368 369 default: /* the rest of the modes imply leaving delay as is. */ 370 return 0; 371 } 372 373 ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY, 374 val_txdly); 375 if (ret < 0) { 376 dev_err(dev, "Failed to update the TX delay register\n"); 377 return ret; 378 } else if (ret) { 379 dev_dbg(dev, 380 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n", 381 val_txdly ? "Enabling" : "Disabling"); 382 } else { 383 dev_dbg(dev, 384 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n", 385 val_txdly ? "enabled" : "disabled"); 386 } 387 388 ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY, 389 val_rxdly); 390 if (ret < 0) { 391 dev_err(dev, "Failed to update the RX delay register\n"); 392 return ret; 393 } else if (ret) { 394 dev_dbg(dev, 395 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n", 396 val_rxdly ? "Enabling" : "Disabling"); 397 } else { 398 dev_dbg(dev, 399 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n", 400 val_rxdly ? "enabled" : "disabled"); 401 } 402 403 ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2, 404 RTL8211F_CLKOUT_EN, priv->phycr2); 405 if (ret < 0) { 406 dev_err(dev, "clkout configuration failed: %pe\n", 407 ERR_PTR(ret)); 408 return ret; 409 } 410 411 return genphy_soft_reset(phydev); 412} 413 414static int rtl821x_resume(struct phy_device *phydev) 415{ 416 int ret; 417 418 ret = genphy_resume(phydev); 419 if (ret < 0) 420 return ret; 421 422 msleep(20); 423 424 return 0; 425} 426 427static int rtl8211e_config_init(struct phy_device *phydev) 428{ 429 int ret = 0, oldpage; 430 u16 val; 431 432 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ 433 switch (phydev->interface) { 434 case PHY_INTERFACE_MODE_RGMII: 435 val = RTL8211E_CTRL_DELAY | 0; 436 break; 437 case PHY_INTERFACE_MODE_RGMII_ID: 438 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY; 439 break; 440 case PHY_INTERFACE_MODE_RGMII_RXID: 441 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY; 442 break; 443 case PHY_INTERFACE_MODE_RGMII_TXID: 444 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY; 445 break; 446 default: /* the rest of the modes imply leaving delays as is. */ 447 return 0; 448 } 449 450 /* According to a sample driver there is a 0x1c config register on the 451 * 0xa4 extension page (0x7) layout. It can be used to disable/enable 452 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. 453 * The configuration register definition: 454 * 14 = reserved 455 * 13 = Force Tx RX Delay controlled by bit12 bit11, 456 * 12 = RX Delay, 11 = TX Delay 457 * 10:0 = Test && debug settings reserved by realtek 458 */ 459 oldpage = phy_select_page(phydev, 0x7); 460 if (oldpage < 0) 461 goto err_restore_page; 462 463 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4); 464 if (ret) 465 goto err_restore_page; 466 467 ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY 468 | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY, 469 val); 470 471err_restore_page: 472 return phy_restore_page(phydev, oldpage, ret); 473} 474 475static int rtl8211b_suspend(struct phy_device *phydev) 476{ 477 phy_write(phydev, MII_MMD_DATA, BIT(9)); 478 479 return genphy_suspend(phydev); 480} 481 482static int rtl8211b_resume(struct phy_device *phydev) 483{ 484 phy_write(phydev, MII_MMD_DATA, 0); 485 486 return genphy_resume(phydev); 487} 488 489static int rtl8366rb_config_init(struct phy_device *phydev) 490{ 491 int ret; 492 493 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE, 494 RTL8366RB_POWER_SAVE_ON); 495 if (ret) { 496 dev_err(&phydev->mdio.dev, 497 "error enabling power management\n"); 498 } 499 500 return ret; 501} 502 503/* get actual speed to cover the downshift case */ 504static int rtlgen_get_speed(struct phy_device *phydev) 505{ 506 int val; 507 508 if (!phydev->link) 509 return 0; 510 511 val = phy_read_paged(phydev, 0xa43, 0x12); 512 if (val < 0) 513 return val; 514 515 switch (val & RTLGEN_SPEED_MASK) { 516 case 0x0000: 517 phydev->speed = SPEED_10; 518 break; 519 case 0x0010: 520 phydev->speed = SPEED_100; 521 break; 522 case 0x0020: 523 phydev->speed = SPEED_1000; 524 break; 525 case 0x0200: 526 phydev->speed = SPEED_10000; 527 break; 528 case 0x0210: 529 phydev->speed = SPEED_2500; 530 break; 531 case 0x0220: 532 phydev->speed = SPEED_5000; 533 break; 534 default: 535 break; 536 } 537 538 return 0; 539} 540 541static int rtlgen_read_status(struct phy_device *phydev) 542{ 543 int ret; 544 545 ret = genphy_read_status(phydev); 546 if (ret < 0) 547 return ret; 548 549 return rtlgen_get_speed(phydev); 550} 551 552static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 553{ 554 int ret; 555 556 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) { 557 rtl821x_write_page(phydev, 0xa5c); 558 ret = __phy_read(phydev, 0x12); 559 rtl821x_write_page(phydev, 0); 560 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) { 561 rtl821x_write_page(phydev, 0xa5d); 562 ret = __phy_read(phydev, 0x10); 563 rtl821x_write_page(phydev, 0); 564 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) { 565 rtl821x_write_page(phydev, 0xa5d); 566 ret = __phy_read(phydev, 0x11); 567 rtl821x_write_page(phydev, 0); 568 } else { 569 ret = -EOPNOTSUPP; 570 } 571 572 return ret; 573} 574 575static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 576 u16 val) 577{ 578 int ret; 579 580 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) { 581 rtl821x_write_page(phydev, 0xa5d); 582 ret = __phy_write(phydev, 0x10, val); 583 rtl821x_write_page(phydev, 0); 584 } else { 585 ret = -EOPNOTSUPP; 586 } 587 588 return ret; 589} 590 591static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) 592{ 593 int ret = rtlgen_read_mmd(phydev, devnum, regnum); 594 595 if (ret != -EOPNOTSUPP) 596 return ret; 597 598 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) { 599 rtl821x_write_page(phydev, 0xa6e); 600 ret = __phy_read(phydev, 0x16); 601 rtl821x_write_page(phydev, 0); 602 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) { 603 rtl821x_write_page(phydev, 0xa6d); 604 ret = __phy_read(phydev, 0x12); 605 rtl821x_write_page(phydev, 0); 606 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) { 607 rtl821x_write_page(phydev, 0xa6d); 608 ret = __phy_read(phydev, 0x10); 609 rtl821x_write_page(phydev, 0); 610 } 611 612 return ret; 613} 614 615static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, 616 u16 val) 617{ 618 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val); 619 620 if (ret != -EOPNOTSUPP) 621 return ret; 622 623 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) { 624 rtl821x_write_page(phydev, 0xa6d); 625 ret = __phy_write(phydev, 0x12, val); 626 rtl821x_write_page(phydev, 0); 627 } 628 629 return ret; 630} 631 632static int rtl822x_get_features(struct phy_device *phydev) 633{ 634 int val; 635 636 val = phy_read_paged(phydev, 0xa61, 0x13); 637 if (val < 0) 638 return val; 639 640 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 641 phydev->supported, val & RTL_SUPPORTS_2500FULL); 642 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 643 phydev->supported, val & RTL_SUPPORTS_5000FULL); 644 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 645 phydev->supported, val & RTL_SUPPORTS_10000FULL); 646 647 return genphy_read_abilities(phydev); 648} 649 650static int rtl822x_config_aneg(struct phy_device *phydev) 651{ 652 int ret = 0; 653 654 if (phydev->autoneg == AUTONEG_ENABLE) { 655 u16 adv2500 = 0; 656 657 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 658 phydev->advertising)) 659 adv2500 = RTL_ADV_2500FULL; 660 661 ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12, 662 RTL_ADV_2500FULL, adv2500); 663 if (ret < 0) 664 return ret; 665 } 666 667 return __genphy_config_aneg(phydev, ret); 668} 669 670static int rtl822x_read_status(struct phy_device *phydev) 671{ 672 int ret; 673 674 if (phydev->autoneg == AUTONEG_ENABLE) { 675 int lpadv = phy_read_paged(phydev, 0xa5d, 0x13); 676 677 if (lpadv < 0) 678 return lpadv; 679 680 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 681 phydev->lp_advertising, lpadv & RTL_LPADV_10000FULL); 682 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 683 phydev->lp_advertising, lpadv & RTL_LPADV_5000FULL); 684 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 685 phydev->lp_advertising, lpadv & RTL_LPADV_2500FULL); 686 } 687 688 ret = genphy_read_status(phydev); 689 if (ret < 0) 690 return ret; 691 692 return rtlgen_get_speed(phydev); 693} 694 695static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) 696{ 697 int val; 698 699 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61); 700 val = phy_read(phydev, 0x13); 701 phy_write(phydev, RTL821x_PAGE_SELECT, 0); 702 703 return val >= 0 && val & RTL_SUPPORTS_2500FULL; 704} 705 706static int rtlgen_match_phy_device(struct phy_device *phydev) 707{ 708 return phydev->phy_id == RTL_GENERIC_PHYID && 709 !rtlgen_supports_2_5gbps(phydev); 710} 711 712static int rtl8226_match_phy_device(struct phy_device *phydev) 713{ 714 return phydev->phy_id == RTL_GENERIC_PHYID && 715 rtlgen_supports_2_5gbps(phydev); 716} 717 718static int rtlgen_resume(struct phy_device *phydev) 719{ 720 int ret = genphy_resume(phydev); 721 722 /* Internal PHY's from RTL8168h up may not be instantly ready */ 723 msleep(20); 724 725 return ret; 726} 727 728static int rtl9000a_config_init(struct phy_device *phydev) 729{ 730 phydev->autoneg = AUTONEG_DISABLE; 731 phydev->speed = SPEED_100; 732 phydev->duplex = DUPLEX_FULL; 733 734 return 0; 735} 736 737static int rtl9000a_config_aneg(struct phy_device *phydev) 738{ 739 int ret; 740 u16 ctl = 0; 741 742 switch (phydev->master_slave_set) { 743 case MASTER_SLAVE_CFG_MASTER_FORCE: 744 ctl |= CTL1000_AS_MASTER; 745 break; 746 case MASTER_SLAVE_CFG_SLAVE_FORCE: 747 break; 748 case MASTER_SLAVE_CFG_UNKNOWN: 749 case MASTER_SLAVE_CFG_UNSUPPORTED: 750 return 0; 751 default: 752 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 753 return -EOPNOTSUPP; 754 } 755 756 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl); 757 if (ret == 1) 758 ret = genphy_soft_reset(phydev); 759 760 return ret; 761} 762 763static int rtl9000a_read_status(struct phy_device *phydev) 764{ 765 int ret; 766 767 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 768 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 769 770 ret = genphy_update_link(phydev); 771 if (ret) 772 return ret; 773 774 ret = phy_read(phydev, MII_CTRL1000); 775 if (ret < 0) 776 return ret; 777 if (ret & CTL1000_AS_MASTER) 778 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 779 else 780 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 781 782 ret = phy_read(phydev, MII_STAT1000); 783 if (ret < 0) 784 return ret; 785 if (ret & LPA_1000MSRES) 786 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 787 else 788 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 789 790 return 0; 791} 792 793static int rtl9000a_ack_interrupt(struct phy_device *phydev) 794{ 795 int err; 796 797 err = phy_read(phydev, RTL8211F_INSR); 798 799 return (err < 0) ? err : 0; 800} 801 802static int rtl9000a_config_intr(struct phy_device *phydev) 803{ 804 u16 val; 805 int err; 806 807 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 808 err = rtl9000a_ack_interrupt(phydev); 809 if (err) 810 return err; 811 812 val = (u16)~RTL9000A_GINMR_LINK_STATUS; 813 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 814 } else { 815 val = ~0; 816 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 817 if (err) 818 return err; 819 820 err = rtl9000a_ack_interrupt(phydev); 821 } 822 823 return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val); 824} 825 826static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev) 827{ 828 int irq_status; 829 830 irq_status = phy_read(phydev, RTL8211F_INSR); 831 if (irq_status < 0) { 832 phy_error(phydev); 833 return IRQ_NONE; 834 } 835 836 if (!(irq_status & RTL8211F_INER_LINK_STATUS)) 837 return IRQ_NONE; 838 839 phy_trigger_machine(phydev); 840 841 return IRQ_HANDLED; 842} 843 844static struct phy_driver realtek_drvs[] = { 845 { 846 PHY_ID_MATCH_EXACT(0x00008201), 847 .name = "RTL8201CP Ethernet", 848 .read_page = rtl821x_read_page, 849 .write_page = rtl821x_write_page, 850 }, { 851 PHY_ID_MATCH_EXACT(0x001cc816), 852 .name = "RTL8201F Fast Ethernet", 853 .config_intr = &rtl8201_config_intr, 854 .handle_interrupt = rtl8201_handle_interrupt, 855 .suspend = genphy_suspend, 856 .resume = genphy_resume, 857 .read_page = rtl821x_read_page, 858 .write_page = rtl821x_write_page, 859 }, { 860 PHY_ID_MATCH_MODEL(0x001cc880), 861 .name = "RTL8208 Fast Ethernet", 862 .read_mmd = genphy_read_mmd_unsupported, 863 .write_mmd = genphy_write_mmd_unsupported, 864 .suspend = genphy_suspend, 865 .resume = genphy_resume, 866 .read_page = rtl821x_read_page, 867 .write_page = rtl821x_write_page, 868 }, { 869 PHY_ID_MATCH_EXACT(0x001cc910), 870 .name = "RTL8211 Gigabit Ethernet", 871 .config_aneg = rtl8211_config_aneg, 872 .read_mmd = &genphy_read_mmd_unsupported, 873 .write_mmd = &genphy_write_mmd_unsupported, 874 .read_page = rtl821x_read_page, 875 .write_page = rtl821x_write_page, 876 }, { 877 PHY_ID_MATCH_EXACT(0x001cc912), 878 .name = "RTL8211B Gigabit Ethernet", 879 .config_intr = &rtl8211b_config_intr, 880 .handle_interrupt = rtl821x_handle_interrupt, 881 .read_mmd = &genphy_read_mmd_unsupported, 882 .write_mmd = &genphy_write_mmd_unsupported, 883 .suspend = rtl8211b_suspend, 884 .resume = rtl8211b_resume, 885 .read_page = rtl821x_read_page, 886 .write_page = rtl821x_write_page, 887 }, { 888 PHY_ID_MATCH_EXACT(0x001cc913), 889 .name = "RTL8211C Gigabit Ethernet", 890 .config_init = rtl8211c_config_init, 891 .read_mmd = &genphy_read_mmd_unsupported, 892 .write_mmd = &genphy_write_mmd_unsupported, 893 .read_page = rtl821x_read_page, 894 .write_page = rtl821x_write_page, 895 }, { 896 PHY_ID_MATCH_EXACT(0x001cc914), 897 .name = "RTL8211DN Gigabit Ethernet", 898 .config_intr = rtl8211e_config_intr, 899 .handle_interrupt = rtl821x_handle_interrupt, 900 .suspend = genphy_suspend, 901 .resume = genphy_resume, 902 .read_page = rtl821x_read_page, 903 .write_page = rtl821x_write_page, 904 }, { 905 PHY_ID_MATCH_EXACT(0x001cc915), 906 .name = "RTL8211E Gigabit Ethernet", 907 .config_init = &rtl8211e_config_init, 908 .config_intr = &rtl8211e_config_intr, 909 .handle_interrupt = rtl821x_handle_interrupt, 910 .suspend = genphy_suspend, 911 .resume = genphy_resume, 912 .read_page = rtl821x_read_page, 913 .write_page = rtl821x_write_page, 914 }, { 915 PHY_ID_MATCH_EXACT(0x001cc916), 916 .name = "RTL8211F Gigabit Ethernet", 917 .probe = rtl821x_probe, 918 .config_init = &rtl8211f_config_init, 919 .read_status = rtlgen_read_status, 920 .config_intr = &rtl8211f_config_intr, 921 .handle_interrupt = rtl8211f_handle_interrupt, 922 .suspend = genphy_suspend, 923 .resume = rtl821x_resume, 924 .read_page = rtl821x_read_page, 925 .write_page = rtl821x_write_page, 926 }, { 927 .name = "Generic FE-GE Realtek PHY", 928 .match_phy_device = rtlgen_match_phy_device, 929 .read_status = rtlgen_read_status, 930 .suspend = genphy_suspend, 931 .resume = rtlgen_resume, 932 .read_page = rtl821x_read_page, 933 .write_page = rtl821x_write_page, 934 .read_mmd = rtlgen_read_mmd, 935 .write_mmd = rtlgen_write_mmd, 936 }, { 937 .name = "RTL8226 2.5Gbps PHY", 938 .match_phy_device = rtl8226_match_phy_device, 939 .get_features = rtl822x_get_features, 940 .config_aneg = rtl822x_config_aneg, 941 .read_status = rtl822x_read_status, 942 .suspend = genphy_suspend, 943 .resume = rtlgen_resume, 944 .read_page = rtl821x_read_page, 945 .write_page = rtl821x_write_page, 946 .read_mmd = rtl822x_read_mmd, 947 .write_mmd = rtl822x_write_mmd, 948 }, { 949 PHY_ID_MATCH_EXACT(0x001cc840), 950 .name = "RTL8226B_RTL8221B 2.5Gbps PHY", 951 .get_features = rtl822x_get_features, 952 .config_aneg = rtl822x_config_aneg, 953 .read_status = rtl822x_read_status, 954 .suspend = genphy_suspend, 955 .resume = rtlgen_resume, 956 .read_page = rtl821x_read_page, 957 .write_page = rtl821x_write_page, 958 .read_mmd = rtl822x_read_mmd, 959 .write_mmd = rtl822x_write_mmd, 960 }, { 961 PHY_ID_MATCH_EXACT(0x001cc838), 962 .name = "RTL8226-CG 2.5Gbps PHY", 963 .get_features = rtl822x_get_features, 964 .config_aneg = rtl822x_config_aneg, 965 .read_status = rtl822x_read_status, 966 .suspend = genphy_suspend, 967 .resume = rtlgen_resume, 968 .read_page = rtl821x_read_page, 969 .write_page = rtl821x_write_page, 970 }, { 971 PHY_ID_MATCH_EXACT(0x001cc848), 972 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY", 973 .get_features = rtl822x_get_features, 974 .config_aneg = rtl822x_config_aneg, 975 .read_status = rtl822x_read_status, 976 .suspend = genphy_suspend, 977 .resume = rtlgen_resume, 978 .read_page = rtl821x_read_page, 979 .write_page = rtl821x_write_page, 980 }, { 981 PHY_ID_MATCH_EXACT(0x001cc849), 982 .name = "RTL8221B-VB-CG 2.5Gbps PHY", 983 .get_features = rtl822x_get_features, 984 .config_aneg = rtl822x_config_aneg, 985 .read_status = rtl822x_read_status, 986 .suspend = genphy_suspend, 987 .resume = rtlgen_resume, 988 .read_page = rtl821x_read_page, 989 .write_page = rtl821x_write_page, 990 }, { 991 PHY_ID_MATCH_EXACT(0x001cc84a), 992 .name = "RTL8221B-VM-CG 2.5Gbps PHY", 993 .get_features = rtl822x_get_features, 994 .config_aneg = rtl822x_config_aneg, 995 .read_status = rtl822x_read_status, 996 .suspend = genphy_suspend, 997 .resume = rtlgen_resume, 998 .read_page = rtl821x_read_page, 999 .write_page = rtl821x_write_page, 1000 }, { 1001 PHY_ID_MATCH_EXACT(0x001cc961), 1002 .name = "RTL8366RB Gigabit Ethernet", 1003 .config_init = &rtl8366rb_config_init, 1004 /* These interrupts are handled by the irq controller 1005 * embedded inside the RTL8366RB, they get unmasked when the 1006 * irq is requested and ACKed by reading the status register, 1007 * which is done by the irqchip code. 1008 */ 1009 .config_intr = genphy_no_config_intr, 1010 .handle_interrupt = genphy_handle_interrupt_no_ack, 1011 .suspend = genphy_suspend, 1012 .resume = genphy_resume, 1013 }, { 1014 PHY_ID_MATCH_EXACT(0x001ccb00), 1015 .name = "RTL9000AA_RTL9000AN Ethernet", 1016 .features = PHY_BASIC_T1_FEATURES, 1017 .config_init = rtl9000a_config_init, 1018 .config_aneg = rtl9000a_config_aneg, 1019 .read_status = rtl9000a_read_status, 1020 .config_intr = rtl9000a_config_intr, 1021 .handle_interrupt = rtl9000a_handle_interrupt, 1022 .suspend = genphy_suspend, 1023 .resume = genphy_resume, 1024 .read_page = rtl821x_read_page, 1025 .write_page = rtl821x_write_page, 1026 }, { 1027 PHY_ID_MATCH_EXACT(0x001cc942), 1028 .name = "RTL8365MB-VC Gigabit Ethernet", 1029 /* Interrupt handling analogous to RTL8366RB */ 1030 .config_intr = genphy_no_config_intr, 1031 .handle_interrupt = genphy_handle_interrupt_no_ack, 1032 .suspend = genphy_suspend, 1033 .resume = genphy_resume, 1034 }, 1035}; 1036 1037module_phy_driver(realtek_drvs); 1038 1039static const struct mdio_device_id __maybe_unused realtek_tbl[] = { 1040 { PHY_ID_MATCH_VENDOR(0x001cc800) }, 1041 { } 1042}; 1043 1044MODULE_DEVICE_TABLE(mdio, realtek_tbl);