vmxnet3_defs.h (22950B)
1/* 2 * Linux driver for VMware's vmxnet3 ethernet NIC. 3 * 4 * Copyright (C) 2008-2021, VMware, Inc. All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; version 2 of the License and no later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 13 * NON INFRINGEMENT. See the GNU General Public License for more 14 * details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * The full GNU General Public License is included in this distribution in 21 * the file called "COPYING". 22 * 23 * Maintained by: pv-drivers@vmware.com 24 * 25 */ 26 27#ifndef _VMXNET3_DEFS_H_ 28#define _VMXNET3_DEFS_H_ 29 30#include "upt1_defs.h" 31 32/* all registers are 32 bit wide */ 33/* BAR 1 */ 34enum { 35 VMXNET3_REG_VRRS = 0x0, /* Vmxnet3 Revision Report Selection */ 36 VMXNET3_REG_UVRS = 0x8, /* UPT Version Report Selection */ 37 VMXNET3_REG_DSAL = 0x10, /* Driver Shared Address Low */ 38 VMXNET3_REG_DSAH = 0x18, /* Driver Shared Address High */ 39 VMXNET3_REG_CMD = 0x20, /* Command */ 40 VMXNET3_REG_MACL = 0x28, /* MAC Address Low */ 41 VMXNET3_REG_MACH = 0x30, /* MAC Address High */ 42 VMXNET3_REG_ICR = 0x38, /* Interrupt Cause Register */ 43 VMXNET3_REG_ECR = 0x40 /* Event Cause Register */ 44}; 45 46/* BAR 0 */ 47enum { 48 VMXNET3_REG_IMR = 0x0, /* Interrupt Mask Register */ 49 VMXNET3_REG_TXPROD = 0x600, /* Tx Producer Index */ 50 VMXNET3_REG_RXPROD = 0x800, /* Rx Producer Index for ring 1 */ 51 VMXNET3_REG_RXPROD2 = 0xA00 /* Rx Producer Index for ring 2 */ 52}; 53 54#define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */ 55#define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */ 56 57#define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */ 58#define VMXNET3_REG_ALIGN_MASK 0x7 59 60/* I/O Mapped access to registers */ 61#define VMXNET3_IO_TYPE_PT 0 62#define VMXNET3_IO_TYPE_VD 1 63#define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF)) 64#define VMXNET3_IO_TYPE(addr) ((addr) >> 24) 65#define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF) 66 67enum { 68 VMXNET3_CMD_FIRST_SET = 0xCAFE0000, 69 VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET, 70 VMXNET3_CMD_QUIESCE_DEV, 71 VMXNET3_CMD_RESET_DEV, 72 VMXNET3_CMD_UPDATE_RX_MODE, 73 VMXNET3_CMD_UPDATE_MAC_FILTERS, 74 VMXNET3_CMD_UPDATE_VLAN_FILTERS, 75 VMXNET3_CMD_UPDATE_RSSIDT, 76 VMXNET3_CMD_UPDATE_IML, 77 VMXNET3_CMD_UPDATE_PMCFG, 78 VMXNET3_CMD_UPDATE_FEATURE, 79 VMXNET3_CMD_RESERVED1, 80 VMXNET3_CMD_LOAD_PLUGIN, 81 VMXNET3_CMD_RESERVED2, 82 VMXNET3_CMD_RESERVED3, 83 VMXNET3_CMD_SET_COALESCE, 84 VMXNET3_CMD_REGISTER_MEMREGS, 85 VMXNET3_CMD_SET_RSS_FIELDS, 86 87 VMXNET3_CMD_FIRST_GET = 0xF00D0000, 88 VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET, 89 VMXNET3_CMD_GET_STATS, 90 VMXNET3_CMD_GET_LINK, 91 VMXNET3_CMD_GET_PERM_MAC_LO, 92 VMXNET3_CMD_GET_PERM_MAC_HI, 93 VMXNET3_CMD_GET_DID_LO, 94 VMXNET3_CMD_GET_DID_HI, 95 VMXNET3_CMD_GET_DEV_EXTRA_INFO, 96 VMXNET3_CMD_GET_CONF_INTR, 97 VMXNET3_CMD_GET_RESERVED1, 98 VMXNET3_CMD_GET_TXDATA_DESC_SIZE, 99 VMXNET3_CMD_GET_COALESCE, 100 VMXNET3_CMD_GET_RSS_FIELDS, 101 VMXNET3_CMD_GET_RESERVED2, 102 VMXNET3_CMD_GET_RESERVED3, 103 VMXNET3_CMD_GET_MAX_QUEUES_CONF, 104}; 105 106/* 107 * Little Endian layout of bitfields - 108 * Byte 0 : 7.....len.....0 109 * Byte 1 : oco gen 13.len.8 110 * Byte 2 : 5.msscof.0 ext1 dtype 111 * Byte 3 : 13...msscof...6 112 * 113 * Big Endian layout of bitfields - 114 * Byte 0: 13...msscof...6 115 * Byte 1 : 5.msscof.0 ext1 dtype 116 * Byte 2 : oco gen 13.len.8 117 * Byte 3 : 7.....len.....0 118 * 119 * Thus, le32_to_cpu on the dword will allow the big endian driver to read 120 * the bit fields correctly. And cpu_to_le32 will convert bitfields 121 * bit fields written by big endian driver to format required by device. 122 */ 123 124struct Vmxnet3_TxDesc { 125 __le64 addr; 126 127#ifdef __BIG_ENDIAN_BITFIELD 128 u32 msscof:14; /* MSS, checksum offset, flags */ 129 u32 ext1:1; 130 u32 dtype:1; /* descriptor type */ 131 u32 oco:1; 132 u32 gen:1; /* generation bit */ 133 u32 len:14; 134#else 135 u32 len:14; 136 u32 gen:1; /* generation bit */ 137 u32 oco:1; 138 u32 dtype:1; /* descriptor type */ 139 u32 ext1:1; 140 u32 msscof:14; /* MSS, checksum offset, flags */ 141#endif /* __BIG_ENDIAN_BITFIELD */ 142 143#ifdef __BIG_ENDIAN_BITFIELD 144 u32 tci:16; /* Tag to Insert */ 145 u32 ti:1; /* VLAN Tag Insertion */ 146 u32 ext2:1; 147 u32 cq:1; /* completion request */ 148 u32 eop:1; /* End Of Packet */ 149 u32 om:2; /* offload mode */ 150 u32 hlen:10; /* header len */ 151#else 152 u32 hlen:10; /* header len */ 153 u32 om:2; /* offload mode */ 154 u32 eop:1; /* End Of Packet */ 155 u32 cq:1; /* completion request */ 156 u32 ext2:1; 157 u32 ti:1; /* VLAN Tag Insertion */ 158 u32 tci:16; /* Tag to Insert */ 159#endif /* __BIG_ENDIAN_BITFIELD */ 160}; 161 162/* TxDesc.OM values */ 163#define VMXNET3_OM_NONE 0 164#define VMXNET3_OM_ENCAP 1 165#define VMXNET3_OM_CSUM 2 166#define VMXNET3_OM_TSO 3 167 168/* fields in TxDesc we access w/o using bit fields */ 169#define VMXNET3_TXD_EOP_SHIFT 12 170#define VMXNET3_TXD_CQ_SHIFT 13 171#define VMXNET3_TXD_GEN_SHIFT 14 172#define VMXNET3_TXD_EOP_DWORD_SHIFT 3 173#define VMXNET3_TXD_GEN_DWORD_SHIFT 2 174 175#define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT) 176#define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT) 177#define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT) 178 179#define VMXNET3_HDR_COPY_SIZE 128 180 181 182struct Vmxnet3_TxDataDesc { 183 u8 data[VMXNET3_HDR_COPY_SIZE]; 184}; 185 186typedef u8 Vmxnet3_RxDataDesc; 187 188#define VMXNET3_TCD_GEN_SHIFT 31 189#define VMXNET3_TCD_GEN_SIZE 1 190#define VMXNET3_TCD_TXIDX_SHIFT 0 191#define VMXNET3_TCD_TXIDX_SIZE 12 192#define VMXNET3_TCD_GEN_DWORD_SHIFT 3 193 194struct Vmxnet3_TxCompDesc { 195 u32 txdIdx:12; /* Index of the EOP TxDesc */ 196 u32 ext1:20; 197 198 __le32 ext2; 199 __le32 ext3; 200 201 u32 rsvd:24; 202 u32 type:7; /* completion type */ 203 u32 gen:1; /* generation bit */ 204}; 205 206struct Vmxnet3_RxDesc { 207 __le64 addr; 208 209#ifdef __BIG_ENDIAN_BITFIELD 210 u32 gen:1; /* Generation bit */ 211 u32 rsvd:15; 212 u32 dtype:1; /* Descriptor type */ 213 u32 btype:1; /* Buffer Type */ 214 u32 len:14; 215#else 216 u32 len:14; 217 u32 btype:1; /* Buffer Type */ 218 u32 dtype:1; /* Descriptor type */ 219 u32 rsvd:15; 220 u32 gen:1; /* Generation bit */ 221#endif 222 u32 ext1; 223}; 224 225/* values of RXD.BTYPE */ 226#define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */ 227#define VMXNET3_RXD_BTYPE_BODY 1 /* body only */ 228 229/* fields in RxDesc we access w/o using bit fields */ 230#define VMXNET3_RXD_BTYPE_SHIFT 14 231#define VMXNET3_RXD_GEN_SHIFT 31 232 233#define VMXNET3_RCD_HDR_INNER_SHIFT 13 234 235struct Vmxnet3_RxCompDesc { 236#ifdef __BIG_ENDIAN_BITFIELD 237 u32 ext2:1; 238 u32 cnc:1; /* Checksum Not Calculated */ 239 u32 rssType:4; /* RSS hash type used */ 240 u32 rqID:10; /* rx queue/ring ID */ 241 u32 sop:1; /* Start of Packet */ 242 u32 eop:1; /* End of Packet */ 243 u32 ext1:2; 244 u32 rxdIdx:12; /* Index of the RxDesc */ 245#else 246 u32 rxdIdx:12; /* Index of the RxDesc */ 247 u32 ext1:2; 248 u32 eop:1; /* End of Packet */ 249 u32 sop:1; /* Start of Packet */ 250 u32 rqID:10; /* rx queue/ring ID */ 251 u32 rssType:4; /* RSS hash type used */ 252 u32 cnc:1; /* Checksum Not Calculated */ 253 u32 ext2:1; 254#endif /* __BIG_ENDIAN_BITFIELD */ 255 256 __le32 rssHash; /* RSS hash value */ 257 258#ifdef __BIG_ENDIAN_BITFIELD 259 u32 tci:16; /* Tag stripped */ 260 u32 ts:1; /* Tag is stripped */ 261 u32 err:1; /* Error */ 262 u32 len:14; /* data length */ 263#else 264 u32 len:14; /* data length */ 265 u32 err:1; /* Error */ 266 u32 ts:1; /* Tag is stripped */ 267 u32 tci:16; /* Tag stripped */ 268#endif /* __BIG_ENDIAN_BITFIELD */ 269 270 271#ifdef __BIG_ENDIAN_BITFIELD 272 u32 gen:1; /* generation bit */ 273 u32 type:7; /* completion type */ 274 u32 fcs:1; /* Frame CRC correct */ 275 u32 frg:1; /* IP Fragment */ 276 u32 v4:1; /* IPv4 */ 277 u32 v6:1; /* IPv6 */ 278 u32 ipc:1; /* IP Checksum Correct */ 279 u32 tcp:1; /* TCP packet */ 280 u32 udp:1; /* UDP packet */ 281 u32 tuc:1; /* TCP/UDP Checksum Correct */ 282 u32 csum:16; 283#else 284 u32 csum:16; 285 u32 tuc:1; /* TCP/UDP Checksum Correct */ 286 u32 udp:1; /* UDP packet */ 287 u32 tcp:1; /* TCP packet */ 288 u32 ipc:1; /* IP Checksum Correct */ 289 u32 v6:1; /* IPv6 */ 290 u32 v4:1; /* IPv4 */ 291 u32 frg:1; /* IP Fragment */ 292 u32 fcs:1; /* Frame CRC correct */ 293 u32 type:7; /* completion type */ 294 u32 gen:1; /* generation bit */ 295#endif /* __BIG_ENDIAN_BITFIELD */ 296}; 297 298struct Vmxnet3_RxCompDescExt { 299 __le32 dword1; 300 u8 segCnt; /* Number of aggregated packets */ 301 u8 dupAckCnt; /* Number of duplicate Acks */ 302 __le16 tsDelta; /* TCP timestamp difference */ 303 __le32 dword2; 304#ifdef __BIG_ENDIAN_BITFIELD 305 u32 gen:1; /* generation bit */ 306 u32 type:7; /* completion type */ 307 u32 fcs:1; /* Frame CRC correct */ 308 u32 frg:1; /* IP Fragment */ 309 u32 v4:1; /* IPv4 */ 310 u32 v6:1; /* IPv6 */ 311 u32 ipc:1; /* IP Checksum Correct */ 312 u32 tcp:1; /* TCP packet */ 313 u32 udp:1; /* UDP packet */ 314 u32 tuc:1; /* TCP/UDP Checksum Correct */ 315 u32 mss:16; 316#else 317 u32 mss:16; 318 u32 tuc:1; /* TCP/UDP Checksum Correct */ 319 u32 udp:1; /* UDP packet */ 320 u32 tcp:1; /* TCP packet */ 321 u32 ipc:1; /* IP Checksum Correct */ 322 u32 v6:1; /* IPv6 */ 323 u32 v4:1; /* IPv4 */ 324 u32 frg:1; /* IP Fragment */ 325 u32 fcs:1; /* Frame CRC correct */ 326 u32 type:7; /* completion type */ 327 u32 gen:1; /* generation bit */ 328#endif /* __BIG_ENDIAN_BITFIELD */ 329}; 330 331 332/* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */ 333#define VMXNET3_RCD_TUC_SHIFT 16 334#define VMXNET3_RCD_IPC_SHIFT 19 335 336/* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */ 337#define VMXNET3_RCD_TYPE_SHIFT 56 338#define VMXNET3_RCD_GEN_SHIFT 63 339 340/* csum OK for TCP/UDP pkts over IP */ 341#define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | \ 342 1 << VMXNET3_RCD_IPC_SHIFT) 343#define VMXNET3_TXD_GEN_SIZE 1 344#define VMXNET3_TXD_EOP_SIZE 1 345 346/* value of RxCompDesc.rssType */ 347#define VMXNET3_RCD_RSS_TYPE_NONE 0 348#define VMXNET3_RCD_RSS_TYPE_IPV4 1 349#define VMXNET3_RCD_RSS_TYPE_TCPIPV4 2 350#define VMXNET3_RCD_RSS_TYPE_IPV6 3 351#define VMXNET3_RCD_RSS_TYPE_TCPIPV6 4 352#define VMXNET3_RCD_RSS_TYPE_UDPIPV4 5 353#define VMXNET3_RCD_RSS_TYPE_UDPIPV6 6 354#define VMXNET3_RCD_RSS_TYPE_ESPIPV4 7 355#define VMXNET3_RCD_RSS_TYPE_ESPIPV6 8 356 357 358/* a union for accessing all cmd/completion descriptors */ 359union Vmxnet3_GenericDesc { 360 __le64 qword[2]; 361 __le32 dword[4]; 362 __le16 word[8]; 363 struct Vmxnet3_TxDesc txd; 364 struct Vmxnet3_RxDesc rxd; 365 struct Vmxnet3_TxCompDesc tcd; 366 struct Vmxnet3_RxCompDesc rcd; 367 struct Vmxnet3_RxCompDescExt rcdExt; 368}; 369 370#define VMXNET3_INIT_GEN 1 371 372/* Max size of a single tx buffer */ 373#define VMXNET3_MAX_TX_BUF_SIZE (1 << 14) 374 375/* # of tx desc needed for a tx buffer size */ 376#define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \ 377 VMXNET3_MAX_TX_BUF_SIZE) 378 379/* max # of tx descs for a non-tso pkt */ 380#define VMXNET3_MAX_TXD_PER_PKT 16 381 382/* Max size of a single rx buffer */ 383#define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1) 384/* Minimum size of a type 0 buffer */ 385#define VMXNET3_MIN_T0_BUF_SIZE 128 386#define VMXNET3_MAX_CSUM_OFFSET 1024 387 388/* Ring base address alignment */ 389#define VMXNET3_RING_BA_ALIGN 512 390#define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1) 391 392/* Ring size must be a multiple of 32 */ 393#define VMXNET3_RING_SIZE_ALIGN 32 394#define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1) 395 396/* Tx Data Ring buffer size must be a multiple of 64 */ 397#define VMXNET3_TXDATA_DESC_SIZE_ALIGN 64 398#define VMXNET3_TXDATA_DESC_SIZE_MASK (VMXNET3_TXDATA_DESC_SIZE_ALIGN - 1) 399 400/* Rx Data Ring buffer size must be a multiple of 64 */ 401#define VMXNET3_RXDATA_DESC_SIZE_ALIGN 64 402#define VMXNET3_RXDATA_DESC_SIZE_MASK (VMXNET3_RXDATA_DESC_SIZE_ALIGN - 1) 403 404/* Max ring size */ 405#define VMXNET3_TX_RING_MAX_SIZE 4096 406#define VMXNET3_TC_RING_MAX_SIZE 4096 407#define VMXNET3_RX_RING_MAX_SIZE 4096 408#define VMXNET3_RX_RING2_MAX_SIZE 4096 409#define VMXNET3_RC_RING_MAX_SIZE 8192 410 411#define VMXNET3_TXDATA_DESC_MIN_SIZE 128 412#define VMXNET3_TXDATA_DESC_MAX_SIZE 2048 413 414#define VMXNET3_RXDATA_DESC_MAX_SIZE 2048 415 416/* a list of reasons for queue stop */ 417 418enum { 419 VMXNET3_ERR_NOEOP = 0x80000000, /* cannot find the EOP desc of a pkt */ 420 VMXNET3_ERR_TXD_REUSE = 0x80000001, /* reuse TxDesc before tx completion */ 421 VMXNET3_ERR_BIG_PKT = 0x80000002, /* too many TxDesc for a pkt */ 422 VMXNET3_ERR_DESC_NOT_SPT = 0x80000003, /* descriptor type not supported */ 423 VMXNET3_ERR_SMALL_BUF = 0x80000004, /* type 0 buffer too small */ 424 VMXNET3_ERR_STRESS = 0x80000005, /* stress option firing in vmkernel */ 425 VMXNET3_ERR_SWITCH = 0x80000006, /* mode switch failure */ 426 VMXNET3_ERR_TXD_INVALID = 0x80000007, /* invalid TxDesc */ 427}; 428 429/* completion descriptor types */ 430#define VMXNET3_CDTYPE_TXCOMP 0 /* Tx Completion Descriptor */ 431#define VMXNET3_CDTYPE_RXCOMP 3 /* Rx Completion Descriptor */ 432#define VMXNET3_CDTYPE_RXCOMP_LRO 4 /* Rx Completion Descriptor for LRO */ 433 434enum { 435 VMXNET3_GOS_BITS_UNK = 0, /* unknown */ 436 VMXNET3_GOS_BITS_32 = 1, 437 VMXNET3_GOS_BITS_64 = 2, 438}; 439 440#define VMXNET3_GOS_TYPE_LINUX 1 441 442 443struct Vmxnet3_GOSInfo { 444#ifdef __BIG_ENDIAN_BITFIELD 445 u32 gosMisc:10; /* other info about gos */ 446 u32 gosVer:16; /* gos version */ 447 u32 gosType:4; /* which guest */ 448 u32 gosBits:2; /* 32-bit or 64-bit? */ 449#else 450 u32 gosBits:2; /* 32-bit or 64-bit? */ 451 u32 gosType:4; /* which guest */ 452 u32 gosVer:16; /* gos version */ 453 u32 gosMisc:10; /* other info about gos */ 454#endif /* __BIG_ENDIAN_BITFIELD */ 455}; 456 457struct Vmxnet3_DriverInfo { 458 __le32 version; 459 struct Vmxnet3_GOSInfo gos; 460 __le32 vmxnet3RevSpt; 461 __le32 uptVerSpt; 462}; 463 464 465#define VMXNET3_REV1_MAGIC 3133079265u 466 467/* 468 * QueueDescPA must be 128 bytes aligned. It points to an array of 469 * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc. 470 * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by 471 * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively. 472 */ 473#define VMXNET3_QUEUE_DESC_ALIGN 128 474 475 476struct Vmxnet3_MiscConf { 477 struct Vmxnet3_DriverInfo driverInfo; 478 __le64 uptFeatures; 479 __le64 ddPA; /* driver data PA */ 480 __le64 queueDescPA; /* queue descriptor table PA */ 481 __le32 ddLen; /* driver data len */ 482 __le32 queueDescLen; /* queue desc. table len in bytes */ 483 __le32 mtu; 484 __le16 maxNumRxSG; 485 u8 numTxQueues; 486 u8 numRxQueues; 487 __le32 reserved[4]; 488}; 489 490 491struct Vmxnet3_TxQueueConf { 492 __le64 txRingBasePA; 493 __le64 dataRingBasePA; 494 __le64 compRingBasePA; 495 __le64 ddPA; /* driver data */ 496 __le64 reserved; 497 __le32 txRingSize; /* # of tx desc */ 498 __le32 dataRingSize; /* # of data desc */ 499 __le32 compRingSize; /* # of comp desc */ 500 __le32 ddLen; /* size of driver data */ 501 u8 intrIdx; 502 u8 _pad1[1]; 503 __le16 txDataRingDescSize; 504 u8 _pad2[4]; 505}; 506 507 508struct Vmxnet3_RxQueueConf { 509 __le64 rxRingBasePA[2]; 510 __le64 compRingBasePA; 511 __le64 ddPA; /* driver data */ 512 __le64 rxDataRingBasePA; 513 __le32 rxRingSize[2]; /* # of rx desc */ 514 __le32 compRingSize; /* # of rx comp desc */ 515 __le32 ddLen; /* size of driver data */ 516 u8 intrIdx; 517 u8 _pad1[1]; 518 __le16 rxDataRingDescSize; /* size of rx data ring buffer */ 519 u8 _pad2[4]; 520}; 521 522 523enum vmxnet3_intr_mask_mode { 524 VMXNET3_IMM_AUTO = 0, 525 VMXNET3_IMM_ACTIVE = 1, 526 VMXNET3_IMM_LAZY = 2 527}; 528 529enum vmxnet3_intr_type { 530 VMXNET3_IT_AUTO = 0, 531 VMXNET3_IT_INTX = 1, 532 VMXNET3_IT_MSI = 2, 533 VMXNET3_IT_MSIX = 3 534}; 535 536#define VMXNET3_MAX_TX_QUEUES 8 537#define VMXNET3_MAX_RX_QUEUES 16 538/* addition 1 for events */ 539#define VMXNET3_MAX_INTRS 25 540 541/* Version 6 and later will use below macros */ 542#define VMXNET3_EXT_MAX_TX_QUEUES 32 543#define VMXNET3_EXT_MAX_RX_QUEUES 32 544/* addition 1 for events */ 545#define VMXNET3_EXT_MAX_INTRS 65 546#define VMXNET3_FIRST_SET_INTRS 64 547 548/* value of intrCtrl */ 549#define VMXNET3_IC_DISABLE_ALL 0x1 /* bit 0 */ 550 551 552struct Vmxnet3_IntrConf { 553 bool autoMask; 554 u8 numIntrs; /* # of interrupts */ 555 u8 eventIntrIdx; 556 u8 modLevels[VMXNET3_MAX_INTRS]; /* moderation level for 557 * each intr */ 558 __le32 intrCtrl; 559 __le32 reserved[2]; 560}; 561 562struct Vmxnet3_IntrConfExt { 563 u8 autoMask; 564 u8 numIntrs; /* # of interrupts */ 565 u8 eventIntrIdx; 566 u8 reserved; 567 __le32 intrCtrl; 568 __le32 reserved1; 569 u8 modLevels[VMXNET3_EXT_MAX_INTRS]; /* moderation level for 570 * each intr 571 */ 572 u8 reserved2[3]; 573}; 574 575/* one bit per VLAN ID, the size is in the units of u32 */ 576#define VMXNET3_VFT_SIZE (4096 / (sizeof(u32) * 8)) 577 578 579struct Vmxnet3_QueueStatus { 580 bool stopped; 581 u8 _pad[3]; 582 __le32 error; 583}; 584 585 586struct Vmxnet3_TxQueueCtrl { 587 __le32 txNumDeferred; 588 __le32 txThreshold; 589 __le64 reserved; 590}; 591 592 593struct Vmxnet3_RxQueueCtrl { 594 bool updateRxProd; 595 u8 _pad[7]; 596 __le64 reserved; 597}; 598 599enum { 600 VMXNET3_RXM_UCAST = 0x01, /* unicast only */ 601 VMXNET3_RXM_MCAST = 0x02, /* multicast passing the filters */ 602 VMXNET3_RXM_BCAST = 0x04, /* broadcast only */ 603 VMXNET3_RXM_ALL_MULTI = 0x08, /* all multicast */ 604 VMXNET3_RXM_PROMISC = 0x10 /* promiscuous */ 605}; 606 607struct Vmxnet3_RxFilterConf { 608 __le32 rxMode; /* VMXNET3_RXM_xxx */ 609 __le16 mfTableLen; /* size of the multicast filter table */ 610 __le16 _pad1; 611 __le64 mfTablePA; /* PA of the multicast filters table */ 612 __le32 vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */ 613}; 614 615 616#define VMXNET3_PM_MAX_FILTERS 6 617#define VMXNET3_PM_MAX_PATTERN_SIZE 128 618#define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8) 619 620#define VMXNET3_PM_WAKEUP_MAGIC cpu_to_le16(0x01) /* wake up on magic pkts */ 621#define VMXNET3_PM_WAKEUP_FILTER cpu_to_le16(0x02) /* wake up on pkts matching 622 * filters */ 623 624 625struct Vmxnet3_PM_PktFilter { 626 u8 maskSize; 627 u8 patternSize; 628 u8 mask[VMXNET3_PM_MAX_MASK_SIZE]; 629 u8 pattern[VMXNET3_PM_MAX_PATTERN_SIZE]; 630 u8 pad[6]; 631}; 632 633 634struct Vmxnet3_PMConf { 635 __le16 wakeUpEvents; /* VMXNET3_PM_WAKEUP_xxx */ 636 u8 numFilters; 637 u8 pad[5]; 638 struct Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS]; 639}; 640 641 642struct Vmxnet3_VariableLenConfDesc { 643 __le32 confVer; 644 __le32 confLen; 645 __le64 confPA; 646}; 647 648 649struct Vmxnet3_TxQueueDesc { 650 struct Vmxnet3_TxQueueCtrl ctrl; 651 struct Vmxnet3_TxQueueConf conf; 652 653 /* Driver read after a GET command */ 654 struct Vmxnet3_QueueStatus status; 655 struct UPT1_TxStats stats; 656 u8 _pad[88]; /* 128 aligned */ 657}; 658 659 660struct Vmxnet3_RxQueueDesc { 661 struct Vmxnet3_RxQueueCtrl ctrl; 662 struct Vmxnet3_RxQueueConf conf; 663 /* Driver read after a GET commad */ 664 struct Vmxnet3_QueueStatus status; 665 struct UPT1_RxStats stats; 666 u8 __pad[88]; /* 128 aligned */ 667}; 668 669struct Vmxnet3_SetPolling { 670 u8 enablePolling; 671}; 672 673#define VMXNET3_COAL_STATIC_MAX_DEPTH 128 674#define VMXNET3_COAL_RBC_MIN_RATE 100 675#define VMXNET3_COAL_RBC_MAX_RATE 100000 676 677enum Vmxnet3_CoalesceMode { 678 VMXNET3_COALESCE_DISABLED = 0, 679 VMXNET3_COALESCE_ADAPT = 1, 680 VMXNET3_COALESCE_STATIC = 2, 681 VMXNET3_COALESCE_RBC = 3 682}; 683 684struct Vmxnet3_CoalesceRbc { 685 u32 rbc_rate; 686}; 687 688struct Vmxnet3_CoalesceStatic { 689 u32 tx_depth; 690 u32 tx_comp_depth; 691 u32 rx_depth; 692}; 693 694struct Vmxnet3_CoalesceScheme { 695 enum Vmxnet3_CoalesceMode coalMode; 696 union { 697 struct Vmxnet3_CoalesceRbc coalRbc; 698 struct Vmxnet3_CoalesceStatic coalStatic; 699 } coalPara; 700}; 701 702struct Vmxnet3_MemoryRegion { 703 __le64 startPA; 704 __le32 length; 705 __le16 txQueueBits; 706 __le16 rxQueueBits; 707}; 708 709#define MAX_MEMORY_REGION_PER_QUEUE 16 710#define MAX_MEMORY_REGION_PER_DEVICE 256 711 712struct Vmxnet3_MemRegs { 713 __le16 numRegs; 714 __le16 pad[3]; 715 struct Vmxnet3_MemoryRegion memRegs[1]; 716}; 717 718enum Vmxnet3_RSSField { 719 VMXNET3_RSS_FIELDS_TCPIP4 = 0x0001, 720 VMXNET3_RSS_FIELDS_TCPIP6 = 0x0002, 721 VMXNET3_RSS_FIELDS_UDPIP4 = 0x0004, 722 VMXNET3_RSS_FIELDS_UDPIP6 = 0x0008, 723 VMXNET3_RSS_FIELDS_ESPIP4 = 0x0010, 724 VMXNET3_RSS_FIELDS_ESPIP6 = 0x0020, 725}; 726 727/* If the command data <= 16 bytes, use the shared memory directly. 728 * otherwise, use variable length configuration descriptor. 729 */ 730union Vmxnet3_CmdInfo { 731 struct Vmxnet3_VariableLenConfDesc varConf; 732 struct Vmxnet3_SetPolling setPolling; 733 enum Vmxnet3_RSSField setRssFields; 734 __le64 data[2]; 735}; 736 737struct Vmxnet3_DSDevRead { 738 /* read-only region for device, read by dev in response to a SET cmd */ 739 struct Vmxnet3_MiscConf misc; 740 struct Vmxnet3_IntrConf intrConf; 741 struct Vmxnet3_RxFilterConf rxFilterConf; 742 struct Vmxnet3_VariableLenConfDesc rssConfDesc; 743 struct Vmxnet3_VariableLenConfDesc pmConfDesc; 744 struct Vmxnet3_VariableLenConfDesc pluginConfDesc; 745}; 746 747struct Vmxnet3_DSDevReadExt { 748 /* read-only region for device, read by dev in response to a SET cmd */ 749 struct Vmxnet3_IntrConfExt intrConfExt; 750}; 751 752/* All structures in DriverShared are padded to multiples of 8 bytes */ 753struct Vmxnet3_DriverShared { 754 __le32 magic; 755 /* make devRead start at 64bit boundaries */ 756 __le32 size; /* size of DriverShared */ 757 struct Vmxnet3_DSDevRead devRead; 758 __le32 ecr; 759 __le32 reserved; 760 union { 761 __le32 reserved1[4]; 762 union Vmxnet3_CmdInfo cmdInfo; /* only valid in the context of 763 * executing the relevant 764 * command 765 */ 766 } cu; 767 struct Vmxnet3_DSDevReadExt devReadExt; 768}; 769 770 771#define VMXNET3_ECR_RQERR (1 << 0) 772#define VMXNET3_ECR_TQERR (1 << 1) 773#define VMXNET3_ECR_LINK (1 << 2) 774#define VMXNET3_ECR_DIC (1 << 3) 775#define VMXNET3_ECR_DEBUG (1 << 4) 776 777/* flip the gen bit of a ring */ 778#define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1) 779 780/* only use this if moving the idx won't affect the gen bit */ 781#define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \ 782 do {\ 783 (idx)++;\ 784 if (unlikely((idx) == (ring_size))) {\ 785 (idx) = 0;\ 786 } \ 787 } while (0) 788 789#define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \ 790 (vfTable[vid >> 5] |= (1 << (vid & 31))) 791#define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \ 792 (vfTable[vid >> 5] &= ~(1 << (vid & 31))) 793 794#define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \ 795 ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0) 796 797#define VMXNET3_MAX_MTU 9000 798#define VMXNET3_V6_MAX_MTU 9190 799#define VMXNET3_MIN_MTU 60 800 801#define VMXNET3_LINK_UP (10000 << 16 | 1) /* 10 Gbps, up */ 802#define VMXNET3_LINK_DOWN 0 803 804#endif /* _VMXNET3_DEFS_H_ */