cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ce.h (13067B)


      1/* SPDX-License-Identifier: ISC */
      2/*
      3 * Copyright (c) 2005-2011 Atheros Communications Inc.
      4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
      5 * Copyright (c) 2018 The Linux Foundation. All rights reserved.
      6 */
      7
      8#ifndef _CE_H_
      9#define _CE_H_
     10
     11#include "hif.h"
     12
     13#define CE_HTT_H2T_MSG_SRC_NENTRIES 8192
     14
     15/* Descriptor rings must be aligned to this boundary */
     16#define CE_DESC_RING_ALIGN	8
     17#define CE_SEND_FLAG_GATHER	0x00010000
     18
     19/*
     20 * Copy Engine support: low-level Target-side Copy Engine API.
     21 * This is a hardware access layer used by code that understands
     22 * how to use copy engines.
     23 */
     24
     25struct ath10k_ce_pipe;
     26
     27#define CE_DESC_FLAGS_GATHER         (1 << 0)
     28#define CE_DESC_FLAGS_BYTE_SWAP      (1 << 1)
     29#define CE_WCN3990_DESC_FLAGS_GATHER BIT(31)
     30
     31#define CE_DESC_ADDR_MASK		GENMASK_ULL(34, 0)
     32#define CE_DESC_ADDR_HI_MASK		GENMASK(4, 0)
     33
     34/* Following desc flags are used in QCA99X0 */
     35#define CE_DESC_FLAGS_HOST_INT_DIS	(1 << 2)
     36#define CE_DESC_FLAGS_TGT_INT_DIS	(1 << 3)
     37
     38#define CE_DESC_FLAGS_META_DATA_MASK ar->hw_values->ce_desc_meta_data_mask
     39#define CE_DESC_FLAGS_META_DATA_LSB  ar->hw_values->ce_desc_meta_data_lsb
     40
     41#define CE_DDR_RRI_MASK			GENMASK(15, 0)
     42#define CE_DDR_DRRI_SHIFT		16
     43
     44struct ce_desc {
     45	__le32 addr;
     46	__le16 nbytes;
     47	__le16 flags; /* %CE_DESC_FLAGS_ */
     48};
     49
     50struct ce_desc_64 {
     51	__le64 addr;
     52	__le16 nbytes; /* length in register map */
     53	__le16 flags; /* fw_metadata_high */
     54	__le32 toeplitz_hash_result;
     55};
     56
     57#define CE_DESC_SIZE sizeof(struct ce_desc)
     58#define CE_DESC_SIZE_64 sizeof(struct ce_desc_64)
     59
     60struct ath10k_ce_ring {
     61	/* Number of entries in this ring; must be power of 2 */
     62	unsigned int nentries;
     63	unsigned int nentries_mask;
     64
     65	/*
     66	 * For dest ring, this is the next index to be processed
     67	 * by software after it was/is received into.
     68	 *
     69	 * For src ring, this is the last descriptor that was sent
     70	 * and completion processed by software.
     71	 *
     72	 * Regardless of src or dest ring, this is an invariant
     73	 * (modulo ring size):
     74	 *     write index >= read index >= sw_index
     75	 */
     76	unsigned int sw_index;
     77	/* cached copy */
     78	unsigned int write_index;
     79	/*
     80	 * For src ring, this is the next index not yet processed by HW.
     81	 * This is a cached copy of the real HW index (read index), used
     82	 * for avoiding reading the HW index register more often than
     83	 * necessary.
     84	 * This extends the invariant:
     85	 *     write index >= read index >= hw_index >= sw_index
     86	 *
     87	 * For dest ring, this is currently unused.
     88	 */
     89	/* cached copy */
     90	unsigned int hw_index;
     91
     92	/* Start of DMA-coherent area reserved for descriptors */
     93	/* Host address space */
     94	void *base_addr_owner_space_unaligned;
     95	/* CE address space */
     96	dma_addr_t base_addr_ce_space_unaligned;
     97
     98	/*
     99	 * Actual start of descriptors.
    100	 * Aligned to descriptor-size boundary.
    101	 * Points into reserved DMA-coherent area, above.
    102	 */
    103	/* Host address space */
    104	void *base_addr_owner_space;
    105
    106	/* CE address space */
    107	dma_addr_t base_addr_ce_space;
    108
    109	char *shadow_base_unaligned;
    110	struct ce_desc_64 *shadow_base;
    111
    112	/* keep last */
    113	void *per_transfer_context[];
    114};
    115
    116struct ath10k_ce_pipe {
    117	struct ath10k *ar;
    118	unsigned int id;
    119
    120	unsigned int attr_flags;
    121
    122	u32 ctrl_addr;
    123
    124	void (*send_cb)(struct ath10k_ce_pipe *);
    125	void (*recv_cb)(struct ath10k_ce_pipe *);
    126
    127	unsigned int src_sz_max;
    128	struct ath10k_ce_ring *src_ring;
    129	struct ath10k_ce_ring *dest_ring;
    130	const struct ath10k_ce_ops *ops;
    131};
    132
    133/* Copy Engine settable attributes */
    134struct ce_attr;
    135
    136struct ath10k_bus_ops {
    137	u32 (*read32)(struct ath10k *ar, u32 offset);
    138	void (*write32)(struct ath10k *ar, u32 offset, u32 value);
    139	int (*get_num_banks)(struct ath10k *ar);
    140};
    141
    142static inline struct ath10k_ce *ath10k_ce_priv(struct ath10k *ar)
    143{
    144	return (struct ath10k_ce *)ar->ce_priv;
    145}
    146
    147struct ath10k_ce {
    148	/* protects CE info */
    149	spinlock_t ce_lock;
    150	const struct ath10k_bus_ops *bus_ops;
    151	struct ath10k_ce_pipe ce_states[CE_COUNT_MAX];
    152	u32 *vaddr_rri;
    153	dma_addr_t paddr_rri;
    154};
    155
    156/*==================Send====================*/
    157
    158/* ath10k_ce_send flags */
    159#define CE_SEND_FLAG_BYTE_SWAP 1
    160
    161/*
    162 * Queue a source buffer to be sent to an anonymous destination buffer.
    163 *   ce         - which copy engine to use
    164 *   buffer          - address of buffer
    165 *   nbytes          - number of bytes to send
    166 *   transfer_id     - arbitrary ID; reflected to destination
    167 *   flags           - CE_SEND_FLAG_* values
    168 * Returns 0 on success; otherwise an error status.
    169 *
    170 * Note: If no flags are specified, use CE's default data swap mode.
    171 *
    172 * Implementation note: pushes 1 buffer to Source ring
    173 */
    174int ath10k_ce_send(struct ath10k_ce_pipe *ce_state,
    175		   void *per_transfer_send_context,
    176		   dma_addr_t buffer,
    177		   unsigned int nbytes,
    178		   /* 14 bits */
    179		   unsigned int transfer_id,
    180		   unsigned int flags);
    181
    182int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state,
    183			  void *per_transfer_context,
    184			  dma_addr_t buffer,
    185			  unsigned int nbytes,
    186			  unsigned int transfer_id,
    187			  unsigned int flags);
    188
    189void __ath10k_ce_send_revert(struct ath10k_ce_pipe *pipe);
    190
    191int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe);
    192
    193/*==================Recv=======================*/
    194
    195int __ath10k_ce_rx_num_free_bufs(struct ath10k_ce_pipe *pipe);
    196int ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx,
    197			  dma_addr_t paddr);
    198void ath10k_ce_rx_update_write_idx(struct ath10k_ce_pipe *pipe, u32 nentries);
    199
    200/* recv flags */
    201/* Data is byte-swapped */
    202#define CE_RECV_FLAG_SWAPPED	1
    203
    204/*
    205 * Supply data for the next completed unprocessed receive descriptor.
    206 * Pops buffer from Dest ring.
    207 */
    208int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state,
    209				  void **per_transfer_contextp,
    210				  unsigned int *nbytesp);
    211/*
    212 * Supply data for the next completed unprocessed send descriptor.
    213 * Pops 1 completed send buffer from Source ring.
    214 */
    215int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state,
    216				  void **per_transfer_contextp);
    217
    218int ath10k_ce_completed_send_next_nolock(struct ath10k_ce_pipe *ce_state,
    219					 void **per_transfer_contextp);
    220
    221/*==================CE Engine Initialization=======================*/
    222
    223int ath10k_ce_init_pipe(struct ath10k *ar, unsigned int ce_id,
    224			const struct ce_attr *attr);
    225void ath10k_ce_deinit_pipe(struct ath10k *ar, unsigned int ce_id);
    226int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id,
    227			 const struct ce_attr *attr);
    228void ath10k_ce_free_pipe(struct ath10k *ar, int ce_id);
    229
    230/*==================CE Engine Shutdown=======================*/
    231/*
    232 * Support clean shutdown by allowing the caller to revoke
    233 * receive buffers.  Target DMA must be stopped before using
    234 * this API.
    235 */
    236int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state,
    237			       void **per_transfer_contextp,
    238			       dma_addr_t *bufferp);
    239
    240int ath10k_ce_completed_recv_next_nolock(struct ath10k_ce_pipe *ce_state,
    241					 void **per_transfer_contextp,
    242					 unsigned int *nbytesp);
    243
    244/*
    245 * Support clean shutdown by allowing the caller to cancel
    246 * pending sends.  Target DMA must be stopped before using
    247 * this API.
    248 */
    249int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state,
    250			       void **per_transfer_contextp,
    251			       dma_addr_t *bufferp,
    252			       unsigned int *nbytesp,
    253			       unsigned int *transfer_idp);
    254
    255/*==================CE Interrupt Handlers====================*/
    256void ath10k_ce_per_engine_service_any(struct ath10k *ar);
    257void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id);
    258void ath10k_ce_disable_interrupt(struct ath10k *ar, int ce_id);
    259void ath10k_ce_disable_interrupts(struct ath10k *ar);
    260void ath10k_ce_enable_interrupt(struct ath10k *ar, int ce_id);
    261void ath10k_ce_enable_interrupts(struct ath10k *ar);
    262void ath10k_ce_dump_registers(struct ath10k *ar,
    263			      struct ath10k_fw_crash_data *crash_data);
    264
    265void ath10k_ce_alloc_rri(struct ath10k *ar);
    266void ath10k_ce_free_rri(struct ath10k *ar);
    267
    268/* ce_attr.flags values */
    269/* Use NonSnooping PCIe accesses? */
    270#define CE_ATTR_NO_SNOOP		BIT(0)
    271
    272/* Byte swap data words */
    273#define CE_ATTR_BYTE_SWAP_DATA		BIT(1)
    274
    275/* Swizzle descriptors? */
    276#define CE_ATTR_SWIZZLE_DESCRIPTORS	BIT(2)
    277
    278/* no interrupt on copy completion */
    279#define CE_ATTR_DIS_INTR		BIT(3)
    280
    281/* no interrupt, only polling */
    282#define CE_ATTR_POLL			BIT(4)
    283
    284/* Attributes of an instance of a Copy Engine */
    285struct ce_attr {
    286	/* CE_ATTR_* values */
    287	unsigned int flags;
    288
    289	/* #entries in source ring - Must be a power of 2 */
    290	unsigned int src_nentries;
    291
    292	/*
    293	 * Max source send size for this CE.
    294	 * This is also the minimum size of a destination buffer.
    295	 */
    296	unsigned int src_sz_max;
    297
    298	/* #entries in destination ring - Must be a power of 2 */
    299	unsigned int dest_nentries;
    300
    301	void (*send_cb)(struct ath10k_ce_pipe *);
    302	void (*recv_cb)(struct ath10k_ce_pipe *);
    303};
    304
    305struct ath10k_ce_ops {
    306	struct ath10k_ce_ring *(*ce_alloc_src_ring)(struct ath10k *ar,
    307						    u32 ce_id,
    308						    const struct ce_attr *attr);
    309	struct ath10k_ce_ring *(*ce_alloc_dst_ring)(struct ath10k *ar,
    310						    u32 ce_id,
    311						    const struct ce_attr *attr);
    312	int (*ce_rx_post_buf)(struct ath10k_ce_pipe *pipe, void *ctx,
    313			      dma_addr_t paddr);
    314	int (*ce_completed_recv_next_nolock)(struct ath10k_ce_pipe *ce_state,
    315					     void **per_transfer_contextp,
    316					     u32 *nbytesp);
    317	int (*ce_revoke_recv_next)(struct ath10k_ce_pipe *ce_state,
    318				   void **per_transfer_contextp,
    319				   dma_addr_t *nbytesp);
    320	void (*ce_extract_desc_data)(struct ath10k *ar,
    321				     struct ath10k_ce_ring *src_ring,
    322				     u32 sw_index, dma_addr_t *bufferp,
    323				     u32 *nbytesp, u32 *transfer_idp);
    324	void (*ce_free_pipe)(struct ath10k *ar, int ce_id);
    325	int (*ce_send_nolock)(struct ath10k_ce_pipe *pipe,
    326			      void *per_transfer_context,
    327			      dma_addr_t buffer, u32 nbytes,
    328			      u32 transfer_id, u32 flags);
    329	void (*ce_set_src_ring_base_addr_hi)(struct ath10k *ar,
    330					     u32 ce_ctrl_addr,
    331					     u64 addr);
    332	void (*ce_set_dest_ring_base_addr_hi)(struct ath10k *ar,
    333					      u32 ce_ctrl_addr,
    334					      u64 addr);
    335	int (*ce_completed_send_next_nolock)(struct ath10k_ce_pipe *ce_state,
    336					     void **per_transfer_contextp);
    337};
    338
    339static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id)
    340{
    341	return CE0_BASE_ADDRESS + (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS) * ce_id;
    342}
    343
    344#define COPY_ENGINE_ID(COPY_ENGINE_BASE_ADDRESS) (((COPY_ENGINE_BASE_ADDRESS) \
    345		- CE0_BASE_ADDRESS) / (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS))
    346
    347#define CE_SRC_RING_TO_DESC(baddr, idx) \
    348	(&(((struct ce_desc *)baddr)[idx]))
    349
    350#define CE_DEST_RING_TO_DESC(baddr, idx) \
    351	(&(((struct ce_desc *)baddr)[idx]))
    352
    353#define CE_SRC_RING_TO_DESC_64(baddr, idx) \
    354	(&(((struct ce_desc_64 *)baddr)[idx]))
    355
    356#define CE_DEST_RING_TO_DESC_64(baddr, idx) \
    357	(&(((struct ce_desc_64 *)baddr)[idx]))
    358
    359/* Ring arithmetic (modulus number of entries in ring, which is a pwr of 2). */
    360#define CE_RING_DELTA(nentries_mask, fromidx, toidx) \
    361	(((int)(toidx) - (int)(fromidx)) & (nentries_mask))
    362
    363#define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask))
    364#define CE_RING_IDX_ADD(nentries_mask, idx, num) \
    365		(((idx) + (num)) & (nentries_mask))
    366
    367#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \
    368				ar->regs->ce_wrap_intr_sum_host_msi_lsb
    369#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \
    370				ar->regs->ce_wrap_intr_sum_host_msi_mask
    371#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) \
    372	(((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \
    373		CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
    374#define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS			0x0000
    375
    376static inline u32 ath10k_ce_interrupt_summary(struct ath10k *ar)
    377{
    378	struct ath10k_ce *ce = ath10k_ce_priv(ar);
    379
    380	return CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(
    381		ce->bus_ops->read32((ar), CE_WRAPPER_BASE_ADDRESS +
    382		CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS));
    383}
    384
    385/* Host software's Copy Engine configuration. */
    386#define CE_ATTR_FLAGS 0
    387
    388/*
    389 * Configuration information for a Copy Engine pipe.
    390 * Passed from Host to Target during startup (one per CE).
    391 *
    392 * NOTE: Structure is shared between Host software and Target firmware!
    393 */
    394struct ce_pipe_config {
    395	__le32 pipenum;
    396	__le32 pipedir;
    397	__le32 nentries;
    398	__le32 nbytes_max;
    399	__le32 flags;
    400	__le32 reserved;
    401};
    402
    403/*
    404 * Directions for interconnect pipe configuration.
    405 * These definitions may be used during configuration and are shared
    406 * between Host and Target.
    407 *
    408 * Pipe Directions are relative to the Host, so PIPEDIR_IN means
    409 * "coming IN over air through Target to Host" as with a WiFi Rx operation.
    410 * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
    411 * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
    412 * Target since things that are "PIPEDIR_OUT" are coming IN to the Target
    413 * over the interconnect.
    414 */
    415#define PIPEDIR_NONE    0
    416#define PIPEDIR_IN      1  /* Target-->Host, WiFi Rx direction */
    417#define PIPEDIR_OUT     2  /* Host->Target, WiFi Tx direction */
    418#define PIPEDIR_INOUT   3  /* bidirectional */
    419
    420/* Establish a mapping between a service/direction and a pipe. */
    421struct ce_service_to_pipe {
    422	__le32 service_id;
    423	__le32 pipedir;
    424	__le32 pipenum;
    425};
    426
    427#endif /* _CE_H_ */