cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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hw.c (80338B)


      1// SPDX-License-Identifier: BSD-3-Clause-Clear
      2/*
      3 * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved.
      4 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
      5 */
      6
      7#include <linux/types.h>
      8#include <linux/bitops.h>
      9#include <linux/bitfield.h>
     10
     11#include "core.h"
     12#include "ce.h"
     13#include "hif.h"
     14#include "hal.h"
     15#include "hw.h"
     16
     17/* Map from pdev index to hw mac index */
     18static u8 ath11k_hw_ipq8074_mac_from_pdev_id(int pdev_idx)
     19{
     20	switch (pdev_idx) {
     21	case 0:
     22		return 0;
     23	case 1:
     24		return 2;
     25	case 2:
     26		return 1;
     27	default:
     28		return ATH11K_INVALID_HW_MAC_ID;
     29	}
     30}
     31
     32static u8 ath11k_hw_ipq6018_mac_from_pdev_id(int pdev_idx)
     33{
     34	return pdev_idx;
     35}
     36
     37static void ath11k_hw_ipq8074_tx_mesh_enable(struct ath11k_base *ab,
     38					     struct hal_tcl_data_cmd *tcl_cmd)
     39{
     40	tcl_cmd->info2 |= FIELD_PREP(HAL_IPQ8074_TCL_DATA_CMD_INFO2_MESH_ENABLE,
     41				     true);
     42}
     43
     44static void ath11k_hw_qcn9074_tx_mesh_enable(struct ath11k_base *ab,
     45					     struct hal_tcl_data_cmd *tcl_cmd)
     46{
     47	tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE,
     48				     true);
     49}
     50
     51static void ath11k_hw_wcn6855_tx_mesh_enable(struct ath11k_base *ab,
     52					     struct hal_tcl_data_cmd *tcl_cmd)
     53{
     54	tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE,
     55				     true);
     56}
     57
     58static void ath11k_init_wmi_config_qca6390(struct ath11k_base *ab,
     59					   struct target_resource_config *config)
     60{
     61	config->num_vdevs = 4;
     62	config->num_peers = 16;
     63	config->num_tids = 32;
     64
     65	config->num_offload_peers = 3;
     66	config->num_offload_reorder_buffs = 3;
     67	config->num_peer_keys = TARGET_NUM_PEER_KEYS;
     68	config->ast_skid_limit = TARGET_AST_SKID_LIMIT;
     69	config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
     70	config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
     71	config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI;
     72	config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI;
     73	config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI;
     74	config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI;
     75	config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI;
     76	config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS;
     77	config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV;
     78	config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV;
     79	config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES;
     80	config->num_mcast_groups = 0;
     81	config->num_mcast_table_elems = 0;
     82	config->mcast2ucast_mode = 0;
     83	config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE;
     84	config->num_wds_entries = 0;
     85	config->dma_burst_size = 0;
     86	config->rx_skip_defrag_timeout_dup_detection_check = 0;
     87	config->vow_config = TARGET_VOW_CONFIG;
     88	config->gtk_offload_max_vdev = 2;
     89	config->num_msdu_desc = 0x400;
     90	config->beacon_tx_offload_max_vdev = 2;
     91	config->rx_batchmode = TARGET_RX_BATCHMODE;
     92
     93	config->peer_map_unmap_v2_support = 0;
     94	config->use_pdev_id = 1;
     95	config->max_frag_entries = 0xa;
     96	config->num_tdls_vdevs = 0x1;
     97	config->num_tdls_conn_table_entries = 8;
     98	config->beacon_tx_offload_max_vdev = 0x2;
     99	config->num_multicast_filter_entries = 0x20;
    100	config->num_wow_filters = 0x16;
    101	config->num_keep_alive_pattern = 0;
    102	config->flag1 |= WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64;
    103}
    104
    105static void ath11k_hw_ipq8074_reo_setup(struct ath11k_base *ab)
    106{
    107	u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;
    108	u32 val;
    109	/* Each hash entry uses three bits to map to a particular ring. */
    110	u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 |
    111		HAL_HASH_ROUTING_RING_SW2 << 3 |
    112		HAL_HASH_ROUTING_RING_SW3 << 6 |
    113		HAL_HASH_ROUTING_RING_SW4 << 9 |
    114		HAL_HASH_ROUTING_RING_SW1 << 12 |
    115		HAL_HASH_ROUTING_RING_SW2 << 15 |
    116		HAL_HASH_ROUTING_RING_SW3 << 18 |
    117		HAL_HASH_ROUTING_RING_SW4 << 21;
    118
    119	val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE);
    120
    121	val &= ~HAL_REO1_GEN_ENABLE_FRAG_DST_RING;
    122	val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_FRAG_DST_RING,
    123			HAL_SRNG_RING_ID_REO2SW1) |
    124		FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) |
    125		FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1);
    126	ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val);
    127
    128	ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab),
    129			   HAL_DEFAULT_REO_TIMEOUT_USEC);
    130	ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab),
    131			   HAL_DEFAULT_REO_TIMEOUT_USEC);
    132	ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab),
    133			   HAL_DEFAULT_REO_TIMEOUT_USEC);
    134	ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab),
    135			   HAL_DEFAULT_REO_TIMEOUT_USEC);
    136
    137	ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0,
    138			   FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
    139				      ring_hash_map));
    140	ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1,
    141			   FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
    142				      ring_hash_map));
    143	ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2,
    144			   FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
    145				      ring_hash_map));
    146	ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3,
    147			   FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
    148				      ring_hash_map));
    149}
    150
    151static void ath11k_init_wmi_config_ipq8074(struct ath11k_base *ab,
    152					   struct target_resource_config *config)
    153{
    154	config->num_vdevs = ab->num_radios * TARGET_NUM_VDEVS(ab);
    155
    156	if (ab->num_radios == 2) {
    157		config->num_peers = TARGET_NUM_PEERS(ab, DBS);
    158		config->num_tids = TARGET_NUM_TIDS(ab, DBS);
    159	} else if (ab->num_radios == 3) {
    160		config->num_peers = TARGET_NUM_PEERS(ab, DBS_SBS);
    161		config->num_tids = TARGET_NUM_TIDS(ab, DBS_SBS);
    162	} else {
    163		/* Control should not reach here */
    164		config->num_peers = TARGET_NUM_PEERS(ab, SINGLE);
    165		config->num_tids = TARGET_NUM_TIDS(ab, SINGLE);
    166	}
    167	config->num_offload_peers = TARGET_NUM_OFFLD_PEERS;
    168	config->num_offload_reorder_buffs = TARGET_NUM_OFFLD_REORDER_BUFFS;
    169	config->num_peer_keys = TARGET_NUM_PEER_KEYS;
    170	config->ast_skid_limit = TARGET_AST_SKID_LIMIT;
    171	config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
    172	config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
    173	config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI;
    174	config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI;
    175	config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI;
    176	config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI;
    177
    178	if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags))
    179		config->rx_decap_mode = TARGET_DECAP_MODE_RAW;
    180	else
    181		config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI;
    182
    183	config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS;
    184	config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV;
    185	config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV;
    186	config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES;
    187	config->num_mcast_groups = TARGET_NUM_MCAST_GROUPS;
    188	config->num_mcast_table_elems = TARGET_NUM_MCAST_TABLE_ELEMS;
    189	config->mcast2ucast_mode = TARGET_MCAST2UCAST_MODE;
    190	config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE;
    191	config->num_wds_entries = TARGET_NUM_WDS_ENTRIES;
    192	config->dma_burst_size = TARGET_DMA_BURST_SIZE;
    193	config->rx_skip_defrag_timeout_dup_detection_check =
    194		TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK;
    195	config->vow_config = TARGET_VOW_CONFIG;
    196	config->gtk_offload_max_vdev = TARGET_GTK_OFFLOAD_MAX_VDEV;
    197	config->num_msdu_desc = TARGET_NUM_MSDU_DESC;
    198	config->beacon_tx_offload_max_vdev = ab->num_radios * TARGET_MAX_BCN_OFFLD;
    199	config->rx_batchmode = TARGET_RX_BATCHMODE;
    200	config->peer_map_unmap_v2_support = 1;
    201	config->twt_ap_pdev_count = ab->num_radios;
    202	config->twt_ap_sta_count = 1000;
    203	config->flag1 |= WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64;
    204}
    205
    206static int ath11k_hw_mac_id_to_pdev_id_ipq8074(struct ath11k_hw_params *hw,
    207					       int mac_id)
    208{
    209	return mac_id;
    210}
    211
    212static int ath11k_hw_mac_id_to_srng_id_ipq8074(struct ath11k_hw_params *hw,
    213					       int mac_id)
    214{
    215	return 0;
    216}
    217
    218static int ath11k_hw_mac_id_to_pdev_id_qca6390(struct ath11k_hw_params *hw,
    219					       int mac_id)
    220{
    221	return 0;
    222}
    223
    224static int ath11k_hw_mac_id_to_srng_id_qca6390(struct ath11k_hw_params *hw,
    225					       int mac_id)
    226{
    227	return mac_id;
    228}
    229
    230static bool ath11k_hw_ipq8074_rx_desc_get_first_msdu(struct hal_rx_desc *desc)
    231{
    232	return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU,
    233			   __le32_to_cpu(desc->u.ipq8074.msdu_end.info2));
    234}
    235
    236static bool ath11k_hw_ipq8074_rx_desc_get_last_msdu(struct hal_rx_desc *desc)
    237{
    238	return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU,
    239			   __le32_to_cpu(desc->u.ipq8074.msdu_end.info2));
    240}
    241
    242static u8 ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc)
    243{
    244	return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING,
    245			 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2));
    246}
    247
    248static u8 *ath11k_hw_ipq8074_rx_desc_get_hdr_status(struct hal_rx_desc *desc)
    249{
    250	return desc->u.ipq8074.hdr_status;
    251}
    252
    253static bool ath11k_hw_ipq8074_rx_desc_encrypt_valid(struct hal_rx_desc *desc)
    254{
    255	return __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1) &
    256	       RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID;
    257}
    258
    259static u32 ath11k_hw_ipq8074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc)
    260{
    261	return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE,
    262			 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2));
    263}
    264
    265static u8 ath11k_hw_ipq8074_rx_desc_get_decap_type(struct hal_rx_desc *desc)
    266{
    267	return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT,
    268			 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2));
    269}
    270
    271static u8 ath11k_hw_ipq8074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc)
    272{
    273	return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT,
    274			 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2));
    275}
    276
    277static bool ath11k_hw_ipq8074_rx_desc_get_ldpc_support(struct hal_rx_desc *desc)
    278{
    279	return FIELD_GET(RX_MSDU_START_INFO2_LDPC,
    280			 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2));
    281}
    282
    283static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc)
    284{
    285	return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID,
    286			   __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1));
    287}
    288
    289static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc)
    290{
    291	return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID,
    292			   __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1));
    293}
    294
    295static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc)
    296{
    297	return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM,
    298			 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1));
    299}
    300
    301static u16 ath11k_hw_ipq8074_rx_desc_get_msdu_len(struct hal_rx_desc *desc)
    302{
    303	return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH,
    304			 __le32_to_cpu(desc->u.ipq8074.msdu_start.info1));
    305}
    306
    307static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc)
    308{
    309	return FIELD_GET(RX_MSDU_START_INFO3_SGI,
    310			 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3));
    311}
    312
    313static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc)
    314{
    315	return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS,
    316			 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3));
    317}
    318
    319static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc)
    320{
    321	return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW,
    322			 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3));
    323}
    324
    325static u32 ath11k_hw_ipq8074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc)
    326{
    327	return __le32_to_cpu(desc->u.ipq8074.msdu_start.phy_meta_data);
    328}
    329
    330static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc)
    331{
    332	return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE,
    333			 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3));
    334}
    335
    336static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc)
    337{
    338	return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP,
    339			 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3));
    340}
    341
    342static u8 ath11k_hw_ipq8074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc)
    343{
    344	return FIELD_GET(RX_MPDU_START_INFO2_TID,
    345			 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2));
    346}
    347
    348static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc)
    349{
    350	return __le16_to_cpu(desc->u.ipq8074.mpdu_start.sw_peer_id);
    351}
    352
    353static void ath11k_hw_ipq8074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc,
    354						    struct hal_rx_desc *ldesc)
    355{
    356	memcpy((u8 *)&fdesc->u.ipq8074.msdu_end, (u8 *)&ldesc->u.ipq8074.msdu_end,
    357	       sizeof(struct rx_msdu_end_ipq8074));
    358	memcpy((u8 *)&fdesc->u.ipq8074.attention, (u8 *)&ldesc->u.ipq8074.attention,
    359	       sizeof(struct rx_attention));
    360	memcpy((u8 *)&fdesc->u.ipq8074.mpdu_end, (u8 *)&ldesc->u.ipq8074.mpdu_end,
    361	       sizeof(struct rx_mpdu_end));
    362}
    363
    364static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc)
    365{
    366	return FIELD_GET(HAL_TLV_HDR_TAG,
    367			 __le32_to_cpu(desc->u.ipq8074.mpdu_start_tag));
    368}
    369
    370static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc)
    371{
    372	return __le16_to_cpu(desc->u.ipq8074.mpdu_start.phy_ppdu_id);
    373}
    374
    375static void ath11k_hw_ipq8074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len)
    376{
    377	u32 info = __le32_to_cpu(desc->u.ipq8074.msdu_start.info1);
    378
    379	info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH;
    380	info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len);
    381
    382	desc->u.ipq8074.msdu_start.info1 = __cpu_to_le32(info);
    383}
    384
    385static bool ath11k_hw_ipq8074_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc)
    386{
    387	return __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1) &
    388	       RX_MPDU_START_INFO1_MAC_ADDR2_VALID;
    389}
    390
    391static u8 *ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc)
    392{
    393	return desc->u.ipq8074.mpdu_start.addr2;
    394}
    395
    396static
    397struct rx_attention *ath11k_hw_ipq8074_rx_desc_get_attention(struct hal_rx_desc *desc)
    398{
    399	return &desc->u.ipq8074.attention;
    400}
    401
    402static u8 *ath11k_hw_ipq8074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc)
    403{
    404	return &desc->u.ipq8074.msdu_payload[0];
    405}
    406
    407static bool ath11k_hw_qcn9074_rx_desc_get_first_msdu(struct hal_rx_desc *desc)
    408{
    409	return !!FIELD_GET(RX_MSDU_END_INFO4_FIRST_MSDU,
    410			   __le16_to_cpu(desc->u.qcn9074.msdu_end.info4));
    411}
    412
    413static bool ath11k_hw_qcn9074_rx_desc_get_last_msdu(struct hal_rx_desc *desc)
    414{
    415	return !!FIELD_GET(RX_MSDU_END_INFO4_LAST_MSDU,
    416			   __le16_to_cpu(desc->u.qcn9074.msdu_end.info4));
    417}
    418
    419static u8 ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc)
    420{
    421	return FIELD_GET(RX_MSDU_END_INFO4_L3_HDR_PADDING,
    422			 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4));
    423}
    424
    425static u8 *ath11k_hw_qcn9074_rx_desc_get_hdr_status(struct hal_rx_desc *desc)
    426{
    427	return desc->u.qcn9074.hdr_status;
    428}
    429
    430static bool ath11k_hw_qcn9074_rx_desc_encrypt_valid(struct hal_rx_desc *desc)
    431{
    432	return __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11) &
    433	       RX_MPDU_START_INFO11_ENCRYPT_INFO_VALID;
    434}
    435
    436static u32 ath11k_hw_qcn9074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc)
    437{
    438	return FIELD_GET(RX_MPDU_START_INFO9_ENC_TYPE,
    439			 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9));
    440}
    441
    442static u8 ath11k_hw_qcn9074_rx_desc_get_decap_type(struct hal_rx_desc *desc)
    443{
    444	return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT,
    445			 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2));
    446}
    447
    448static u8 ath11k_hw_qcn9074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc)
    449{
    450	return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT,
    451			 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2));
    452}
    453
    454static bool ath11k_hw_qcn9074_rx_desc_get_ldpc_support(struct hal_rx_desc *desc)
    455{
    456	return FIELD_GET(RX_MSDU_START_INFO2_LDPC,
    457			 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2));
    458}
    459
    460static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc)
    461{
    462	return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_CTRL_VALID,
    463			   __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11));
    464}
    465
    466static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc)
    467{
    468	return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_FCTRL_VALID,
    469			   __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11));
    470}
    471
    472static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc)
    473{
    474	return FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_NUM,
    475			 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11));
    476}
    477
    478static u16 ath11k_hw_qcn9074_rx_desc_get_msdu_len(struct hal_rx_desc *desc)
    479{
    480	return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH,
    481			 __le32_to_cpu(desc->u.qcn9074.msdu_start.info1));
    482}
    483
    484static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc)
    485{
    486	return FIELD_GET(RX_MSDU_START_INFO3_SGI,
    487			 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3));
    488}
    489
    490static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc)
    491{
    492	return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS,
    493			 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3));
    494}
    495
    496static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc)
    497{
    498	return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW,
    499			 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3));
    500}
    501
    502static u32 ath11k_hw_qcn9074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc)
    503{
    504	return __le32_to_cpu(desc->u.qcn9074.msdu_start.phy_meta_data);
    505}
    506
    507static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc)
    508{
    509	return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE,
    510			 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3));
    511}
    512
    513static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc)
    514{
    515	return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP,
    516			 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3));
    517}
    518
    519static u8 ath11k_hw_qcn9074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc)
    520{
    521	return FIELD_GET(RX_MPDU_START_INFO9_TID,
    522			 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9));
    523}
    524
    525static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc)
    526{
    527	return __le16_to_cpu(desc->u.qcn9074.mpdu_start.sw_peer_id);
    528}
    529
    530static void ath11k_hw_qcn9074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc,
    531						    struct hal_rx_desc *ldesc)
    532{
    533	memcpy((u8 *)&fdesc->u.qcn9074.msdu_end, (u8 *)&ldesc->u.qcn9074.msdu_end,
    534	       sizeof(struct rx_msdu_end_qcn9074));
    535	memcpy((u8 *)&fdesc->u.qcn9074.attention, (u8 *)&ldesc->u.qcn9074.attention,
    536	       sizeof(struct rx_attention));
    537	memcpy((u8 *)&fdesc->u.qcn9074.mpdu_end, (u8 *)&ldesc->u.qcn9074.mpdu_end,
    538	       sizeof(struct rx_mpdu_end));
    539}
    540
    541static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc)
    542{
    543	return FIELD_GET(HAL_TLV_HDR_TAG,
    544			 __le32_to_cpu(desc->u.qcn9074.mpdu_start_tag));
    545}
    546
    547static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc)
    548{
    549	return __le16_to_cpu(desc->u.qcn9074.mpdu_start.phy_ppdu_id);
    550}
    551
    552static void ath11k_hw_qcn9074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len)
    553{
    554	u32 info = __le32_to_cpu(desc->u.qcn9074.msdu_start.info1);
    555
    556	info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH;
    557	info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len);
    558
    559	desc->u.qcn9074.msdu_start.info1 = __cpu_to_le32(info);
    560}
    561
    562static
    563struct rx_attention *ath11k_hw_qcn9074_rx_desc_get_attention(struct hal_rx_desc *desc)
    564{
    565	return &desc->u.qcn9074.attention;
    566}
    567
    568static u8 *ath11k_hw_qcn9074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc)
    569{
    570	return &desc->u.qcn9074.msdu_payload[0];
    571}
    572
    573static bool ath11k_hw_ipq9074_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc)
    574{
    575	return __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11) &
    576	       RX_MPDU_START_INFO11_MAC_ADDR2_VALID;
    577}
    578
    579static u8 *ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc)
    580{
    581	return desc->u.qcn9074.mpdu_start.addr2;
    582}
    583
    584static bool ath11k_hw_wcn6855_rx_desc_get_first_msdu(struct hal_rx_desc *desc)
    585{
    586	return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU_WCN6855,
    587			   __le32_to_cpu(desc->u.wcn6855.msdu_end.info2));
    588}
    589
    590static bool ath11k_hw_wcn6855_rx_desc_get_last_msdu(struct hal_rx_desc *desc)
    591{
    592	return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU_WCN6855,
    593			   __le32_to_cpu(desc->u.wcn6855.msdu_end.info2));
    594}
    595
    596static u8 ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc)
    597{
    598	return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING,
    599			 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2));
    600}
    601
    602static u8 *ath11k_hw_wcn6855_rx_desc_get_hdr_status(struct hal_rx_desc *desc)
    603{
    604	return desc->u.wcn6855.hdr_status;
    605}
    606
    607static bool ath11k_hw_wcn6855_rx_desc_encrypt_valid(struct hal_rx_desc *desc)
    608{
    609	return __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1) &
    610	       RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID;
    611}
    612
    613static u32 ath11k_hw_wcn6855_rx_desc_get_encrypt_type(struct hal_rx_desc *desc)
    614{
    615	return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE,
    616			 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info2));
    617}
    618
    619static u8 ath11k_hw_wcn6855_rx_desc_get_decap_type(struct hal_rx_desc *desc)
    620{
    621	return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT,
    622			 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2));
    623}
    624
    625static u8 ath11k_hw_wcn6855_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc)
    626{
    627	return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT,
    628			 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2));
    629}
    630
    631static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc)
    632{
    633	return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID,
    634			   __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1));
    635}
    636
    637static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc)
    638{
    639	return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID,
    640			   __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1));
    641}
    642
    643static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc)
    644{
    645	return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM,
    646			 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1));
    647}
    648
    649static u16 ath11k_hw_wcn6855_rx_desc_get_msdu_len(struct hal_rx_desc *desc)
    650{
    651	return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH,
    652			 __le32_to_cpu(desc->u.wcn6855.msdu_start.info1));
    653}
    654
    655static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc)
    656{
    657	return FIELD_GET(RX_MSDU_START_INFO3_SGI,
    658			 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
    659}
    660
    661static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc)
    662{
    663	return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS,
    664			 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
    665}
    666
    667static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc)
    668{
    669	return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW,
    670			 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
    671}
    672
    673static u32 ath11k_hw_wcn6855_rx_desc_get_msdu_freq(struct hal_rx_desc *desc)
    674{
    675	return __le32_to_cpu(desc->u.wcn6855.msdu_start.phy_meta_data);
    676}
    677
    678static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc)
    679{
    680	return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE,
    681			 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
    682}
    683
    684static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_nss(struct hal_rx_desc *desc)
    685{
    686	return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP,
    687			 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
    688}
    689
    690static u8 ath11k_hw_wcn6855_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc)
    691{
    692	return FIELD_GET(RX_MPDU_START_INFO2_TID_WCN6855,
    693			 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info2));
    694}
    695
    696static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc)
    697{
    698	return __le16_to_cpu(desc->u.wcn6855.mpdu_start.sw_peer_id);
    699}
    700
    701static void ath11k_hw_wcn6855_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc,
    702						    struct hal_rx_desc *ldesc)
    703{
    704	memcpy((u8 *)&fdesc->u.wcn6855.msdu_end, (u8 *)&ldesc->u.wcn6855.msdu_end,
    705	       sizeof(struct rx_msdu_end_wcn6855));
    706	memcpy((u8 *)&fdesc->u.wcn6855.attention, (u8 *)&ldesc->u.wcn6855.attention,
    707	       sizeof(struct rx_attention));
    708	memcpy((u8 *)&fdesc->u.wcn6855.mpdu_end, (u8 *)&ldesc->u.wcn6855.mpdu_end,
    709	       sizeof(struct rx_mpdu_end));
    710}
    711
    712static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc)
    713{
    714	return FIELD_GET(HAL_TLV_HDR_TAG,
    715			 __le32_to_cpu(desc->u.wcn6855.mpdu_start_tag));
    716}
    717
    718static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc)
    719{
    720	return __le16_to_cpu(desc->u.wcn6855.mpdu_start.phy_ppdu_id);
    721}
    722
    723static void ath11k_hw_wcn6855_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len)
    724{
    725	u32 info = __le32_to_cpu(desc->u.wcn6855.msdu_start.info1);
    726
    727	info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH;
    728	info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len);
    729
    730	desc->u.wcn6855.msdu_start.info1 = __cpu_to_le32(info);
    731}
    732
    733static
    734struct rx_attention *ath11k_hw_wcn6855_rx_desc_get_attention(struct hal_rx_desc *desc)
    735{
    736	return &desc->u.wcn6855.attention;
    737}
    738
    739static u8 *ath11k_hw_wcn6855_rx_desc_get_msdu_payload(struct hal_rx_desc *desc)
    740{
    741	return &desc->u.wcn6855.msdu_payload[0];
    742}
    743
    744static bool ath11k_hw_wcn6855_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc)
    745{
    746	return __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1) &
    747	       RX_MPDU_START_INFO1_MAC_ADDR2_VALID;
    748}
    749
    750static u8 *ath11k_hw_wcn6855_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc)
    751{
    752	return desc->u.wcn6855.mpdu_start.addr2;
    753}
    754
    755static void ath11k_hw_wcn6855_reo_setup(struct ath11k_base *ab)
    756{
    757	u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;
    758	u32 val;
    759	/* Each hash entry uses four bits to map to a particular ring. */
    760	u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 |
    761		HAL_HASH_ROUTING_RING_SW2 << 4 |
    762		HAL_HASH_ROUTING_RING_SW3 << 8 |
    763		HAL_HASH_ROUTING_RING_SW4 << 12 |
    764		HAL_HASH_ROUTING_RING_SW1 << 16 |
    765		HAL_HASH_ROUTING_RING_SW2 << 20 |
    766		HAL_HASH_ROUTING_RING_SW3 << 24 |
    767		HAL_HASH_ROUTING_RING_SW4 << 28;
    768
    769	val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE);
    770	val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) |
    771		FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1);
    772	ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val);
    773
    774	val = ath11k_hif_read32(ab, reo_base + HAL_REO1_MISC_CTL(ab));
    775	val &= ~HAL_REO1_MISC_CTL_FRAGMENT_DST_RING;
    776	val |= FIELD_PREP(HAL_REO1_MISC_CTL_FRAGMENT_DST_RING, HAL_SRNG_RING_ID_REO2SW1);
    777	ath11k_hif_write32(ab, reo_base + HAL_REO1_MISC_CTL(ab), val);
    778
    779	ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab),
    780			   HAL_DEFAULT_REO_TIMEOUT_USEC);
    781	ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab),
    782			   HAL_DEFAULT_REO_TIMEOUT_USEC);
    783	ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab),
    784			   HAL_DEFAULT_REO_TIMEOUT_USEC);
    785	ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab),
    786			   HAL_DEFAULT_REO_TIMEOUT_USEC);
    787
    788	ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2,
    789			   ring_hash_map);
    790	ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3,
    791			   ring_hash_map);
    792}
    793
    794static u16 ath11k_hw_ipq8074_mpdu_info_get_peerid(u8 *tlv_data)
    795{
    796	u16 peer_id = 0;
    797	struct hal_rx_mpdu_info *mpdu_info =
    798		(struct hal_rx_mpdu_info *)tlv_data;
    799
    800	peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID,
    801			    __le32_to_cpu(mpdu_info->info0));
    802
    803	return peer_id;
    804}
    805
    806static u16 ath11k_hw_wcn6855_mpdu_info_get_peerid(u8 *tlv_data)
    807{
    808	u16 peer_id = 0;
    809	struct hal_rx_mpdu_info_wcn6855 *mpdu_info =
    810		(struct hal_rx_mpdu_info_wcn6855 *)tlv_data;
    811
    812	peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID_WCN6855,
    813			    __le32_to_cpu(mpdu_info->info0));
    814	return peer_id;
    815}
    816
    817static bool ath11k_hw_wcn6855_rx_desc_get_ldpc_support(struct hal_rx_desc *desc)
    818{
    819	return FIELD_GET(RX_MSDU_START_INFO2_LDPC,
    820			 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2));
    821}
    822
    823const struct ath11k_hw_ops ipq8074_ops = {
    824	.get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
    825	.wmi_init_config = ath11k_init_wmi_config_ipq8074,
    826	.mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074,
    827	.mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074,
    828	.tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable,
    829	.rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu,
    830	.rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu,
    831	.rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes,
    832	.rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status,
    833	.rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid,
    834	.rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type,
    835	.rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type,
    836	.rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl,
    837	.rx_desc_get_ldpc_support = ath11k_hw_ipq8074_rx_desc_get_ldpc_support,
    838	.rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld,
    839	.rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid,
    840	.rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no,
    841	.rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len,
    842	.rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi,
    843	.rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs,
    844	.rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw,
    845	.rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq,
    846	.rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type,
    847	.rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss,
    848	.rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid,
    849	.rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id,
    850	.rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end,
    851	.rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag,
    852	.rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id,
    853	.rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len,
    854	.rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention,
    855	.rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload,
    856	.reo_setup = ath11k_hw_ipq8074_reo_setup,
    857	.mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
    858	.rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid,
    859	.rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2,
    860};
    861
    862const struct ath11k_hw_ops ipq6018_ops = {
    863	.get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id,
    864	.wmi_init_config = ath11k_init_wmi_config_ipq8074,
    865	.mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074,
    866	.mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074,
    867	.tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable,
    868	.rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu,
    869	.rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu,
    870	.rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes,
    871	.rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status,
    872	.rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid,
    873	.rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type,
    874	.rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type,
    875	.rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl,
    876	.rx_desc_get_ldpc_support = ath11k_hw_ipq8074_rx_desc_get_ldpc_support,
    877	.rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld,
    878	.rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid,
    879	.rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no,
    880	.rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len,
    881	.rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi,
    882	.rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs,
    883	.rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw,
    884	.rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq,
    885	.rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type,
    886	.rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss,
    887	.rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid,
    888	.rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id,
    889	.rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end,
    890	.rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag,
    891	.rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id,
    892	.rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len,
    893	.rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention,
    894	.rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload,
    895	.reo_setup = ath11k_hw_ipq8074_reo_setup,
    896	.mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
    897	.rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid,
    898	.rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2,
    899};
    900
    901const struct ath11k_hw_ops qca6390_ops = {
    902	.get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
    903	.wmi_init_config = ath11k_init_wmi_config_qca6390,
    904	.mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390,
    905	.mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390,
    906	.tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable,
    907	.rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu,
    908	.rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu,
    909	.rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes,
    910	.rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status,
    911	.rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid,
    912	.rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type,
    913	.rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type,
    914	.rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl,
    915	.rx_desc_get_ldpc_support = ath11k_hw_ipq8074_rx_desc_get_ldpc_support,
    916	.rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld,
    917	.rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid,
    918	.rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no,
    919	.rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len,
    920	.rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi,
    921	.rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs,
    922	.rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw,
    923	.rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq,
    924	.rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type,
    925	.rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss,
    926	.rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid,
    927	.rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id,
    928	.rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end,
    929	.rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag,
    930	.rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id,
    931	.rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len,
    932	.rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention,
    933	.rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload,
    934	.reo_setup = ath11k_hw_ipq8074_reo_setup,
    935	.mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
    936	.rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid,
    937	.rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2,
    938};
    939
    940const struct ath11k_hw_ops qcn9074_ops = {
    941	.get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id,
    942	.wmi_init_config = ath11k_init_wmi_config_ipq8074,
    943	.mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074,
    944	.mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074,
    945	.tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable,
    946	.rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu,
    947	.rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu,
    948	.rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes,
    949	.rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status,
    950	.rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid,
    951	.rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type,
    952	.rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type,
    953	.rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl,
    954	.rx_desc_get_ldpc_support = ath11k_hw_qcn9074_rx_desc_get_ldpc_support,
    955	.rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld,
    956	.rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid,
    957	.rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no,
    958	.rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len,
    959	.rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi,
    960	.rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs,
    961	.rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw,
    962	.rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq,
    963	.rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type,
    964	.rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss,
    965	.rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid,
    966	.rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id,
    967	.rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end,
    968	.rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag,
    969	.rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id,
    970	.rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len,
    971	.rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention,
    972	.rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload,
    973	.reo_setup = ath11k_hw_ipq8074_reo_setup,
    974	.mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
    975	.rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid,
    976	.rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2,
    977};
    978
    979const struct ath11k_hw_ops wcn6855_ops = {
    980	.get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
    981	.wmi_init_config = ath11k_init_wmi_config_qca6390,
    982	.mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390,
    983	.mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390,
    984	.tx_mesh_enable = ath11k_hw_wcn6855_tx_mesh_enable,
    985	.rx_desc_get_first_msdu = ath11k_hw_wcn6855_rx_desc_get_first_msdu,
    986	.rx_desc_get_last_msdu = ath11k_hw_wcn6855_rx_desc_get_last_msdu,
    987	.rx_desc_get_l3_pad_bytes = ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes,
    988	.rx_desc_get_hdr_status = ath11k_hw_wcn6855_rx_desc_get_hdr_status,
    989	.rx_desc_encrypt_valid = ath11k_hw_wcn6855_rx_desc_encrypt_valid,
    990	.rx_desc_get_encrypt_type = ath11k_hw_wcn6855_rx_desc_get_encrypt_type,
    991	.rx_desc_get_decap_type = ath11k_hw_wcn6855_rx_desc_get_decap_type,
    992	.rx_desc_get_mesh_ctl = ath11k_hw_wcn6855_rx_desc_get_mesh_ctl,
    993	.rx_desc_get_ldpc_support = ath11k_hw_wcn6855_rx_desc_get_ldpc_support,
    994	.rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld,
    995	.rx_desc_get_mpdu_fc_valid = ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid,
    996	.rx_desc_get_mpdu_start_seq_no = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no,
    997	.rx_desc_get_msdu_len = ath11k_hw_wcn6855_rx_desc_get_msdu_len,
    998	.rx_desc_get_msdu_sgi = ath11k_hw_wcn6855_rx_desc_get_msdu_sgi,
    999	.rx_desc_get_msdu_rate_mcs = ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs,
   1000	.rx_desc_get_msdu_rx_bw = ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw,
   1001	.rx_desc_get_msdu_freq = ath11k_hw_wcn6855_rx_desc_get_msdu_freq,
   1002	.rx_desc_get_msdu_pkt_type = ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type,
   1003	.rx_desc_get_msdu_nss = ath11k_hw_wcn6855_rx_desc_get_msdu_nss,
   1004	.rx_desc_get_mpdu_tid = ath11k_hw_wcn6855_rx_desc_get_mpdu_tid,
   1005	.rx_desc_get_mpdu_peer_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id,
   1006	.rx_desc_copy_attn_end_tlv = ath11k_hw_wcn6855_rx_desc_copy_attn_end,
   1007	.rx_desc_get_mpdu_start_tag = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag,
   1008	.rx_desc_get_mpdu_ppdu_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id,
   1009	.rx_desc_set_msdu_len = ath11k_hw_wcn6855_rx_desc_set_msdu_len,
   1010	.rx_desc_get_attention = ath11k_hw_wcn6855_rx_desc_get_attention,
   1011	.rx_desc_get_msdu_payload = ath11k_hw_wcn6855_rx_desc_get_msdu_payload,
   1012	.reo_setup = ath11k_hw_wcn6855_reo_setup,
   1013	.mpdu_info_get_peerid = ath11k_hw_wcn6855_mpdu_info_get_peerid,
   1014	.rx_desc_mac_addr2_valid = ath11k_hw_wcn6855_rx_desc_mac_addr2_valid,
   1015	.rx_desc_mpdu_start_addr2 = ath11k_hw_wcn6855_rx_desc_mpdu_start_addr2,
   1016};
   1017
   1018const struct ath11k_hw_ops wcn6750_ops = {
   1019	.get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
   1020	.wmi_init_config = ath11k_init_wmi_config_qca6390,
   1021	.mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390,
   1022	.mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390,
   1023	.tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable,
   1024	.rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu,
   1025	.rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu,
   1026	.rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes,
   1027	.rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status,
   1028	.rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid,
   1029	.rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type,
   1030	.rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type,
   1031	.rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl,
   1032	.rx_desc_get_ldpc_support = ath11k_hw_qcn9074_rx_desc_get_ldpc_support,
   1033	.rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld,
   1034	.rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid,
   1035	.rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no,
   1036	.rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len,
   1037	.rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi,
   1038	.rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs,
   1039	.rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw,
   1040	.rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq,
   1041	.rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type,
   1042	.rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss,
   1043	.rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid,
   1044	.rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id,
   1045	.rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end,
   1046	.rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag,
   1047	.rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id,
   1048	.rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len,
   1049	.rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention,
   1050	.rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload,
   1051	.reo_setup = ath11k_hw_wcn6855_reo_setup,
   1052	.mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
   1053	.rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid,
   1054	.rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2,
   1055};
   1056
   1057#define ATH11K_TX_RING_MASK_0 0x1
   1058#define ATH11K_TX_RING_MASK_1 0x2
   1059#define ATH11K_TX_RING_MASK_2 0x4
   1060
   1061#define ATH11K_RX_RING_MASK_0 0x1
   1062#define ATH11K_RX_RING_MASK_1 0x2
   1063#define ATH11K_RX_RING_MASK_2 0x4
   1064#define ATH11K_RX_RING_MASK_3 0x8
   1065
   1066#define ATH11K_RX_ERR_RING_MASK_0 0x1
   1067
   1068#define ATH11K_RX_WBM_REL_RING_MASK_0 0x1
   1069
   1070#define ATH11K_REO_STATUS_RING_MASK_0 0x1
   1071
   1072#define ATH11K_RXDMA2HOST_RING_MASK_0 0x1
   1073#define ATH11K_RXDMA2HOST_RING_MASK_1 0x2
   1074#define ATH11K_RXDMA2HOST_RING_MASK_2 0x4
   1075
   1076#define ATH11K_HOST2RXDMA_RING_MASK_0 0x1
   1077#define ATH11K_HOST2RXDMA_RING_MASK_1 0x2
   1078#define ATH11K_HOST2RXDMA_RING_MASK_2 0x4
   1079
   1080#define ATH11K_RX_MON_STATUS_RING_MASK_0 0x1
   1081#define ATH11K_RX_MON_STATUS_RING_MASK_1 0x2
   1082#define ATH11K_RX_MON_STATUS_RING_MASK_2 0x4
   1083
   1084const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074 = {
   1085	.tx  = {
   1086		ATH11K_TX_RING_MASK_0,
   1087		ATH11K_TX_RING_MASK_1,
   1088		ATH11K_TX_RING_MASK_2,
   1089	},
   1090	.rx_mon_status = {
   1091		0, 0, 0, 0,
   1092		ATH11K_RX_MON_STATUS_RING_MASK_0,
   1093		ATH11K_RX_MON_STATUS_RING_MASK_1,
   1094		ATH11K_RX_MON_STATUS_RING_MASK_2,
   1095	},
   1096	.rx = {
   1097		0, 0, 0, 0, 0, 0, 0,
   1098		ATH11K_RX_RING_MASK_0,
   1099		ATH11K_RX_RING_MASK_1,
   1100		ATH11K_RX_RING_MASK_2,
   1101		ATH11K_RX_RING_MASK_3,
   1102	},
   1103	.rx_err = {
   1104		ATH11K_RX_ERR_RING_MASK_0,
   1105	},
   1106	.rx_wbm_rel = {
   1107		ATH11K_RX_WBM_REL_RING_MASK_0,
   1108	},
   1109	.reo_status = {
   1110		ATH11K_REO_STATUS_RING_MASK_0,
   1111	},
   1112	.rxdma2host = {
   1113		ATH11K_RXDMA2HOST_RING_MASK_0,
   1114		ATH11K_RXDMA2HOST_RING_MASK_1,
   1115		ATH11K_RXDMA2HOST_RING_MASK_2,
   1116	},
   1117	.host2rxdma = {
   1118		ATH11K_HOST2RXDMA_RING_MASK_0,
   1119		ATH11K_HOST2RXDMA_RING_MASK_1,
   1120		ATH11K_HOST2RXDMA_RING_MASK_2,
   1121	},
   1122};
   1123
   1124const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390 = {
   1125	.tx  = {
   1126		ATH11K_TX_RING_MASK_0,
   1127	},
   1128	.rx_mon_status = {
   1129		0, 0, 0, 0,
   1130		ATH11K_RX_MON_STATUS_RING_MASK_0,
   1131		ATH11K_RX_MON_STATUS_RING_MASK_1,
   1132		ATH11K_RX_MON_STATUS_RING_MASK_2,
   1133	},
   1134	.rx = {
   1135		0, 0, 0, 0, 0, 0, 0,
   1136		ATH11K_RX_RING_MASK_0,
   1137		ATH11K_RX_RING_MASK_1,
   1138		ATH11K_RX_RING_MASK_2,
   1139		ATH11K_RX_RING_MASK_3,
   1140	},
   1141	.rx_err = {
   1142		ATH11K_RX_ERR_RING_MASK_0,
   1143	},
   1144	.rx_wbm_rel = {
   1145		ATH11K_RX_WBM_REL_RING_MASK_0,
   1146	},
   1147	.reo_status = {
   1148		ATH11K_REO_STATUS_RING_MASK_0,
   1149	},
   1150	.rxdma2host = {
   1151		ATH11K_RXDMA2HOST_RING_MASK_0,
   1152		ATH11K_RXDMA2HOST_RING_MASK_1,
   1153		ATH11K_RXDMA2HOST_RING_MASK_2,
   1154	},
   1155	.host2rxdma = {
   1156	},
   1157};
   1158
   1159/* Target firmware's Copy Engine configuration. */
   1160const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq8074[] = {
   1161	/* CE0: host->target HTC control and raw streams */
   1162	{
   1163		.pipenum = __cpu_to_le32(0),
   1164		.pipedir = __cpu_to_le32(PIPEDIR_OUT),
   1165		.nentries = __cpu_to_le32(32),
   1166		.nbytes_max = __cpu_to_le32(2048),
   1167		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
   1168		.reserved = __cpu_to_le32(0),
   1169	},
   1170
   1171	/* CE1: target->host HTT + HTC control */
   1172	{
   1173		.pipenum = __cpu_to_le32(1),
   1174		.pipedir = __cpu_to_le32(PIPEDIR_IN),
   1175		.nentries = __cpu_to_le32(32),
   1176		.nbytes_max = __cpu_to_le32(2048),
   1177		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
   1178		.reserved = __cpu_to_le32(0),
   1179	},
   1180
   1181	/* CE2: target->host WMI */
   1182	{
   1183		.pipenum = __cpu_to_le32(2),
   1184		.pipedir = __cpu_to_le32(PIPEDIR_IN),
   1185		.nentries = __cpu_to_le32(32),
   1186		.nbytes_max = __cpu_to_le32(2048),
   1187		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
   1188		.reserved = __cpu_to_le32(0),
   1189	},
   1190
   1191	/* CE3: host->target WMI */
   1192	{
   1193		.pipenum = __cpu_to_le32(3),
   1194		.pipedir = __cpu_to_le32(PIPEDIR_OUT),
   1195		.nentries = __cpu_to_le32(32),
   1196		.nbytes_max = __cpu_to_le32(2048),
   1197		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
   1198		.reserved = __cpu_to_le32(0),
   1199	},
   1200
   1201	/* CE4: host->target HTT */
   1202	{
   1203		.pipenum = __cpu_to_le32(4),
   1204		.pipedir = __cpu_to_le32(PIPEDIR_OUT),
   1205		.nentries = __cpu_to_le32(256),
   1206		.nbytes_max = __cpu_to_le32(256),
   1207		.flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
   1208		.reserved = __cpu_to_le32(0),
   1209	},
   1210
   1211	/* CE5: target->host Pktlog */
   1212	{
   1213		.pipenum = __cpu_to_le32(5),
   1214		.pipedir = __cpu_to_le32(PIPEDIR_IN),
   1215		.nentries = __cpu_to_le32(32),
   1216		.nbytes_max = __cpu_to_le32(2048),
   1217		.flags = __cpu_to_le32(0),
   1218		.reserved = __cpu_to_le32(0),
   1219	},
   1220
   1221	/* CE6: Reserved for target autonomous hif_memcpy */
   1222	{
   1223		.pipenum = __cpu_to_le32(6),
   1224		.pipedir = __cpu_to_le32(PIPEDIR_INOUT),
   1225		.nentries = __cpu_to_le32(32),
   1226		.nbytes_max = __cpu_to_le32(65535),
   1227		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
   1228		.reserved = __cpu_to_le32(0),
   1229	},
   1230
   1231	/* CE7 used only by Host */
   1232	{
   1233		.pipenum = __cpu_to_le32(7),
   1234		.pipedir = __cpu_to_le32(PIPEDIR_OUT),
   1235		.nentries = __cpu_to_le32(32),
   1236		.nbytes_max = __cpu_to_le32(2048),
   1237		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
   1238		.reserved = __cpu_to_le32(0),
   1239	},
   1240
   1241	/* CE8 target->host used only by IPA */
   1242	{
   1243		.pipenum = __cpu_to_le32(8),
   1244		.pipedir = __cpu_to_le32(PIPEDIR_INOUT),
   1245		.nentries = __cpu_to_le32(32),
   1246		.nbytes_max = __cpu_to_le32(65535),
   1247		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
   1248		.reserved = __cpu_to_le32(0),
   1249	},
   1250
   1251	/* CE9 host->target HTT */
   1252	{
   1253		.pipenum = __cpu_to_le32(9),
   1254		.pipedir = __cpu_to_le32(PIPEDIR_OUT),
   1255		.nentries = __cpu_to_le32(32),
   1256		.nbytes_max = __cpu_to_le32(2048),
   1257		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
   1258		.reserved = __cpu_to_le32(0),
   1259	},
   1260
   1261	/* CE10 target->host HTT */
   1262	{
   1263		.pipenum = __cpu_to_le32(10),
   1264		.pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H),
   1265		.nentries = __cpu_to_le32(0),
   1266		.nbytes_max = __cpu_to_le32(0),
   1267		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
   1268		.reserved = __cpu_to_le32(0),
   1269	},
   1270
   1271	/* CE11 Not used */
   1272};
   1273
   1274/* Map from service/endpoint to Copy Engine.
   1275 * This table is derived from the CE_PCI TABLE, above.
   1276 * It is passed to the Target at startup for use by firmware.
   1277 */
   1278const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq8074[] = {
   1279	{
   1280		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
   1281		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1282		.pipenum = __cpu_to_le32(3),
   1283	},
   1284	{
   1285		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
   1286		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1287		.pipenum = __cpu_to_le32(2),
   1288	},
   1289	{
   1290		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
   1291		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1292		.pipenum = __cpu_to_le32(3),
   1293	},
   1294	{
   1295		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
   1296		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1297		.pipenum = __cpu_to_le32(2),
   1298	},
   1299	{
   1300		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
   1301		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1302		.pipenum = __cpu_to_le32(3),
   1303	},
   1304	{
   1305		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
   1306		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1307		.pipenum = __cpu_to_le32(2),
   1308	},
   1309	{
   1310		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
   1311		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1312		.pipenum = __cpu_to_le32(3),
   1313	},
   1314	{
   1315		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
   1316		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1317		.pipenum = __cpu_to_le32(2),
   1318	},
   1319	{
   1320		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
   1321		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1322		.pipenum = __cpu_to_le32(3),
   1323	},
   1324	{
   1325		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
   1326		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1327		.pipenum = __cpu_to_le32(2),
   1328	},
   1329	{
   1330		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1),
   1331		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1332		.pipenum = __cpu_to_le32(7),
   1333	},
   1334	{
   1335		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1),
   1336		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1337		.pipenum = __cpu_to_le32(2),
   1338	},
   1339	{
   1340		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2),
   1341		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1342		.pipenum = __cpu_to_le32(9),
   1343	},
   1344	{
   1345		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2),
   1346		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1347		.pipenum = __cpu_to_le32(2),
   1348	},
   1349	{
   1350		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
   1351		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1352		.pipenum = __cpu_to_le32(0),
   1353	},
   1354	{
   1355		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
   1356		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1357		.pipenum = __cpu_to_le32(1),
   1358	},
   1359	{ /* not used */
   1360		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
   1361		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1362		.pipenum = __cpu_to_le32(0),
   1363	},
   1364	{ /* not used */
   1365		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
   1366		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1367		.pipenum = __cpu_to_le32(1),
   1368	},
   1369	{
   1370		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
   1371		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1372		.pipenum = __cpu_to_le32(4),
   1373	},
   1374	{
   1375		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
   1376		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1377		.pipenum = __cpu_to_le32(1),
   1378	},
   1379	{
   1380		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG),
   1381		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1382		.pipenum = __cpu_to_le32(5),
   1383	},
   1384
   1385	/* (Additions here) */
   1386
   1387	{ /* terminator entry */ }
   1388};
   1389
   1390const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq6018[] = {
   1391	{
   1392		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
   1393		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1394		.pipenum = __cpu_to_le32(3),
   1395	},
   1396	{
   1397		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
   1398		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1399		.pipenum = __cpu_to_le32(2),
   1400	},
   1401	{
   1402		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
   1403		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1404		.pipenum = __cpu_to_le32(3),
   1405	},
   1406	{
   1407		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
   1408		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1409		.pipenum = __cpu_to_le32(2),
   1410	},
   1411	{
   1412		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
   1413		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1414		.pipenum = __cpu_to_le32(3),
   1415	},
   1416	{
   1417		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
   1418		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1419		.pipenum = __cpu_to_le32(2),
   1420	},
   1421	{
   1422		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
   1423		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1424		.pipenum = __cpu_to_le32(3),
   1425	},
   1426	{
   1427		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
   1428		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1429		.pipenum = __cpu_to_le32(2),
   1430	},
   1431	{
   1432		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
   1433		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1434		.pipenum = __cpu_to_le32(3),
   1435	},
   1436	{
   1437		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
   1438		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1439		.pipenum = __cpu_to_le32(2),
   1440	},
   1441	{
   1442		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1),
   1443		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1444		.pipenum = __cpu_to_le32(7),
   1445	},
   1446	{
   1447		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1),
   1448		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1449		.pipenum = __cpu_to_le32(2),
   1450	},
   1451	{
   1452		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
   1453		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1454		.pipenum = __cpu_to_le32(0),
   1455	},
   1456	{
   1457		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
   1458		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1459		.pipenum = __cpu_to_le32(1),
   1460	},
   1461	{ /* not used */
   1462		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
   1463		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1464		.pipenum = __cpu_to_le32(0),
   1465	},
   1466	{ /* not used */
   1467		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
   1468		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1469		.pipenum = __cpu_to_le32(1),
   1470	},
   1471	{
   1472		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
   1473		.pipedir = __cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1474		.pipenum = __cpu_to_le32(4),
   1475	},
   1476	{
   1477		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
   1478		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1479		.pipenum = __cpu_to_le32(1),
   1480	},
   1481	{
   1482		.service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG),
   1483		.pipedir = __cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1484		.pipenum = __cpu_to_le32(5),
   1485	},
   1486
   1487	/* (Additions here) */
   1488
   1489	{ /* terminator entry */ }
   1490};
   1491
   1492/* Target firmware's Copy Engine configuration. */
   1493const struct ce_pipe_config ath11k_target_ce_config_wlan_qca6390[] = {
   1494	/* CE0: host->target HTC control and raw streams */
   1495	{
   1496		.pipenum = __cpu_to_le32(0),
   1497		.pipedir = __cpu_to_le32(PIPEDIR_OUT),
   1498		.nentries = __cpu_to_le32(32),
   1499		.nbytes_max = __cpu_to_le32(2048),
   1500		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
   1501		.reserved = __cpu_to_le32(0),
   1502	},
   1503
   1504	/* CE1: target->host HTT + HTC control */
   1505	{
   1506		.pipenum = __cpu_to_le32(1),
   1507		.pipedir = __cpu_to_le32(PIPEDIR_IN),
   1508		.nentries = __cpu_to_le32(32),
   1509		.nbytes_max = __cpu_to_le32(2048),
   1510		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
   1511		.reserved = __cpu_to_le32(0),
   1512	},
   1513
   1514	/* CE2: target->host WMI */
   1515	{
   1516		.pipenum = __cpu_to_le32(2),
   1517		.pipedir = __cpu_to_le32(PIPEDIR_IN),
   1518		.nentries = __cpu_to_le32(32),
   1519		.nbytes_max = __cpu_to_le32(2048),
   1520		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
   1521		.reserved = __cpu_to_le32(0),
   1522	},
   1523
   1524	/* CE3: host->target WMI */
   1525	{
   1526		.pipenum = __cpu_to_le32(3),
   1527		.pipedir = __cpu_to_le32(PIPEDIR_OUT),
   1528		.nentries = __cpu_to_le32(32),
   1529		.nbytes_max = __cpu_to_le32(2048),
   1530		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
   1531		.reserved = __cpu_to_le32(0),
   1532	},
   1533
   1534	/* CE4: host->target HTT */
   1535	{
   1536		.pipenum = __cpu_to_le32(4),
   1537		.pipedir = __cpu_to_le32(PIPEDIR_OUT),
   1538		.nentries = __cpu_to_le32(256),
   1539		.nbytes_max = __cpu_to_le32(256),
   1540		.flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
   1541		.reserved = __cpu_to_le32(0),
   1542	},
   1543
   1544	/* CE5: target->host Pktlog */
   1545	{
   1546		.pipenum = __cpu_to_le32(5),
   1547		.pipedir = __cpu_to_le32(PIPEDIR_IN),
   1548		.nentries = __cpu_to_le32(32),
   1549		.nbytes_max = __cpu_to_le32(2048),
   1550		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
   1551		.reserved = __cpu_to_le32(0),
   1552	},
   1553
   1554	/* CE6: Reserved for target autonomous hif_memcpy */
   1555	{
   1556		.pipenum = __cpu_to_le32(6),
   1557		.pipedir = __cpu_to_le32(PIPEDIR_INOUT),
   1558		.nentries = __cpu_to_le32(32),
   1559		.nbytes_max = __cpu_to_le32(16384),
   1560		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
   1561		.reserved = __cpu_to_le32(0),
   1562	},
   1563
   1564	/* CE7 used only by Host */
   1565	{
   1566		.pipenum = __cpu_to_le32(7),
   1567		.pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H),
   1568		.nentries = __cpu_to_le32(0),
   1569		.nbytes_max = __cpu_to_le32(0),
   1570		.flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
   1571		.reserved = __cpu_to_le32(0),
   1572	},
   1573
   1574	/* CE8 target->host used only by IPA */
   1575	{
   1576		.pipenum = __cpu_to_le32(8),
   1577		.pipedir = __cpu_to_le32(PIPEDIR_INOUT),
   1578		.nentries = __cpu_to_le32(32),
   1579		.nbytes_max = __cpu_to_le32(16384),
   1580		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
   1581		.reserved = __cpu_to_le32(0),
   1582	},
   1583	/* CE 9, 10, 11 are used by MHI driver */
   1584};
   1585
   1586/* Map from service/endpoint to Copy Engine.
   1587 * This table is derived from the CE_PCI TABLE, above.
   1588 * It is passed to the Target at startup for use by firmware.
   1589 */
   1590const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qca6390[] = {
   1591	{
   1592		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
   1593		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1594		__cpu_to_le32(3),
   1595	},
   1596	{
   1597		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
   1598		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1599		__cpu_to_le32(2),
   1600	},
   1601	{
   1602		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
   1603		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1604		__cpu_to_le32(3),
   1605	},
   1606	{
   1607		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
   1608		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1609		__cpu_to_le32(2),
   1610	},
   1611	{
   1612		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
   1613		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1614		__cpu_to_le32(3),
   1615	},
   1616	{
   1617		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
   1618		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1619		__cpu_to_le32(2),
   1620	},
   1621	{
   1622		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
   1623		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1624		__cpu_to_le32(3),
   1625	},
   1626	{
   1627		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
   1628		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1629		__cpu_to_le32(2),
   1630	},
   1631	{
   1632		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
   1633		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1634		__cpu_to_le32(3),
   1635	},
   1636	{
   1637		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
   1638		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1639		__cpu_to_le32(2),
   1640	},
   1641	{
   1642		__cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
   1643		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1644		__cpu_to_le32(0),
   1645	},
   1646	{
   1647		__cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
   1648		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1649		__cpu_to_le32(2),
   1650	},
   1651	{
   1652		__cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
   1653		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1654		__cpu_to_le32(4),
   1655	},
   1656	{
   1657		__cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
   1658		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1659		__cpu_to_le32(1),
   1660	},
   1661
   1662	/* (Additions here) */
   1663
   1664	{ /* must be last */
   1665		__cpu_to_le32(0),
   1666		__cpu_to_le32(0),
   1667		__cpu_to_le32(0),
   1668	},
   1669};
   1670
   1671/* Target firmware's Copy Engine configuration. */
   1672const struct ce_pipe_config ath11k_target_ce_config_wlan_qcn9074[] = {
   1673	/* CE0: host->target HTC control and raw streams */
   1674	{
   1675		.pipenum = __cpu_to_le32(0),
   1676		.pipedir = __cpu_to_le32(PIPEDIR_OUT),
   1677		.nentries = __cpu_to_le32(32),
   1678		.nbytes_max = __cpu_to_le32(2048),
   1679		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
   1680		.reserved = __cpu_to_le32(0),
   1681	},
   1682
   1683	/* CE1: target->host HTT + HTC control */
   1684	{
   1685		.pipenum = __cpu_to_le32(1),
   1686		.pipedir = __cpu_to_le32(PIPEDIR_IN),
   1687		.nentries = __cpu_to_le32(32),
   1688		.nbytes_max = __cpu_to_le32(2048),
   1689		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
   1690		.reserved = __cpu_to_le32(0),
   1691	},
   1692
   1693	/* CE2: target->host WMI */
   1694	{
   1695		.pipenum = __cpu_to_le32(2),
   1696		.pipedir = __cpu_to_le32(PIPEDIR_IN),
   1697		.nentries = __cpu_to_le32(32),
   1698		.nbytes_max = __cpu_to_le32(2048),
   1699		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
   1700		.reserved = __cpu_to_le32(0),
   1701	},
   1702
   1703	/* CE3: host->target WMI */
   1704	{
   1705		.pipenum = __cpu_to_le32(3),
   1706		.pipedir = __cpu_to_le32(PIPEDIR_OUT),
   1707		.nentries = __cpu_to_le32(32),
   1708		.nbytes_max = __cpu_to_le32(2048),
   1709		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
   1710		.reserved = __cpu_to_le32(0),
   1711	},
   1712
   1713	/* CE4: host->target HTT */
   1714	{
   1715		.pipenum = __cpu_to_le32(4),
   1716		.pipedir = __cpu_to_le32(PIPEDIR_OUT),
   1717		.nentries = __cpu_to_le32(256),
   1718		.nbytes_max = __cpu_to_le32(256),
   1719		.flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
   1720		.reserved = __cpu_to_le32(0),
   1721	},
   1722
   1723	/* CE5: target->host Pktlog */
   1724	{
   1725		.pipenum = __cpu_to_le32(5),
   1726		.pipedir = __cpu_to_le32(PIPEDIR_IN),
   1727		.nentries = __cpu_to_le32(32),
   1728		.nbytes_max = __cpu_to_le32(2048),
   1729		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
   1730		.reserved = __cpu_to_le32(0),
   1731	},
   1732
   1733	/* CE6: Reserved for target autonomous hif_memcpy */
   1734	{
   1735		.pipenum = __cpu_to_le32(6),
   1736		.pipedir = __cpu_to_le32(PIPEDIR_INOUT),
   1737		.nentries = __cpu_to_le32(32),
   1738		.nbytes_max = __cpu_to_le32(16384),
   1739		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
   1740		.reserved = __cpu_to_le32(0),
   1741	},
   1742
   1743	/* CE7 used only by Host */
   1744	{
   1745		.pipenum = __cpu_to_le32(7),
   1746		.pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H),
   1747		.nentries = __cpu_to_le32(0),
   1748		.nbytes_max = __cpu_to_le32(0),
   1749		.flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
   1750		.reserved = __cpu_to_le32(0),
   1751	},
   1752
   1753	/* CE8 target->host used only by IPA */
   1754	{
   1755		.pipenum = __cpu_to_le32(8),
   1756		.pipedir = __cpu_to_le32(PIPEDIR_INOUT),
   1757		.nentries = __cpu_to_le32(32),
   1758		.nbytes_max = __cpu_to_le32(16384),
   1759		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
   1760		.reserved = __cpu_to_le32(0),
   1761	},
   1762	/* CE 9, 10, 11 are used by MHI driver */
   1763};
   1764
   1765/* Map from service/endpoint to Copy Engine.
   1766 * This table is derived from the CE_PCI TABLE, above.
   1767 * It is passed to the Target at startup for use by firmware.
   1768 */
   1769const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qcn9074[] = {
   1770	{
   1771		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
   1772		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1773		__cpu_to_le32(3),
   1774	},
   1775	{
   1776		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
   1777		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1778		__cpu_to_le32(2),
   1779	},
   1780	{
   1781		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
   1782		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1783		__cpu_to_le32(3),
   1784	},
   1785	{
   1786		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
   1787		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1788		__cpu_to_le32(2),
   1789	},
   1790	{
   1791		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
   1792		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1793		__cpu_to_le32(3),
   1794	},
   1795	{
   1796		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
   1797		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1798		__cpu_to_le32(2),
   1799	},
   1800	{
   1801		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
   1802		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1803		__cpu_to_le32(3),
   1804	},
   1805	{
   1806		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
   1807		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1808		__cpu_to_le32(2),
   1809	},
   1810	{
   1811		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
   1812		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1813		__cpu_to_le32(3),
   1814	},
   1815	{
   1816		__cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
   1817		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1818		__cpu_to_le32(2),
   1819	},
   1820	{
   1821		__cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
   1822		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1823		__cpu_to_le32(0),
   1824	},
   1825	{
   1826		__cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
   1827		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1828		__cpu_to_le32(1),
   1829	},
   1830	{
   1831		__cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
   1832		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1833		__cpu_to_le32(0),
   1834	},
   1835	{
   1836		__cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
   1837		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1838		__cpu_to_le32(1),
   1839	},
   1840	{
   1841		__cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
   1842		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
   1843		__cpu_to_le32(4),
   1844	},
   1845	{
   1846		__cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
   1847		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1848		__cpu_to_le32(1),
   1849	},
   1850	{
   1851		__cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG),
   1852		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
   1853		__cpu_to_le32(5),
   1854	},
   1855
   1856	/* (Additions here) */
   1857
   1858	{ /* must be last */
   1859		__cpu_to_le32(0),
   1860		__cpu_to_le32(0),
   1861		__cpu_to_le32(0),
   1862	},
   1863};
   1864
   1865const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qcn9074 = {
   1866	.tx  = {
   1867		ATH11K_TX_RING_MASK_0,
   1868		ATH11K_TX_RING_MASK_1,
   1869		ATH11K_TX_RING_MASK_2,
   1870	},
   1871	.rx_mon_status = {
   1872		0, 0, 0,
   1873		ATH11K_RX_MON_STATUS_RING_MASK_0,
   1874		ATH11K_RX_MON_STATUS_RING_MASK_1,
   1875		ATH11K_RX_MON_STATUS_RING_MASK_2,
   1876	},
   1877	.rx = {
   1878		0, 0, 0, 0,
   1879		ATH11K_RX_RING_MASK_0,
   1880		ATH11K_RX_RING_MASK_1,
   1881		ATH11K_RX_RING_MASK_2,
   1882		ATH11K_RX_RING_MASK_3,
   1883	},
   1884	.rx_err = {
   1885		0, 0, 0,
   1886		ATH11K_RX_ERR_RING_MASK_0,
   1887	},
   1888	.rx_wbm_rel = {
   1889		0, 0, 0,
   1890		ATH11K_RX_WBM_REL_RING_MASK_0,
   1891	},
   1892	.reo_status = {
   1893		0, 0, 0,
   1894		ATH11K_REO_STATUS_RING_MASK_0,
   1895	},
   1896	.rxdma2host = {
   1897		0, 0, 0,
   1898		ATH11K_RXDMA2HOST_RING_MASK_0,
   1899	},
   1900	.host2rxdma = {
   1901		0, 0, 0,
   1902		ATH11K_HOST2RXDMA_RING_MASK_0,
   1903	},
   1904};
   1905
   1906const struct ath11k_hw_regs ipq8074_regs = {
   1907	/* SW2TCL(x) R0 ring configuration address */
   1908	.hal_tcl1_ring_base_lsb = 0x00000510,
   1909	.hal_tcl1_ring_base_msb = 0x00000514,
   1910	.hal_tcl1_ring_id = 0x00000518,
   1911	.hal_tcl1_ring_misc = 0x00000520,
   1912	.hal_tcl1_ring_tp_addr_lsb = 0x0000052c,
   1913	.hal_tcl1_ring_tp_addr_msb = 0x00000530,
   1914	.hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000540,
   1915	.hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000544,
   1916	.hal_tcl1_ring_msi1_base_lsb = 0x00000558,
   1917	.hal_tcl1_ring_msi1_base_msb = 0x0000055c,
   1918	.hal_tcl1_ring_msi1_data = 0x00000560,
   1919	.hal_tcl2_ring_base_lsb = 0x00000568,
   1920	.hal_tcl_ring_base_lsb = 0x00000618,
   1921
   1922	/* TCL STATUS ring address */
   1923	.hal_tcl_status_ring_base_lsb = 0x00000720,
   1924
   1925	/* REO2SW(x) R0 ring configuration address */
   1926	.hal_reo1_ring_base_lsb = 0x0000029c,
   1927	.hal_reo1_ring_base_msb = 0x000002a0,
   1928	.hal_reo1_ring_id = 0x000002a4,
   1929	.hal_reo1_ring_misc = 0x000002ac,
   1930	.hal_reo1_ring_hp_addr_lsb = 0x000002b0,
   1931	.hal_reo1_ring_hp_addr_msb = 0x000002b4,
   1932	.hal_reo1_ring_producer_int_setup = 0x000002c0,
   1933	.hal_reo1_ring_msi1_base_lsb = 0x000002e4,
   1934	.hal_reo1_ring_msi1_base_msb = 0x000002e8,
   1935	.hal_reo1_ring_msi1_data = 0x000002ec,
   1936	.hal_reo2_ring_base_lsb = 0x000002f4,
   1937	.hal_reo1_aging_thresh_ix_0 = 0x00000564,
   1938	.hal_reo1_aging_thresh_ix_1 = 0x00000568,
   1939	.hal_reo1_aging_thresh_ix_2 = 0x0000056c,
   1940	.hal_reo1_aging_thresh_ix_3 = 0x00000570,
   1941
   1942	/* REO2SW(x) R2 ring pointers (head/tail) address */
   1943	.hal_reo1_ring_hp = 0x00003038,
   1944	.hal_reo1_ring_tp = 0x0000303c,
   1945	.hal_reo2_ring_hp = 0x00003040,
   1946
   1947	/* REO2TCL R0 ring configuration address */
   1948	.hal_reo_tcl_ring_base_lsb = 0x000003fc,
   1949	.hal_reo_tcl_ring_hp = 0x00003058,
   1950
   1951	/* REO CMD ring address */
   1952	.hal_reo_cmd_ring_base_lsb = 0x00000194,
   1953	.hal_reo_cmd_ring_hp = 0x00003020,
   1954
   1955	/* REO status address */
   1956	.hal_reo_status_ring_base_lsb = 0x00000504,
   1957	.hal_reo_status_hp = 0x00003070,
   1958
   1959	/* SW2REO ring address */
   1960	.hal_sw2reo_ring_base_lsb = 0x000001ec,
   1961	.hal_sw2reo_ring_hp = 0x00003028,
   1962
   1963	/* WCSS relative address */
   1964	.hal_seq_wcss_umac_ce0_src_reg = 0x00a00000,
   1965	.hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000,
   1966	.hal_seq_wcss_umac_ce1_src_reg = 0x00a02000,
   1967	.hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000,
   1968
   1969	/* WBM Idle address */
   1970	.hal_wbm_idle_link_ring_base_lsb = 0x00000860,
   1971	.hal_wbm_idle_link_ring_misc = 0x00000870,
   1972
   1973	/* SW2WBM release address */
   1974	.hal_wbm_release_ring_base_lsb = 0x000001d8,
   1975
   1976	/* WBM2SW release address */
   1977	.hal_wbm0_release_ring_base_lsb = 0x00000910,
   1978	.hal_wbm1_release_ring_base_lsb = 0x00000968,
   1979
   1980	/* PCIe base address */
   1981	.pcie_qserdes_sysclk_en_sel = 0x0,
   1982	.pcie_pcs_osc_dtct_config_base = 0x0,
   1983
   1984	/* Shadow register area */
   1985	.hal_shadow_base_addr = 0x0,
   1986
   1987	/* REO misc control register, not used in IPQ8074 */
   1988	.hal_reo1_misc_ctl = 0x0,
   1989};
   1990
   1991const struct ath11k_hw_regs qca6390_regs = {
   1992	/* SW2TCL(x) R0 ring configuration address */
   1993	.hal_tcl1_ring_base_lsb = 0x00000684,
   1994	.hal_tcl1_ring_base_msb = 0x00000688,
   1995	.hal_tcl1_ring_id = 0x0000068c,
   1996	.hal_tcl1_ring_misc = 0x00000694,
   1997	.hal_tcl1_ring_tp_addr_lsb = 0x000006a0,
   1998	.hal_tcl1_ring_tp_addr_msb = 0x000006a4,
   1999	.hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006b4,
   2000	.hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006b8,
   2001	.hal_tcl1_ring_msi1_base_lsb = 0x000006cc,
   2002	.hal_tcl1_ring_msi1_base_msb = 0x000006d0,
   2003	.hal_tcl1_ring_msi1_data = 0x000006d4,
   2004	.hal_tcl2_ring_base_lsb = 0x000006dc,
   2005	.hal_tcl_ring_base_lsb = 0x0000078c,
   2006
   2007	/* TCL STATUS ring address */
   2008	.hal_tcl_status_ring_base_lsb = 0x00000894,
   2009
   2010	/* REO2SW(x) R0 ring configuration address */
   2011	.hal_reo1_ring_base_lsb = 0x00000244,
   2012	.hal_reo1_ring_base_msb = 0x00000248,
   2013	.hal_reo1_ring_id = 0x0000024c,
   2014	.hal_reo1_ring_misc = 0x00000254,
   2015	.hal_reo1_ring_hp_addr_lsb = 0x00000258,
   2016	.hal_reo1_ring_hp_addr_msb = 0x0000025c,
   2017	.hal_reo1_ring_producer_int_setup = 0x00000268,
   2018	.hal_reo1_ring_msi1_base_lsb = 0x0000028c,
   2019	.hal_reo1_ring_msi1_base_msb = 0x00000290,
   2020	.hal_reo1_ring_msi1_data = 0x00000294,
   2021	.hal_reo2_ring_base_lsb = 0x0000029c,
   2022	.hal_reo1_aging_thresh_ix_0 = 0x0000050c,
   2023	.hal_reo1_aging_thresh_ix_1 = 0x00000510,
   2024	.hal_reo1_aging_thresh_ix_2 = 0x00000514,
   2025	.hal_reo1_aging_thresh_ix_3 = 0x00000518,
   2026
   2027	/* REO2SW(x) R2 ring pointers (head/tail) address */
   2028	.hal_reo1_ring_hp = 0x00003030,
   2029	.hal_reo1_ring_tp = 0x00003034,
   2030	.hal_reo2_ring_hp = 0x00003038,
   2031
   2032	/* REO2TCL R0 ring configuration address */
   2033	.hal_reo_tcl_ring_base_lsb = 0x000003a4,
   2034	.hal_reo_tcl_ring_hp = 0x00003050,
   2035
   2036	/* REO CMD ring address */
   2037	.hal_reo_cmd_ring_base_lsb = 0x00000194,
   2038	.hal_reo_cmd_ring_hp = 0x00003020,
   2039
   2040	/* REO status address */
   2041	.hal_reo_status_ring_base_lsb = 0x000004ac,
   2042	.hal_reo_status_hp = 0x00003068,
   2043
   2044	/* SW2REO ring address */
   2045	.hal_sw2reo_ring_base_lsb = 0x000001ec,
   2046	.hal_sw2reo_ring_hp = 0x00003028,
   2047
   2048	/* WCSS relative address */
   2049	.hal_seq_wcss_umac_ce0_src_reg = 0x00a00000,
   2050	.hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000,
   2051	.hal_seq_wcss_umac_ce1_src_reg = 0x00a02000,
   2052	.hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000,
   2053
   2054	/* WBM Idle address */
   2055	.hal_wbm_idle_link_ring_base_lsb = 0x00000860,
   2056	.hal_wbm_idle_link_ring_misc = 0x00000870,
   2057
   2058	/* SW2WBM release address */
   2059	.hal_wbm_release_ring_base_lsb = 0x000001d8,
   2060
   2061	/* WBM2SW release address */
   2062	.hal_wbm0_release_ring_base_lsb = 0x00000910,
   2063	.hal_wbm1_release_ring_base_lsb = 0x00000968,
   2064
   2065	/* PCIe base address */
   2066	.pcie_qserdes_sysclk_en_sel = 0x01e0c0ac,
   2067	.pcie_pcs_osc_dtct_config_base = 0x01e0c628,
   2068
   2069	/* Shadow register area */
   2070	.hal_shadow_base_addr = 0x000008fc,
   2071
   2072	/* REO misc control register, not used in QCA6390 */
   2073	.hal_reo1_misc_ctl = 0x0,
   2074};
   2075
   2076const struct ath11k_hw_regs qcn9074_regs = {
   2077	/* SW2TCL(x) R0 ring configuration address */
   2078	.hal_tcl1_ring_base_lsb = 0x000004f0,
   2079	.hal_tcl1_ring_base_msb = 0x000004f4,
   2080	.hal_tcl1_ring_id = 0x000004f8,
   2081	.hal_tcl1_ring_misc = 0x00000500,
   2082	.hal_tcl1_ring_tp_addr_lsb = 0x0000050c,
   2083	.hal_tcl1_ring_tp_addr_msb = 0x00000510,
   2084	.hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000520,
   2085	.hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000524,
   2086	.hal_tcl1_ring_msi1_base_lsb = 0x00000538,
   2087	.hal_tcl1_ring_msi1_base_msb = 0x0000053c,
   2088	.hal_tcl1_ring_msi1_data = 0x00000540,
   2089	.hal_tcl2_ring_base_lsb = 0x00000548,
   2090	.hal_tcl_ring_base_lsb = 0x000005f8,
   2091
   2092	/* TCL STATUS ring address */
   2093	.hal_tcl_status_ring_base_lsb = 0x00000700,
   2094
   2095	/* REO2SW(x) R0 ring configuration address */
   2096	.hal_reo1_ring_base_lsb = 0x0000029c,
   2097	.hal_reo1_ring_base_msb = 0x000002a0,
   2098	.hal_reo1_ring_id = 0x000002a4,
   2099	.hal_reo1_ring_misc = 0x000002ac,
   2100	.hal_reo1_ring_hp_addr_lsb = 0x000002b0,
   2101	.hal_reo1_ring_hp_addr_msb = 0x000002b4,
   2102	.hal_reo1_ring_producer_int_setup = 0x000002c0,
   2103	.hal_reo1_ring_msi1_base_lsb = 0x000002e4,
   2104	.hal_reo1_ring_msi1_base_msb = 0x000002e8,
   2105	.hal_reo1_ring_msi1_data = 0x000002ec,
   2106	.hal_reo2_ring_base_lsb = 0x000002f4,
   2107	.hal_reo1_aging_thresh_ix_0 = 0x00000564,
   2108	.hal_reo1_aging_thresh_ix_1 = 0x00000568,
   2109	.hal_reo1_aging_thresh_ix_2 = 0x0000056c,
   2110	.hal_reo1_aging_thresh_ix_3 = 0x00000570,
   2111
   2112	/* REO2SW(x) R2 ring pointers (head/tail) address */
   2113	.hal_reo1_ring_hp = 0x00003038,
   2114	.hal_reo1_ring_tp = 0x0000303c,
   2115	.hal_reo2_ring_hp = 0x00003040,
   2116
   2117	/* REO2TCL R0 ring configuration address */
   2118	.hal_reo_tcl_ring_base_lsb = 0x000003fc,
   2119	.hal_reo_tcl_ring_hp = 0x00003058,
   2120
   2121	/* REO CMD ring address */
   2122	.hal_reo_cmd_ring_base_lsb = 0x00000194,
   2123	.hal_reo_cmd_ring_hp = 0x00003020,
   2124
   2125	/* REO status address */
   2126	.hal_reo_status_ring_base_lsb = 0x00000504,
   2127	.hal_reo_status_hp = 0x00003070,
   2128
   2129	/* SW2REO ring address */
   2130	.hal_sw2reo_ring_base_lsb = 0x000001ec,
   2131	.hal_sw2reo_ring_hp = 0x00003028,
   2132
   2133	/* WCSS relative address */
   2134	.hal_seq_wcss_umac_ce0_src_reg = 0x01b80000,
   2135	.hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000,
   2136	.hal_seq_wcss_umac_ce1_src_reg = 0x01b82000,
   2137	.hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000,
   2138
   2139	/* WBM Idle address */
   2140	.hal_wbm_idle_link_ring_base_lsb = 0x00000874,
   2141	.hal_wbm_idle_link_ring_misc = 0x00000884,
   2142
   2143	/* SW2WBM release address */
   2144	.hal_wbm_release_ring_base_lsb = 0x000001ec,
   2145
   2146	/* WBM2SW release address */
   2147	.hal_wbm0_release_ring_base_lsb = 0x00000924,
   2148	.hal_wbm1_release_ring_base_lsb = 0x0000097c,
   2149
   2150	/* PCIe base address */
   2151	.pcie_qserdes_sysclk_en_sel = 0x01e0e0a8,
   2152	.pcie_pcs_osc_dtct_config_base = 0x01e0f45c,
   2153
   2154	/* Shadow register area */
   2155	.hal_shadow_base_addr = 0x0,
   2156
   2157	/* REO misc control register, not used in QCN9074 */
   2158	.hal_reo1_misc_ctl = 0x0,
   2159};
   2160
   2161const struct ath11k_hw_regs wcn6855_regs = {
   2162	/* SW2TCL(x) R0 ring configuration address */
   2163	.hal_tcl1_ring_base_lsb = 0x00000690,
   2164	.hal_tcl1_ring_base_msb = 0x00000694,
   2165	.hal_tcl1_ring_id = 0x00000698,
   2166	.hal_tcl1_ring_misc = 0x000006a0,
   2167	.hal_tcl1_ring_tp_addr_lsb = 0x000006ac,
   2168	.hal_tcl1_ring_tp_addr_msb = 0x000006b0,
   2169	.hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c0,
   2170	.hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c4,
   2171	.hal_tcl1_ring_msi1_base_lsb = 0x000006d8,
   2172	.hal_tcl1_ring_msi1_base_msb = 0x000006dc,
   2173	.hal_tcl1_ring_msi1_data = 0x000006e0,
   2174	.hal_tcl2_ring_base_lsb = 0x000006e8,
   2175	.hal_tcl_ring_base_lsb = 0x00000798,
   2176
   2177	/* TCL STATUS ring address */
   2178	.hal_tcl_status_ring_base_lsb = 0x000008a0,
   2179
   2180	/* REO2SW(x) R0 ring configuration address */
   2181	.hal_reo1_ring_base_lsb = 0x00000244,
   2182	.hal_reo1_ring_base_msb = 0x00000248,
   2183	.hal_reo1_ring_id = 0x0000024c,
   2184	.hal_reo1_ring_misc = 0x00000254,
   2185	.hal_reo1_ring_hp_addr_lsb = 0x00000258,
   2186	.hal_reo1_ring_hp_addr_msb = 0x0000025c,
   2187	.hal_reo1_ring_producer_int_setup = 0x00000268,
   2188	.hal_reo1_ring_msi1_base_lsb = 0x0000028c,
   2189	.hal_reo1_ring_msi1_base_msb = 0x00000290,
   2190	.hal_reo1_ring_msi1_data = 0x00000294,
   2191	.hal_reo2_ring_base_lsb = 0x0000029c,
   2192	.hal_reo1_aging_thresh_ix_0 = 0x000005bc,
   2193	.hal_reo1_aging_thresh_ix_1 = 0x000005c0,
   2194	.hal_reo1_aging_thresh_ix_2 = 0x000005c4,
   2195	.hal_reo1_aging_thresh_ix_3 = 0x000005c8,
   2196
   2197	/* REO2SW(x) R2 ring pointers (head/tail) address */
   2198	.hal_reo1_ring_hp = 0x00003030,
   2199	.hal_reo1_ring_tp = 0x00003034,
   2200	.hal_reo2_ring_hp = 0x00003038,
   2201
   2202	/* REO2TCL R0 ring configuration address */
   2203	.hal_reo_tcl_ring_base_lsb = 0x00000454,
   2204	.hal_reo_tcl_ring_hp = 0x00003060,
   2205
   2206	/* REO CMD ring address */
   2207	.hal_reo_cmd_ring_base_lsb = 0x00000194,
   2208	.hal_reo_cmd_ring_hp = 0x00003020,
   2209
   2210	/* REO status address */
   2211	.hal_reo_status_ring_base_lsb = 0x0000055c,
   2212	.hal_reo_status_hp = 0x00003078,
   2213
   2214	/* SW2REO ring address */
   2215	.hal_sw2reo_ring_base_lsb = 0x000001ec,
   2216	.hal_sw2reo_ring_hp = 0x00003028,
   2217
   2218	/* WCSS relative address */
   2219	.hal_seq_wcss_umac_ce0_src_reg = 0x1b80000,
   2220	.hal_seq_wcss_umac_ce0_dst_reg = 0x1b81000,
   2221	.hal_seq_wcss_umac_ce1_src_reg = 0x1b82000,
   2222	.hal_seq_wcss_umac_ce1_dst_reg = 0x1b83000,
   2223
   2224	/* WBM Idle address */
   2225	.hal_wbm_idle_link_ring_base_lsb = 0x00000870,
   2226	.hal_wbm_idle_link_ring_misc = 0x00000880,
   2227
   2228	/* SW2WBM release address */
   2229	.hal_wbm_release_ring_base_lsb = 0x000001e8,
   2230
   2231	/* WBM2SW release address */
   2232	.hal_wbm0_release_ring_base_lsb = 0x00000920,
   2233	.hal_wbm1_release_ring_base_lsb = 0x00000978,
   2234
   2235	/* PCIe base address */
   2236	.pcie_qserdes_sysclk_en_sel = 0x01e0c0ac,
   2237	.pcie_pcs_osc_dtct_config_base = 0x01e0c628,
   2238
   2239	/* Shadow register area */
   2240	.hal_shadow_base_addr = 0x000008fc,
   2241
   2242	/* REO misc control register, used for fragment
   2243	 * destination ring config in WCN6855.
   2244	 */
   2245	.hal_reo1_misc_ctl = 0x00000630,
   2246};
   2247
   2248const struct ath11k_hw_regs wcn6750_regs = {
   2249	/* SW2TCL(x) R0 ring configuration address */
   2250	.hal_tcl1_ring_base_lsb = 0x00000694,
   2251	.hal_tcl1_ring_base_msb = 0x00000698,
   2252	.hal_tcl1_ring_id = 0x0000069c,
   2253	.hal_tcl1_ring_misc = 0x000006a4,
   2254	.hal_tcl1_ring_tp_addr_lsb = 0x000006b0,
   2255	.hal_tcl1_ring_tp_addr_msb = 0x000006b4,
   2256	.hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c4,
   2257	.hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c8,
   2258	.hal_tcl1_ring_msi1_base_lsb = 0x000006dc,
   2259	.hal_tcl1_ring_msi1_base_msb = 0x000006e0,
   2260	.hal_tcl1_ring_msi1_data = 0x000006e4,
   2261	.hal_tcl2_ring_base_lsb = 0x000006ec,
   2262	.hal_tcl_ring_base_lsb = 0x0000079c,
   2263
   2264	/* TCL STATUS ring address */
   2265	.hal_tcl_status_ring_base_lsb = 0x000008a4,
   2266
   2267	/* REO2SW(x) R0 ring configuration address */
   2268	.hal_reo1_ring_base_lsb = 0x000001ec,
   2269	.hal_reo1_ring_base_msb = 0x000001f0,
   2270	.hal_reo1_ring_id = 0x000001f4,
   2271	.hal_reo1_ring_misc = 0x000001fc,
   2272	.hal_reo1_ring_hp_addr_lsb = 0x00000200,
   2273	.hal_reo1_ring_hp_addr_msb = 0x00000204,
   2274	.hal_reo1_ring_producer_int_setup = 0x00000210,
   2275	.hal_reo1_ring_msi1_base_lsb = 0x00000234,
   2276	.hal_reo1_ring_msi1_base_msb = 0x00000238,
   2277	.hal_reo1_ring_msi1_data = 0x0000023c,
   2278	.hal_reo2_ring_base_lsb = 0x00000244,
   2279	.hal_reo1_aging_thresh_ix_0 = 0x00000564,
   2280	.hal_reo1_aging_thresh_ix_1 = 0x00000568,
   2281	.hal_reo1_aging_thresh_ix_2 = 0x0000056c,
   2282	.hal_reo1_aging_thresh_ix_3 = 0x00000570,
   2283
   2284	/* REO2SW(x) R2 ring pointers (head/tail) address */
   2285	.hal_reo1_ring_hp = 0x00003028,
   2286	.hal_reo1_ring_tp = 0x0000302c,
   2287	.hal_reo2_ring_hp = 0x00003030,
   2288
   2289	/* REO2TCL R0 ring configuration address */
   2290	.hal_reo_tcl_ring_base_lsb = 0x000003fc,
   2291	.hal_reo_tcl_ring_hp = 0x00003058,
   2292
   2293	/* REO CMD ring address */
   2294	.hal_reo_cmd_ring_base_lsb = 0x000000e4,
   2295	.hal_reo_cmd_ring_hp = 0x00003010,
   2296
   2297	/* REO status address */
   2298	.hal_reo_status_ring_base_lsb = 0x00000504,
   2299	.hal_reo_status_hp = 0x00003070,
   2300
   2301	/* SW2REO ring address */
   2302	.hal_sw2reo_ring_base_lsb = 0x0000013c,
   2303	.hal_sw2reo_ring_hp = 0x00003018,
   2304
   2305	/* WCSS relative address */
   2306	.hal_seq_wcss_umac_ce0_src_reg = 0x01b80000,
   2307	.hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000,
   2308	.hal_seq_wcss_umac_ce1_src_reg = 0x01b82000,
   2309	.hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000,
   2310
   2311	/* WBM Idle address */
   2312	.hal_wbm_idle_link_ring_base_lsb = 0x00000874,
   2313	.hal_wbm_idle_link_ring_misc = 0x00000884,
   2314
   2315	/* SW2WBM release address */
   2316	.hal_wbm_release_ring_base_lsb = 0x000001ec,
   2317
   2318	/* WBM2SW release address */
   2319	.hal_wbm0_release_ring_base_lsb = 0x00000924,
   2320	.hal_wbm1_release_ring_base_lsb = 0x0000097c,
   2321
   2322	/* PCIe base address */
   2323	.pcie_qserdes_sysclk_en_sel = 0x0,
   2324	.pcie_pcs_osc_dtct_config_base = 0x0,
   2325
   2326	/* Shadow register area */
   2327	.hal_shadow_base_addr = 0x00000504,
   2328
   2329	/* REO misc control register, used for fragment
   2330	 * destination ring config in WCN6750.
   2331	 */
   2332	.hal_reo1_misc_ctl = 0x000005d8,
   2333};
   2334
   2335const struct ath11k_hw_hal_params ath11k_hw_hal_params_ipq8074 = {
   2336	.rx_buf_rbm = HAL_RX_BUF_RBM_SW3_BM,
   2337};
   2338
   2339const struct ath11k_hw_hal_params ath11k_hw_hal_params_qca6390 = {
   2340	.rx_buf_rbm = HAL_RX_BUF_RBM_SW1_BM,
   2341};
   2342
   2343static const struct cfg80211_sar_freq_ranges ath11k_hw_sar_freq_ranges_wcn6855[] = {
   2344	{.start_freq = 2402, .end_freq = 2482 },  /* 2G ch1~ch13 */
   2345	{.start_freq = 5150, .end_freq = 5250 },  /* 5G UNII-1 ch32~ch48 */
   2346	{.start_freq = 5250, .end_freq = 5725 },  /* 5G UNII-2 ch50~ch144 */
   2347	{.start_freq = 5725, .end_freq = 5810 },  /* 5G UNII-3 ch149~ch161 */
   2348	{.start_freq = 5815, .end_freq = 5895 },  /* 5G UNII-4 ch163~ch177 */
   2349	{.start_freq = 5925, .end_freq = 6165 },  /* 6G UNII-5 Ch1, Ch2 ~ Ch41 */
   2350	{.start_freq = 6165, .end_freq = 6425 },  /* 6G UNII-5 ch45~ch93 */
   2351	{.start_freq = 6425, .end_freq = 6525 },  /* 6G UNII-6 ch97~ch113 */
   2352	{.start_freq = 6525, .end_freq = 6705 },  /* 6G UNII-7 ch117~ch149 */
   2353	{.start_freq = 6705, .end_freq = 6875 },  /* 6G UNII-7 ch153~ch185 */
   2354	{.start_freq = 6875, .end_freq = 7125 },  /* 6G UNII-8 ch189~ch233 */
   2355};
   2356
   2357const struct cfg80211_sar_capa ath11k_hw_sar_capa_wcn6855 = {
   2358	.type = NL80211_SAR_TYPE_POWER,
   2359	.num_freq_ranges = (ARRAY_SIZE(ath11k_hw_sar_freq_ranges_wcn6855)),
   2360	.freq_ranges = ath11k_hw_sar_freq_ranges_wcn6855,
   2361};