cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pcic.h (1803B)

      1/* SPDX-License-Identifier: BSD-3-Clause-Clear */
      2/*
      3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
      4 * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
      5 */
      6
      7#ifndef _ATH11K_PCI_CMN_H
      8#define _ATH11K_PCI_CMN_H
      9
     10#include "core.h"
     11
     12#define ATH11K_PCI_IRQ_CE0_OFFSET	3
     13#define ATH11K_PCI_IRQ_DP_OFFSET	14
     14
     15#define ATH11K_PCI_WINDOW_ENABLE_BIT		0x40000000
     16#define ATH11K_PCI_WINDOW_REG_ADDRESS		0x310c
     17#define ATH11K_PCI_WINDOW_VALUE_MASK		GENMASK(24, 19)
     18#define ATH11K_PCI_WINDOW_START			0x80000
     19#define ATH11K_PCI_WINDOW_RANGE_MASK		GENMASK(18, 0)
     20
     21/* BAR0 + 4k is always accessible, and no
     22 * need to force wakeup.
     23 * 4K - 32 = 0xFE0
     24 */
     25#define ATH11K_PCI_ACCESS_ALWAYS_OFF 0xFE0
     26
     27int ath11k_pcic_get_user_msi_assignment(struct ath11k_base *ab, char *user_name,
     28					int *num_vectors, u32 *user_base_data,
     29					u32 *base_vector);
     30void ath11k_pcic_write32(struct ath11k_base *ab, u32 offset, u32 value);
     31u32 ath11k_pcic_read32(struct ath11k_base *ab, u32 offset);
     32void ath11k_pcic_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo,
     33				 u32 *msi_addr_hi);
     34void ath11k_pcic_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id, u32 *msi_idx);
     35void ath11k_pcic_free_irq(struct ath11k_base *ab);
     36int ath11k_pcic_config_irq(struct ath11k_base *ab);
     37void ath11k_pcic_ext_irq_enable(struct ath11k_base *ab);
     38void ath11k_pcic_ext_irq_disable(struct ath11k_base *ab);
     39void ath11k_pcic_stop(struct ath11k_base *ab);
     40int ath11k_pcic_start(struct ath11k_base *ab);
     41int ath11k_pcic_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
     42				    u8 *ul_pipe, u8 *dl_pipe);
     43void ath11k_pcic_ce_irqs_enable(struct ath11k_base *ab);
     44void ath11k_pcic_ce_irq_disable_sync(struct ath11k_base *ab);
     45int ath11k_pcic_init_msi_config(struct ath11k_base *ab);
     46#endif