cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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eeprom.h (6350B)


      1/*
      2 * Shared Atheros AR9170 Header
      3 *
      4 * EEPROM layout
      5 *
      6 * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
      7 *
      8 * This program is free software; you can redistribute it and/or modify
      9 * it under the terms of the GNU General Public License as published by
     10 * the Free Software Foundation; either version 2 of the License, or
     11 * (at your option) any later version.
     12 *
     13 * This program is distributed in the hope that it will be useful,
     14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     16 * GNU General Public License for more details.
     17 *
     18 * You should have received a copy of the GNU General Public License
     19 * along with this program; see the file COPYING.  If not, see
     20 * http://www.gnu.org/licenses/.
     21 *
     22 * This file incorporates work covered by the following copyright and
     23 * permission notice:
     24 *    Copyright (c) 2007-2008 Atheros Communications, Inc.
     25 *
     26 *    Permission to use, copy, modify, and/or distribute this software for any
     27 *    purpose with or without fee is hereby granted, provided that the above
     28 *    copyright notice and this permission notice appear in all copies.
     29 *
     30 *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
     31 *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
     32 *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
     33 *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
     34 *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
     35 *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
     36 *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
     37 */
     38#ifndef __CARL9170_SHARED_EEPROM_H
     39#define __CARL9170_SHARED_EEPROM_H
     40
     41#define AR9170_EEPROM_START		0x1600
     42
     43#define AR5416_MAX_CHAINS		2
     44#define AR5416_MODAL_SPURS		5
     45
     46struct ar9170_eeprom_modal {
     47	__le32	antCtrlChain[AR5416_MAX_CHAINS];
     48	__le32	antCtrlCommon;
     49	s8	antennaGainCh[AR5416_MAX_CHAINS];
     50	u8	switchSettling;
     51	u8	txRxAttenCh[AR5416_MAX_CHAINS];
     52	u8	rxTxMarginCh[AR5416_MAX_CHAINS];
     53	s8	adcDesiredSize;
     54	s8	pgaDesiredSize;
     55	u8	xlnaGainCh[AR5416_MAX_CHAINS];
     56	u8	txEndToXpaOff;
     57	u8	txEndToRxOn;
     58	u8	txFrameToXpaOn;
     59	u8	thresh62;
     60	s8	noiseFloorThreshCh[AR5416_MAX_CHAINS];
     61	u8	xpdGain;
     62	u8	xpd;
     63	s8	iqCalICh[AR5416_MAX_CHAINS];
     64	s8	iqCalQCh[AR5416_MAX_CHAINS];
     65	u8	pdGainOverlap;
     66	u8	ob;
     67	u8	db;
     68	u8	xpaBiasLvl;
     69	u8	pwrDecreaseFor2Chain;
     70	u8	pwrDecreaseFor3Chain;
     71	u8	txFrameToDataStart;
     72	u8	txFrameToPaOn;
     73	u8	ht40PowerIncForPdadc;
     74	u8	bswAtten[AR5416_MAX_CHAINS];
     75	u8	bswMargin[AR5416_MAX_CHAINS];
     76	u8	swSettleHt40;
     77	u8	reserved[22];
     78	struct spur_channel {
     79		__le16 spurChan;
     80		u8	spurRangeLow;
     81		u8	spurRangeHigh;
     82	} __packed spur_channels[AR5416_MODAL_SPURS];
     83} __packed;
     84
     85#define AR5416_NUM_PD_GAINS		4
     86#define AR5416_PD_GAIN_ICEPTS		5
     87
     88struct ar9170_calibration_data_per_freq {
     89	u8	pwr_pdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
     90	u8	vpd_pdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
     91} __packed;
     92
     93#define AR5416_NUM_5G_CAL_PIERS		8
     94#define AR5416_NUM_2G_CAL_PIERS		4
     95
     96#define AR5416_NUM_5G_TARGET_PWRS	8
     97#define AR5416_NUM_2G_CCK_TARGET_PWRS	3
     98#define AR5416_NUM_2G_OFDM_TARGET_PWRS	4
     99#define AR5416_MAX_NUM_TGT_PWRS		8
    100
    101struct ar9170_calibration_target_power_legacy {
    102	u8	freq;
    103	u8	power[4];
    104} __packed;
    105
    106struct ar9170_calibration_target_power_ht {
    107	u8	freq;
    108	u8	power[8];
    109} __packed;
    110
    111#define AR5416_NUM_CTLS			24
    112
    113struct ar9170_calctl_edges {
    114	u8	channel;
    115#define AR9170_CALCTL_EDGE_FLAGS	0xC0
    116	u8	power_flags;
    117} __packed;
    118
    119#define AR5416_NUM_BAND_EDGES		8
    120
    121struct ar9170_calctl_data {
    122	struct ar9170_calctl_edges
    123		control_edges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
    124} __packed;
    125
    126struct ar9170_eeprom {
    127	__le16	length;
    128	__le16	checksum;
    129	__le16	version;
    130	u8	operating_flags;
    131#define AR9170_OPFLAG_5GHZ		1
    132#define AR9170_OPFLAG_2GHZ		2
    133	u8	misc;
    134	__le16	reg_domain[2];
    135	u8	mac_address[6];
    136	u8	rx_mask;
    137	u8	tx_mask;
    138	__le16	rf_silent;
    139	__le16	bluetooth_options;
    140	__le16	device_capabilities;
    141	__le32	build_number;
    142	u8	deviceType;
    143	u8	reserved[33];
    144
    145	u8	customer_data[64];
    146
    147	struct ar9170_eeprom_modal
    148		modal_header[2];
    149
    150	u8	cal_freq_pier_5G[AR5416_NUM_5G_CAL_PIERS];
    151	u8	cal_freq_pier_2G[AR5416_NUM_2G_CAL_PIERS];
    152
    153	struct ar9170_calibration_data_per_freq
    154		cal_pier_data_5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS],
    155		cal_pier_data_2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
    156
    157	/* power calibration data */
    158	struct ar9170_calibration_target_power_legacy
    159		cal_tgt_pwr_5G[AR5416_NUM_5G_TARGET_PWRS];
    160	struct ar9170_calibration_target_power_ht
    161		cal_tgt_pwr_5G_ht20[AR5416_NUM_5G_TARGET_PWRS],
    162		cal_tgt_pwr_5G_ht40[AR5416_NUM_5G_TARGET_PWRS];
    163
    164	struct ar9170_calibration_target_power_legacy
    165		cal_tgt_pwr_2G_cck[AR5416_NUM_2G_CCK_TARGET_PWRS],
    166		cal_tgt_pwr_2G_ofdm[AR5416_NUM_2G_OFDM_TARGET_PWRS];
    167	struct ar9170_calibration_target_power_ht
    168		cal_tgt_pwr_2G_ht20[AR5416_NUM_2G_OFDM_TARGET_PWRS],
    169		cal_tgt_pwr_2G_ht40[AR5416_NUM_2G_OFDM_TARGET_PWRS];
    170
    171	/* conformance testing limits */
    172	u8	ctl_index[AR5416_NUM_CTLS];
    173	struct ar9170_calctl_data
    174		ctl_data[AR5416_NUM_CTLS];
    175
    176	u8	pad;
    177	__le16	subsystem_id;
    178} __packed;
    179
    180#define AR9170_LED_MODE_POWER_ON		0x0001
    181#define AR9170_LED_MODE_RESERVED		0x0002
    182#define AR9170_LED_MODE_DISABLE_STATE		0x0004
    183#define AR9170_LED_MODE_OFF_IN_PSM		0x0008
    184
    185/* AR9170_LED_MODE BIT is set */
    186#define AR9170_LED_MODE_FREQUENCY_S		4
    187#define AR9170_LED_MODE_FREQUENCY		0x0030
    188#define AR9170_LED_MODE_FREQUENCY_1HZ		0x0000
    189#define AR9170_LED_MODE_FREQUENCY_0_5HZ		0x0010
    190#define AR9170_LED_MODE_FREQUENCY_0_25HZ	0x0020
    191#define AR9170_LED_MODE_FREQUENCY_0_125HZ	0x0030
    192
    193/* AR9170_LED_MODE BIT is not set */
    194#define AR9170_LED_MODE_CONN_STATE_S		4
    195#define AR9170_LED_MODE_CONN_STATE		0x0030
    196#define AR9170_LED_MODE_CONN_STATE_FORCE_OFF	0x0000
    197#define AR9170_LED_MODE_CONN_STATE_FORCE_ON	0x0010
    198/* Idle off / Active on */
    199#define AR9170_LED_MODE_CONN_STATE_IOFF_AON	0x0020
    200/* Idle on / Active off */
    201#define AR9170_LED_MODE_CONN_STATE_ION_AOFF	0x0010
    202
    203#define AR9170_LED_MODE_MODE			0x0040
    204#define AR9170_LED_MODE_RESERVED2		0x0080
    205
    206#define AR9170_LED_MODE_TON_SCAN_S		8
    207#define AR9170_LED_MODE_TON_SCAN		0x0f00
    208
    209#define AR9170_LED_MODE_TOFF_SCAN_S		12
    210#define AR9170_LED_MODE_TOFF_SCAN		0xf000
    211
    212struct ar9170_led_mode {
    213	__le16 led;
    214};
    215
    216#endif /* __CARL9170_SHARED_EEPROM_H */