dxe.h (18139B)
1/* 2 * Copyright (c) 2013 Eugene Krasnikov <k.eugene.e@gmail.com> 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#ifndef _DXE_H_ 18#define _DXE_H_ 19 20#include "wcn36xx.h" 21 22/* 23TX_LOW = DMA0 24TX_HIGH = DMA4 25RX_LOW = DMA1 26RX_HIGH = DMA3 27H2H_TEST_RX_TX = DMA2 28*/ 29 30/* DXE registers */ 31#define WCN36XX_DXE_MEM_REG 0 32 33#define WCN36XX_CCU_DXE_INT_SELECT_RIVA 0x310 34#define WCN36XX_CCU_DXE_INT_SELECT_PRONTO 0x10dc 35 36/* Descriptor valid */ 37#define WCN36xx_DXE_CTRL_VLD BIT(0) 38/* End of packet */ 39#define WCN36xx_DXE_CTRL_EOP BIT(3) 40/* BD handling bit */ 41#define WCN36xx_DXE_CTRL_BDH BIT(4) 42/* Source is a queue */ 43#define WCN36xx_DXE_CTRL_SIQ BIT(5) 44/* Destination is a queue */ 45#define WCN36xx_DXE_CTRL_DIQ BIT(6) 46/* Pointer address is a queue */ 47#define WCN36xx_DXE_CTRL_PIQ BIT(7) 48/* Release PDU when done */ 49#define WCN36xx_DXE_CTRL_PDU_REL BIT(8) 50/* STOP channel processing */ 51#define WCN36xx_DXE_CTRL_STOP BIT(16) 52/* INT on descriptor done */ 53#define WCN36xx_DXE_CTRL_INT BIT(17) 54/* Endian byte swap enable */ 55#define WCN36xx_DXE_CTRL_SWAP BIT(20) 56/* Master endianness */ 57#define WCN36xx_DXE_CTRL_ENDIANNESS BIT(21) 58 59/* Transfer type */ 60#define WCN36xx_DXE_CTRL_XTYPE_SHIFT 1 61#define WCN36xx_DXE_CTRL_XTYPE_MASK GENMASK(2, WCN36xx_DXE_CTRL_XTYPE_SHIFT) 62#define WCN36xx_DXE_CTRL_XTYPE_SET(x) ((x) << WCN36xx_DXE_CTRL_XTYPE_SHIFT) 63 64/* BMU Threshold select */ 65#define WCN36xx_DXE_CTRL_BTHLD_SEL_SHIFT 9 66#define WCN36xx_DXE_CTRL_BTHLD_SEL_MASK GENMASK(12, WCN36xx_DXE_CTRL_BTHLD_SEL_SHIFT) 67#define WCN36xx_DXE_CTRL_BTHLD_SEL_SET(x) ((x) << WCN36xx_DXE_CTRL_BTHLD_SEL_SHIFT) 68 69/* Priority */ 70#define WCN36xx_DXE_CTRL_PRIO_SHIFT 13 71#define WCN36xx_DXE_CTRL_PRIO_MASK GENMASK(15, WCN36xx_DXE_CTRL_PRIO_SHIFT) 72#define WCN36xx_DXE_CTRL_PRIO_SET(x) ((x) << WCN36xx_DXE_CTRL_PRIO_SHIFT) 73 74/* BD Template index */ 75#define WCN36xx_DXE_CTRL_BDT_IDX_SHIFT 18 76#define WCN36xx_DXE_CTRL_BDT_IDX_MASK GENMASK(19, WCN36xx_DXE_CTRL_BDT_IDX_SHIFT) 77#define WCN36xx_DXE_CTRL_BDT_IDX_SET(x) ((x) << WCN36xx_DXE_CTRL_BDT_IDX_SHIFT) 78 79/* Transfer types: */ 80/* Host to host */ 81#define WCN36xx_DXE_XTYPE_H2H (0) 82/* Host to BMU */ 83#define WCN36xx_DXE_XTYPE_H2B (2) 84/* BMU to host */ 85#define WCN36xx_DXE_XTYPE_B2H (3) 86 87#define WCN36XX_DXE_CTRL_TX_L (WCN36xx_DXE_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_H2B) | \ 88 WCN36xx_DXE_CTRL_DIQ | WCN36xx_DXE_CTRL_BTHLD_SEL_SET(5) | \ 89 WCN36xx_DXE_CTRL_PRIO_SET(4) | WCN36xx_DXE_CTRL_INT | \ 90 WCN36xx_DXE_CTRL_SWAP | WCN36xx_DXE_CTRL_ENDIANNESS) 91 92#define WCN36XX_DXE_CTRL_TX_H (WCN36xx_DXE_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_H2B) | \ 93 WCN36xx_DXE_CTRL_DIQ | WCN36xx_DXE_CTRL_BTHLD_SEL_SET(7) | \ 94 WCN36xx_DXE_CTRL_PRIO_SET(6) | WCN36xx_DXE_CTRL_INT | \ 95 WCN36xx_DXE_CTRL_SWAP | WCN36xx_DXE_CTRL_ENDIANNESS) 96 97#define WCN36XX_DXE_CTRL_RX_L (WCN36xx_DXE_CTRL_VLD | \ 98 WCN36xx_DXE_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_B2H) | \ 99 WCN36xx_DXE_CTRL_EOP | WCN36xx_DXE_CTRL_SIQ | \ 100 WCN36xx_DXE_CTRL_PDU_REL | WCN36xx_DXE_CTRL_BTHLD_SEL_SET(6) | \ 101 WCN36xx_DXE_CTRL_PRIO_SET(5) | WCN36xx_DXE_CTRL_INT | \ 102 WCN36xx_DXE_CTRL_SWAP) 103 104#define WCN36XX_DXE_CTRL_RX_H (WCN36xx_DXE_CTRL_VLD | \ 105 WCN36xx_DXE_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_B2H) | \ 106 WCN36xx_DXE_CTRL_EOP | WCN36xx_DXE_CTRL_SIQ | \ 107 WCN36xx_DXE_CTRL_PDU_REL | WCN36xx_DXE_CTRL_BTHLD_SEL_SET(8) | \ 108 WCN36xx_DXE_CTRL_PRIO_SET(6) | WCN36xx_DXE_CTRL_INT | \ 109 WCN36xx_DXE_CTRL_SWAP) 110 111#define WCN36XX_DXE_CTRL_TX_H_BD (WCN36xx_DXE_CTRL_VLD | \ 112 WCN36xx_DXE_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_H2B) | \ 113 WCN36xx_DXE_CTRL_DIQ | WCN36xx_DXE_CTRL_BTHLD_SEL_SET(7) | \ 114 WCN36xx_DXE_CTRL_PRIO_SET(6) | WCN36xx_DXE_CTRL_SWAP | \ 115 WCN36xx_DXE_CTRL_ENDIANNESS) 116 117#define WCN36XX_DXE_CTRL_TX_H_SKB (WCN36xx_DXE_CTRL_VLD | \ 118 WCN36xx_DXE_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_H2B) | \ 119 WCN36xx_DXE_CTRL_EOP | WCN36xx_DXE_CTRL_DIQ | \ 120 WCN36xx_DXE_CTRL_BTHLD_SEL_SET(7) | WCN36xx_DXE_CTRL_PRIO_SET(6) | \ 121 WCN36xx_DXE_CTRL_INT | WCN36xx_DXE_CTRL_SWAP | \ 122 WCN36xx_DXE_CTRL_ENDIANNESS) 123 124#define WCN36XX_DXE_CTRL_TX_L_BD (WCN36xx_DXE_CTRL_VLD | \ 125 WCN36xx_DXE_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_H2B) | \ 126 WCN36xx_DXE_CTRL_DIQ | WCN36xx_DXE_CTRL_BTHLD_SEL_SET(5) | \ 127 WCN36xx_DXE_CTRL_PRIO_SET(4) | WCN36xx_DXE_CTRL_SWAP | \ 128 WCN36xx_DXE_CTRL_ENDIANNESS) 129 130#define WCN36XX_DXE_CTRL_TX_L_SKB (WCN36xx_DXE_CTRL_VLD | \ 131 WCN36xx_DXE_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_H2B) | \ 132 WCN36xx_DXE_CTRL_EOP | WCN36xx_DXE_CTRL_DIQ | \ 133 WCN36xx_DXE_CTRL_BTHLD_SEL_SET(5) | WCN36xx_DXE_CTRL_PRIO_SET(4) | \ 134 WCN36xx_DXE_CTRL_INT | WCN36xx_DXE_CTRL_SWAP | \ 135 WCN36xx_DXE_CTRL_ENDIANNESS) 136 137/* TODO This must calculated properly but not hardcoded */ 138#define WCN36XX_DXE_WQ_TX_L 0x17 139#define WCN36XX_DXE_WQ_TX_H 0x17 140#define WCN36XX_DXE_WQ_RX_L 0xB 141#define WCN36XX_DXE_WQ_RX_H 0x4 142 143/* Channel enable or restart */ 144#define WCN36xx_DXE_CH_CTRL_EN BIT(0) 145/* End of packet bit */ 146#define WCN36xx_DXE_CH_CTRL_EOP BIT(3) 147/* BD Handling bit */ 148#define WCN36xx_DXE_CH_CTRL_BDH BIT(4) 149/* Source is queue */ 150#define WCN36xx_DXE_CH_CTRL_SIQ BIT(5) 151/* Destination is queue */ 152#define WCN36xx_DXE_CH_CTRL_DIQ BIT(6) 153/* Pointer descriptor is queue */ 154#define WCN36xx_DXE_CH_CTRL_PIQ BIT(7) 155/* Relase PDU when done */ 156#define WCN36xx_DXE_CH_CTRL_PDU_REL BIT(8) 157/* Stop channel processing */ 158#define WCN36xx_DXE_CH_CTRL_STOP BIT(16) 159/* Enable external descriptor interrupt */ 160#define WCN36xx_DXE_CH_CTRL_INE_ED BIT(17) 161/* Enable channel interrupt on errors */ 162#define WCN36xx_DXE_CH_CTRL_INE_ERR BIT(18) 163/* Enable Channel interrupt when done */ 164#define WCN36xx_DXE_CH_CTRL_INE_DONE BIT(19) 165/* External descriptor enable */ 166#define WCN36xx_DXE_CH_CTRL_EDEN BIT(20) 167/* Wait for valid bit */ 168#define WCN36xx_DXE_CH_CTRL_EDVEN BIT(21) 169/* Endianness is little endian*/ 170#define WCN36xx_DXE_CH_CTRL_ENDIANNESS BIT(26) 171/* Abort transfer */ 172#define WCN36xx_DXE_CH_CTRL_ABORT BIT(27) 173/* Long descriptor format */ 174#define WCN36xx_DXE_CH_CTRL_DFMT BIT(28) 175/* Endian byte swap enable */ 176#define WCN36xx_DXE_CH_CTRL_SWAP BIT(31) 177 178/* Transfer type */ 179#define WCN36xx_DXE_CH_CTRL_XTYPE_SHIFT 1 180#define WCN36xx_DXE_CH_CTRL_XTYPE_MASK GENMASK(2, WCN36xx_DXE_CH_CTRL_XTYPE_SHIFT) 181#define WCN36xx_DXE_CH_CTRL_XTYPE_SET(x) ((x) << WCN36xx_DXE_CH_CTRL_XTYPE_SHIFT) 182 183/* Channel BMU Threshold select */ 184#define WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SHIFT 9 185#define WCN36xx_DXE_CH_CTRL_BTHLD_SEL_MASK GENMASK(12, WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SHIFT) 186#define WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SET(x) ((x) << WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SHIFT) 187 188/* Channel Priority */ 189#define WCN36xx_DXE_CH_CTRL_PRIO_SHIFT 13 190#define WCN36xx_DXE_CH_CTRL_PRIO_MASK GENMASK(15, WCN36xx_DXE_CH_CTRL_PRIO_SHIFT) 191#define WCN36xx_DXE_CH_CTRL_PRIO_SET(x) ((x) << WCN36xx_DXE_CH_CTRL_PRIO_SHIFT) 192 193/* Counter select */ 194#define WCN36xx_DXE_CH_CTRL_SEL_SHIFT 22 195#define WCN36xx_DXE_CH_CTRL_SEL_MASK GENMASK(25, WCN36xx_DXE_CH_CTRL_SEL_SHIFT) 196#define WCN36xx_DXE_CH_CTRL_SEL_SET(x) ((x) << WCN36xx_DXE_CH_CTRL_SEL_SHIFT) 197 198/* Channel BD template index */ 199#define WCN36xx_DXE_CH_CTRL_BDT_IDX_SHIFT 29 200#define WCN36xx_DXE_CH_CTRL_BDT_IDX_MASK GENMASK(30, WCN36xx_DXE_CH_CTRL_BDT_IDX_SHIFT) 201#define WCN36xx_DXE_CH_CTRL_BDT_IDX_SET(x) ((x) << WCN36xx_DXE_CH_CTRL_BDT_IDX_SHIFT) 202 203/* DXE default control register values */ 204#define WCN36XX_DXE_CH_DEFAULT_CTL_RX_L (WCN36xx_DXE_CH_CTRL_EN | \ 205 WCN36xx_DXE_CH_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_B2H) | \ 206 WCN36xx_DXE_CH_CTRL_EOP | WCN36xx_DXE_CH_CTRL_SIQ | \ 207 WCN36xx_DXE_CH_CTRL_PDU_REL | WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SET(6) | \ 208 WCN36xx_DXE_CH_CTRL_PRIO_SET(5) | WCN36xx_DXE_CH_CTRL_INE_ED | \ 209 WCN36xx_DXE_CH_CTRL_INE_ERR | WCN36xx_DXE_CH_CTRL_INE_DONE | \ 210 WCN36xx_DXE_CH_CTRL_EDEN | WCN36xx_DXE_CH_CTRL_EDVEN | \ 211 WCN36xx_DXE_CH_CTRL_SEL_SET(1) | WCN36xx_DXE_CH_CTRL_ENDIANNESS | \ 212 WCN36xx_DXE_CH_CTRL_SWAP) 213 214#define WCN36XX_DXE_CH_DEFAULT_CTL_RX_H (WCN36xx_DXE_CH_CTRL_EN | \ 215 WCN36xx_DXE_CH_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_B2H) | \ 216 WCN36xx_DXE_CH_CTRL_EOP | WCN36xx_DXE_CH_CTRL_SIQ | \ 217 WCN36xx_DXE_CH_CTRL_PDU_REL | WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SET(8) | \ 218 WCN36xx_DXE_CH_CTRL_PRIO_SET(6) | WCN36xx_DXE_CH_CTRL_INE_ED | \ 219 WCN36xx_DXE_CH_CTRL_INE_ERR | WCN36xx_DXE_CH_CTRL_INE_DONE | \ 220 WCN36xx_DXE_CH_CTRL_EDEN | WCN36xx_DXE_CH_CTRL_EDVEN | \ 221 WCN36xx_DXE_CH_CTRL_SEL_SET(3) | WCN36xx_DXE_CH_CTRL_ENDIANNESS | \ 222 WCN36xx_DXE_CH_CTRL_SWAP) 223 224#define WCN36XX_DXE_CH_DEFAULT_CTL_TX_H (WCN36xx_DXE_CH_CTRL_EN | \ 225 WCN36xx_DXE_CH_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_H2B) | \ 226 WCN36xx_DXE_CH_CTRL_EOP | WCN36xx_DXE_CH_CTRL_DIQ | \ 227 WCN36xx_DXE_CH_CTRL_PDU_REL | WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SET(7) | \ 228 WCN36xx_DXE_CH_CTRL_PRIO_SET(6) | WCN36xx_DXE_CH_CTRL_INE_ED | \ 229 WCN36xx_DXE_CH_CTRL_INE_ERR | WCN36xx_DXE_CH_CTRL_INE_DONE | \ 230 WCN36xx_DXE_CH_CTRL_EDEN | WCN36xx_DXE_CH_CTRL_EDVEN | \ 231 WCN36xx_DXE_CH_CTRL_SEL_SET(4) | WCN36xx_DXE_CH_CTRL_ENDIANNESS | \ 232 WCN36xx_DXE_CH_CTRL_SWAP) 233 234#define WCN36XX_DXE_CH_DEFAULT_CTL_TX_L (WCN36xx_DXE_CH_CTRL_EN | \ 235 WCN36xx_DXE_CH_CTRL_XTYPE_SET(WCN36xx_DXE_XTYPE_H2B) | \ 236 WCN36xx_DXE_CH_CTRL_EOP | WCN36xx_DXE_CH_CTRL_DIQ | \ 237 WCN36xx_DXE_CH_CTRL_PDU_REL | WCN36xx_DXE_CH_CTRL_BTHLD_SEL_SET(5) | \ 238 WCN36xx_DXE_CH_CTRL_PRIO_SET(4) | WCN36xx_DXE_CH_CTRL_INE_ED | \ 239 WCN36xx_DXE_CH_CTRL_INE_ERR | WCN36xx_DXE_CH_CTRL_INE_DONE | \ 240 WCN36xx_DXE_CH_CTRL_EDEN | WCN36xx_DXE_CH_CTRL_EDVEN | \ 241 WCN36xx_DXE_CH_CTRL_SEL_SET(0) | WCN36xx_DXE_CH_CTRL_ENDIANNESS | \ 242 WCN36xx_DXE_CH_CTRL_SWAP) 243 244/* Common DXE registers */ 245#define WCN36XX_DXE_MEM_CSR (WCN36XX_DXE_MEM_REG + 0x00) 246#define WCN36XX_DXE_REG_CSR_RESET (WCN36XX_DXE_MEM_REG + 0x00) 247#define WCN36XX_DXE_ENCH_ADDR (WCN36XX_DXE_MEM_REG + 0x04) 248#define WCN36XX_DXE_REG_CH_EN (WCN36XX_DXE_MEM_REG + 0x08) 249#define WCN36XX_DXE_REG_CH_DONE (WCN36XX_DXE_MEM_REG + 0x0C) 250#define WCN36XX_DXE_REG_CH_ERR (WCN36XX_DXE_MEM_REG + 0x10) 251#define WCN36XX_DXE_INT_MASK_REG (WCN36XX_DXE_MEM_REG + 0x18) 252#define WCN36XX_DXE_INT_SRC_RAW_REG (WCN36XX_DXE_MEM_REG + 0x20) 253 /* #define WCN36XX_DXE_INT_CH6_MASK 0x00000040 */ 254 /* #define WCN36XX_DXE_INT_CH5_MASK 0x00000020 */ 255 #define WCN36XX_DXE_INT_CH4_MASK 0x00000010 256 #define WCN36XX_DXE_INT_CH3_MASK 0x00000008 257 /* #define WCN36XX_DXE_INT_CH2_MASK 0x00000004 */ 258 #define WCN36XX_DXE_INT_CH1_MASK 0x00000002 259 #define WCN36XX_DXE_INT_CH0_MASK 0x00000001 260#define WCN36XX_DXE_0_INT_CLR (WCN36XX_DXE_MEM_REG + 0x30) 261#define WCN36XX_DXE_0_INT_ED_CLR (WCN36XX_DXE_MEM_REG + 0x34) 262#define WCN36XX_DXE_0_INT_DONE_CLR (WCN36XX_DXE_MEM_REG + 0x38) 263#define WCN36XX_DXE_0_INT_ERR_CLR (WCN36XX_DXE_MEM_REG + 0x3C) 264 265#define WCN36XX_CH_STAT_INT_DONE_MASK 0x00008000 266#define WCN36XX_CH_STAT_INT_ERR_MASK 0x00004000 267#define WCN36XX_CH_STAT_INT_ED_MASK 0x00002000 268 269#define WCN36XX_DXE_0_CH0_STATUS (WCN36XX_DXE_MEM_REG + 0x404) 270#define WCN36XX_DXE_0_CH1_STATUS (WCN36XX_DXE_MEM_REG + 0x444) 271#define WCN36XX_DXE_0_CH2_STATUS (WCN36XX_DXE_MEM_REG + 0x484) 272#define WCN36XX_DXE_0_CH3_STATUS (WCN36XX_DXE_MEM_REG + 0x4C4) 273#define WCN36XX_DXE_0_CH4_STATUS (WCN36XX_DXE_MEM_REG + 0x504) 274 275#define WCN36XX_DXE_REG_RESET 0x5c89 276 277/* Temporary BMU Workqueue 4 */ 278#define WCN36XX_DXE_BMU_WQ_RX_LOW 0xB 279#define WCN36XX_DXE_BMU_WQ_RX_HIGH 0x4 280/* DMA channel offset */ 281#define WCN36XX_DXE_TX_LOW_OFFSET 0x400 282#define WCN36XX_DXE_TX_HIGH_OFFSET 0x500 283#define WCN36XX_DXE_RX_LOW_OFFSET 0x440 284#define WCN36XX_DXE_RX_HIGH_OFFSET 0x4C0 285 286/* Address of the next DXE descriptor */ 287#define WCN36XX_DXE_CH_NEXT_DESC_ADDR 0x001C 288#define WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_L (WCN36XX_DXE_MEM_REG + \ 289 WCN36XX_DXE_TX_LOW_OFFSET + \ 290 WCN36XX_DXE_CH_NEXT_DESC_ADDR) 291#define WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_H (WCN36XX_DXE_MEM_REG + \ 292 WCN36XX_DXE_TX_HIGH_OFFSET + \ 293 WCN36XX_DXE_CH_NEXT_DESC_ADDR) 294#define WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_L (WCN36XX_DXE_MEM_REG + \ 295 WCN36XX_DXE_RX_LOW_OFFSET + \ 296 WCN36XX_DXE_CH_NEXT_DESC_ADDR) 297#define WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_H (WCN36XX_DXE_MEM_REG + \ 298 WCN36XX_DXE_RX_HIGH_OFFSET + \ 299 WCN36XX_DXE_CH_NEXT_DESC_ADDR) 300 301/* DXE Descriptor source address */ 302#define WCN36XX_DXE_CH_SRC_ADDR 0x000C 303#define WCN36XX_DXE_CH_SRC_ADDR_RX_L (WCN36XX_DXE_MEM_REG + \ 304 WCN36XX_DXE_RX_LOW_OFFSET + \ 305 WCN36XX_DXE_CH_SRC_ADDR) 306#define WCN36XX_DXE_CH_SRC_ADDR_RX_H (WCN36XX_DXE_MEM_REG + \ 307 WCN36XX_DXE_RX_HIGH_OFFSET + \ 308 WCN36XX_DXE_CH_SRC_ADDR) 309 310/* DXE Descriptor address destination address */ 311#define WCN36XX_DXE_CH_DEST_ADDR 0x0014 312#define WCN36XX_DXE_CH_DEST_ADDR_TX_L (WCN36XX_DXE_MEM_REG + \ 313 WCN36XX_DXE_TX_LOW_OFFSET + \ 314 WCN36XX_DXE_CH_DEST_ADDR) 315#define WCN36XX_DXE_CH_DEST_ADDR_TX_H (WCN36XX_DXE_MEM_REG + \ 316 WCN36XX_DXE_TX_HIGH_OFFSET + \ 317 WCN36XX_DXE_CH_DEST_ADDR) 318#define WCN36XX_DXE_CH_DEST_ADDR_RX_L (WCN36XX_DXE_MEM_REG + \ 319 WCN36XX_DXE_RX_LOW_OFFSET + \ 320 WCN36XX_DXE_CH_DEST_ADDR) 321#define WCN36XX_DXE_CH_DEST_ADDR_RX_H (WCN36XX_DXE_MEM_REG + \ 322 WCN36XX_DXE_RX_HIGH_OFFSET + \ 323 WCN36XX_DXE_CH_DEST_ADDR) 324 325/* Interrupt status */ 326#define WCN36XX_DXE_CH_STATUS_REG_ADDR 0x0004 327#define WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_L (WCN36XX_DXE_MEM_REG + \ 328 WCN36XX_DXE_TX_LOW_OFFSET + \ 329 WCN36XX_DXE_CH_STATUS_REG_ADDR) 330#define WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_H (WCN36XX_DXE_MEM_REG + \ 331 WCN36XX_DXE_TX_HIGH_OFFSET + \ 332 WCN36XX_DXE_CH_STATUS_REG_ADDR) 333#define WCN36XX_DXE_CH_STATUS_REG_ADDR_RX_L (WCN36XX_DXE_MEM_REG + \ 334 WCN36XX_DXE_RX_LOW_OFFSET + \ 335 WCN36XX_DXE_CH_STATUS_REG_ADDR) 336#define WCN36XX_DXE_CH_STATUS_REG_ADDR_RX_H (WCN36XX_DXE_MEM_REG + \ 337 WCN36XX_DXE_RX_HIGH_OFFSET + \ 338 WCN36XX_DXE_CH_STATUS_REG_ADDR) 339 340 341/* DXE default control register */ 342#define WCN36XX_DXE_REG_CTL_RX_L (WCN36XX_DXE_MEM_REG + \ 343 WCN36XX_DXE_RX_LOW_OFFSET) 344#define WCN36XX_DXE_REG_CTL_RX_H (WCN36XX_DXE_MEM_REG + \ 345 WCN36XX_DXE_RX_HIGH_OFFSET) 346#define WCN36XX_DXE_REG_CTL_TX_H (WCN36XX_DXE_MEM_REG + \ 347 WCN36XX_DXE_TX_HIGH_OFFSET) 348#define WCN36XX_DXE_REG_CTL_TX_L (WCN36XX_DXE_MEM_REG + \ 349 WCN36XX_DXE_TX_LOW_OFFSET) 350 351#define WCN36XX_SMSM_WLAN_TX_ENABLE 0x00000400 352#define WCN36XX_SMSM_WLAN_TX_RINGS_EMPTY 0x00000200 353 354 355/* Interrupt control channel mask */ 356#define WCN36XX_INT_MASK_CHAN_TX_L 0x00000001 357#define WCN36XX_INT_MASK_CHAN_RX_L 0x00000002 358#define WCN36XX_INT_MASK_CHAN_RX_H 0x00000008 359#define WCN36XX_INT_MASK_CHAN_TX_H 0x00000010 360 361#define WCN36XX_BD_CHUNK_SIZE 128 362 363#define WCN36XX_PKT_SIZE 0xF20 364enum wcn36xx_dxe_ch_type { 365 WCN36XX_DXE_CH_TX_L, 366 WCN36XX_DXE_CH_TX_H, 367 WCN36XX_DXE_CH_RX_L, 368 WCN36XX_DXE_CH_RX_H 369}; 370 371/* amount of descriptors per channel */ 372enum wcn36xx_dxe_ch_desc_num { 373 WCN36XX_DXE_CH_DESC_NUMB_TX_L = 128, 374 WCN36XX_DXE_CH_DESC_NUMB_TX_H = 10, 375 WCN36XX_DXE_CH_DESC_NUMB_RX_L = 512, 376 WCN36XX_DXE_CH_DESC_NUMB_RX_H = 40 377}; 378 379/** 380 * struct wcn36xx_dxe_desc - describes descriptor of one DXE buffer 381 * 382 * @ctrl: is a union that consists of following bits: 383 * union { 384 * u32 valid :1; //0 = DMA stop, 1 = DMA continue with this 385 * //descriptor 386 * u32 transfer_type :2; //0 = Host to Host space 387 * u32 eop :1; //End of Packet 388 * u32 bd_handling :1; //if transferType = Host to BMU, then 0 389 * // means first 128 bytes contain BD, and 1 390 * // means create new empty BD 391 * u32 siq :1; // SIQ 392 * u32 diq :1; // DIQ 393 * u32 pdu_rel :1; //0 = don't release BD and PDUs when done, 394 * // 1 = release them 395 * u32 bthld_sel :4; //BMU Threshold Select 396 * u32 prio :3; //Specifies the priority level to use for 397 * // the transfer 398 * u32 stop_channel :1; //1 = DMA stops processing further, channel 399 * //requires re-enabling after this 400 * u32 intr :1; //Interrupt on Descriptor Done 401 * u32 rsvd :1; //reserved 402 * u32 size :14;//14 bits used - ignored for BMU transfers, 403 * //only used for host to host transfers? 404 * } ctrl; 405 */ 406struct wcn36xx_dxe_desc { 407 u32 ctrl; 408 u32 fr_len; 409 410 u32 src_addr_l; 411 u32 dst_addr_l; 412 u32 phy_next_l; 413 u32 src_addr_h; 414 u32 dst_addr_h; 415 u32 phy_next_h; 416} __packed; 417 418/* DXE Control block */ 419struct wcn36xx_dxe_ctl { 420 struct wcn36xx_dxe_ctl *next; 421 struct wcn36xx_dxe_desc *desc; 422 unsigned int desc_phy_addr; 423 int ctl_blk_order; 424 struct sk_buff *skb; 425 void *bd_cpu_addr; 426 dma_addr_t bd_phy_addr; 427}; 428 429struct wcn36xx_dxe_ch { 430 spinlock_t lock; /* protects head/tail ptrs */ 431 enum wcn36xx_dxe_ch_type ch_type; 432 void *cpu_addr; 433 dma_addr_t dma_addr; 434 enum wcn36xx_dxe_ch_desc_num desc_num; 435 /* DXE control block ring */ 436 struct wcn36xx_dxe_ctl *head_blk_ctl; 437 struct wcn36xx_dxe_ctl *tail_blk_ctl; 438 439 /* DXE channel specific configs */ 440 u32 dxe_wq; 441 u32 ctrl_bd; 442 u32 ctrl_skb; 443 u32 reg_ctrl; 444 u32 def_ctrl; 445}; 446 447/* Memory Pool for BD headers */ 448struct wcn36xx_dxe_mem_pool { 449 int chunk_size; 450 void *virt_addr; 451 dma_addr_t phy_addr; 452}; 453 454struct wcn36xx_tx_bd; 455struct wcn36xx_vif; 456int wcn36xx_dxe_allocate_mem_pools(struct wcn36xx *wcn); 457void wcn36xx_dxe_free_mem_pools(struct wcn36xx *wcn); 458void wcn36xx_dxe_rx_frame(struct wcn36xx *wcn); 459int wcn36xx_dxe_alloc_ctl_blks(struct wcn36xx *wcn); 460void wcn36xx_dxe_free_ctl_blks(struct wcn36xx *wcn); 461int wcn36xx_dxe_init(struct wcn36xx *wcn); 462void wcn36xx_dxe_deinit(struct wcn36xx *wcn); 463int wcn36xx_dxe_init_channels(struct wcn36xx *wcn); 464int wcn36xx_dxe_tx_frame(struct wcn36xx *wcn, 465 struct wcn36xx_vif *vif_priv, 466 struct wcn36xx_tx_bd *bd, 467 struct sk_buff *skb, 468 bool is_low); 469int wcn36xx_dxe_tx_flush(struct wcn36xx *wcn); 470void wcn36xx_dxe_tx_ack_ind(struct wcn36xx *wcn, u32 status); 471#endif /* _DXE_H_ */