txrx.h (20504B)
1/* SPDX-License-Identifier: ISC */ 2/* 3 * Copyright (c) 2012-2016 Qualcomm Atheros, Inc. 4 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 5 */ 6 7#ifndef WIL6210_TXRX_H 8#define WIL6210_TXRX_H 9 10#include "wil6210.h" 11#include "txrx_edma.h" 12 13#define BUF_SW_OWNED (1) 14#define BUF_HW_OWNED (0) 15 16/* default size of MAC Tx/Rx buffers */ 17#define TXRX_BUF_LEN_DEFAULT (2048) 18 19/* how many bytes to reserve for rtap header? */ 20#define WIL6210_RTAP_SIZE (128) 21 22/* Tx/Rx path */ 23 24static inline dma_addr_t wil_desc_addr(struct wil_ring_dma_addr *addr) 25{ 26 return le32_to_cpu(addr->addr_low) | 27 ((u64)le16_to_cpu(addr->addr_high) << 32); 28} 29 30static inline void wil_desc_addr_set(struct wil_ring_dma_addr *addr, 31 dma_addr_t pa) 32{ 33 addr->addr_low = cpu_to_le32(lower_32_bits(pa)); 34 addr->addr_high = cpu_to_le16((u16)upper_32_bits(pa)); 35} 36 37/* Tx descriptor - MAC part 38 * [dword 0] 39 * bit 0.. 9 : lifetime_expiry_value:10 40 * bit 10 : interrupt_en:1 41 * bit 11 : status_en:1 42 * bit 12..13 : txss_override:2 43 * bit 14 : timestamp_insertion:1 44 * bit 15 : duration_preserve:1 45 * bit 16..21 : reserved0:6 46 * bit 22..26 : mcs_index:5 47 * bit 27 : mcs_en:1 48 * bit 28..30 : reserved1:3 49 * bit 31 : sn_preserved:1 50 * [dword 1] 51 * bit 0.. 3 : pkt_mode:4 52 * bit 4 : pkt_mode_en:1 53 * bit 5 : mac_id_en:1 54 * bit 6..7 : mac_id:2 55 * bit 8..14 : reserved0:7 56 * bit 15 : ack_policy_en:1 57 * bit 16..19 : dst_index:4 58 * bit 20 : dst_index_en:1 59 * bit 21..22 : ack_policy:2 60 * bit 23 : lifetime_en:1 61 * bit 24..30 : max_retry:7 62 * bit 31 : max_retry_en:1 63 * [dword 2] 64 * bit 0.. 7 : num_of_descriptors:8 65 * bit 8..17 : reserved:10 66 * bit 18..19 : l2_translation_type:2 00 - bypass, 01 - 802.3, 10 - 802.11 67 * bit 20 : snap_hdr_insertion_en:1 68 * bit 21 : vlan_removal_en:1 69 * bit 22..31 : reserved0:10 70 * [dword 3] 71 * bit 0.. 31: ucode_cmd:32 72 */ 73struct vring_tx_mac { 74 u32 d[3]; 75 u32 ucode_cmd; 76} __packed; 77 78/* TX MAC Dword 0 */ 79#define MAC_CFG_DESC_TX_0_LIFETIME_EXPIRY_VALUE_POS 0 80#define MAC_CFG_DESC_TX_0_LIFETIME_EXPIRY_VALUE_LEN 10 81#define MAC_CFG_DESC_TX_0_LIFETIME_EXPIRY_VALUE_MSK 0x3FF 82 83#define MAC_CFG_DESC_TX_0_INTERRUP_EN_POS 10 84#define MAC_CFG_DESC_TX_0_INTERRUP_EN_LEN 1 85#define MAC_CFG_DESC_TX_0_INTERRUP_EN_MSK 0x400 86 87#define MAC_CFG_DESC_TX_0_STATUS_EN_POS 11 88#define MAC_CFG_DESC_TX_0_STATUS_EN_LEN 1 89#define MAC_CFG_DESC_TX_0_STATUS_EN_MSK 0x800 90 91#define MAC_CFG_DESC_TX_0_TXSS_OVERRIDE_POS 12 92#define MAC_CFG_DESC_TX_0_TXSS_OVERRIDE_LEN 2 93#define MAC_CFG_DESC_TX_0_TXSS_OVERRIDE_MSK 0x3000 94 95#define MAC_CFG_DESC_TX_0_TIMESTAMP_INSERTION_POS 14 96#define MAC_CFG_DESC_TX_0_TIMESTAMP_INSERTION_LEN 1 97#define MAC_CFG_DESC_TX_0_TIMESTAMP_INSERTION_MSK 0x4000 98 99#define MAC_CFG_DESC_TX_0_DURATION_PRESERVE_POS 15 100#define MAC_CFG_DESC_TX_0_DURATION_PRESERVE_LEN 1 101#define MAC_CFG_DESC_TX_0_DURATION_PRESERVE_MSK 0x8000 102 103#define MAC_CFG_DESC_TX_0_MCS_INDEX_POS 22 104#define MAC_CFG_DESC_TX_0_MCS_INDEX_LEN 5 105#define MAC_CFG_DESC_TX_0_MCS_INDEX_MSK 0x7C00000 106 107#define MAC_CFG_DESC_TX_0_MCS_EN_POS 27 108#define MAC_CFG_DESC_TX_0_MCS_EN_LEN 1 109#define MAC_CFG_DESC_TX_0_MCS_EN_MSK 0x8000000 110 111#define MAC_CFG_DESC_TX_0_SN_PRESERVED_POS 31 112#define MAC_CFG_DESC_TX_0_SN_PRESERVED_LEN 1 113#define MAC_CFG_DESC_TX_0_SN_PRESERVED_MSK 0x80000000 114 115/* TX MAC Dword 1 */ 116#define MAC_CFG_DESC_TX_1_PKT_MODE_POS 0 117#define MAC_CFG_DESC_TX_1_PKT_MODE_LEN 4 118#define MAC_CFG_DESC_TX_1_PKT_MODE_MSK 0xF 119 120#define MAC_CFG_DESC_TX_1_PKT_MODE_EN_POS 4 121#define MAC_CFG_DESC_TX_1_PKT_MODE_EN_LEN 1 122#define MAC_CFG_DESC_TX_1_PKT_MODE_EN_MSK 0x10 123 124#define MAC_CFG_DESC_TX_1_MAC_ID_EN_POS 5 125#define MAC_CFG_DESC_TX_1_MAC_ID_EN_LEN 1 126#define MAC_CFG_DESC_TX_1_MAC_ID_EN_MSK 0x20 127 128#define MAC_CFG_DESC_TX_1_MAC_ID_POS 6 129#define MAC_CFG_DESC_TX_1_MAC_ID_LEN 2 130#define MAC_CFG_DESC_TX_1_MAC_ID_MSK 0xc0 131 132#define MAC_CFG_DESC_TX_1_ACK_POLICY_EN_POS 15 133#define MAC_CFG_DESC_TX_1_ACK_POLICY_EN_LEN 1 134#define MAC_CFG_DESC_TX_1_ACK_POLICY_EN_MSK 0x8000 135 136#define MAC_CFG_DESC_TX_1_DST_INDEX_POS 16 137#define MAC_CFG_DESC_TX_1_DST_INDEX_LEN 4 138#define MAC_CFG_DESC_TX_1_DST_INDEX_MSK 0xF0000 139 140#define MAC_CFG_DESC_TX_1_DST_INDEX_EN_POS 20 141#define MAC_CFG_DESC_TX_1_DST_INDEX_EN_LEN 1 142#define MAC_CFG_DESC_TX_1_DST_INDEX_EN_MSK 0x100000 143 144#define MAC_CFG_DESC_TX_1_ACK_POLICY_POS 21 145#define MAC_CFG_DESC_TX_1_ACK_POLICY_LEN 2 146#define MAC_CFG_DESC_TX_1_ACK_POLICY_MSK 0x600000 147 148#define MAC_CFG_DESC_TX_1_LIFETIME_EN_POS 23 149#define MAC_CFG_DESC_TX_1_LIFETIME_EN_LEN 1 150#define MAC_CFG_DESC_TX_1_LIFETIME_EN_MSK 0x800000 151 152#define MAC_CFG_DESC_TX_1_MAX_RETRY_POS 24 153#define MAC_CFG_DESC_TX_1_MAX_RETRY_LEN 7 154#define MAC_CFG_DESC_TX_1_MAX_RETRY_MSK 0x7F000000 155 156#define MAC_CFG_DESC_TX_1_MAX_RETRY_EN_POS 31 157#define MAC_CFG_DESC_TX_1_MAX_RETRY_EN_LEN 1 158#define MAC_CFG_DESC_TX_1_MAX_RETRY_EN_MSK 0x80000000 159 160/* TX MAC Dword 2 */ 161#define MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_POS 0 162#define MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_LEN 8 163#define MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_MSK 0xFF 164 165#define MAC_CFG_DESC_TX_2_RESERVED_POS 8 166#define MAC_CFG_DESC_TX_2_RESERVED_LEN 10 167#define MAC_CFG_DESC_TX_2_RESERVED_MSK 0x3FF00 168 169#define MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_POS 18 170#define MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_LEN 2 171#define MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_MSK 0xC0000 172 173#define MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_POS 20 174#define MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_LEN 1 175#define MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_MSK 0x100000 176 177#define MAC_CFG_DESC_TX_2_VLAN_REMOVAL_EN_POS 21 178#define MAC_CFG_DESC_TX_2_VLAN_REMOVAL_EN_LEN 1 179#define MAC_CFG_DESC_TX_2_VLAN_REMOVAL_EN_MSK 0x200000 180 181/* TX MAC Dword 3 */ 182#define MAC_CFG_DESC_TX_3_UCODE_CMD_POS 0 183#define MAC_CFG_DESC_TX_3_UCODE_CMD_LEN 32 184#define MAC_CFG_DESC_TX_3_UCODE_CMD_MSK 0xFFFFFFFF 185 186/* TX DMA Dword 0 */ 187#define DMA_CFG_DESC_TX_0_L4_LENGTH_POS 0 188#define DMA_CFG_DESC_TX_0_L4_LENGTH_LEN 8 189#define DMA_CFG_DESC_TX_0_L4_LENGTH_MSK 0xFF 190 191#define DMA_CFG_DESC_TX_0_CMD_EOP_POS 8 192#define DMA_CFG_DESC_TX_0_CMD_EOP_LEN 1 193#define DMA_CFG_DESC_TX_0_CMD_EOP_MSK 0x100 194 195#define DMA_CFG_DESC_TX_0_CMD_MARK_WB_POS 9 196#define DMA_CFG_DESC_TX_0_CMD_MARK_WB_LEN 1 197#define DMA_CFG_DESC_TX_0_CMD_MARK_WB_MSK 0x200 198 199#define DMA_CFG_DESC_TX_0_CMD_DMA_IT_POS 10 200#define DMA_CFG_DESC_TX_0_CMD_DMA_IT_LEN 1 201#define DMA_CFG_DESC_TX_0_CMD_DMA_IT_MSK 0x400 202 203#define DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_POS 11 204#define DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_LEN 2 205#define DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_MSK 0x1800 206 207#define DMA_CFG_DESC_TX_0_TCP_SEG_EN_POS 13 208#define DMA_CFG_DESC_TX_0_TCP_SEG_EN_LEN 1 209#define DMA_CFG_DESC_TX_0_TCP_SEG_EN_MSK 0x2000 210 211#define DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_POS 14 212#define DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_LEN 1 213#define DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_MSK 0x4000 214 215#define DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_POS 15 216#define DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_LEN 1 217#define DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_MSK 0x8000 218 219#define DMA_CFG_DESC_TX_0_QID_POS 16 220#define DMA_CFG_DESC_TX_0_QID_LEN 5 221#define DMA_CFG_DESC_TX_0_QID_MSK 0x1F0000 222 223#define DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_POS 21 224#define DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_LEN 1 225#define DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_MSK 0x200000 226 227#define DMA_CFG_DESC_TX_0_L4_TYPE_POS 30 228#define DMA_CFG_DESC_TX_0_L4_TYPE_LEN 2 229#define DMA_CFG_DESC_TX_0_L4_TYPE_MSK 0xC0000000 /* L4 type: 0-UDP, 2-TCP */ 230 231#define DMA_CFG_DESC_TX_OFFLOAD_CFG_MAC_LEN_POS 0 232#define DMA_CFG_DESC_TX_OFFLOAD_CFG_MAC_LEN_LEN 7 233#define DMA_CFG_DESC_TX_OFFLOAD_CFG_MAC_LEN_MSK 0x7F /* MAC hdr len */ 234 235#define DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS 7 236#define DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_LEN 1 237#define DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_MSK 0x80 /* 1-IPv4, 0-IPv6 */ 238 239#define TX_DMA_STATUS_DU BIT(0) 240 241/* Tx descriptor - DMA part 242 * [dword 0] 243 * bit 0.. 7 : l4_length:8 layer 4 length 244 * bit 8 : cmd_eop:1 This descriptor is the last one in the packet 245 * bit 9 : reserved 246 * bit 10 : cmd_dma_it:1 immediate interrupt 247 * bit 11..12 : SBD - Segment Buffer Details 248 * 00 - Header Segment 249 * 01 - First Data Segment 250 * 10 - Medium Data Segment 251 * 11 - Last Data Segment 252 * bit 13 : TSE - TCP Segmentation Enable 253 * bit 14 : IIC - Directs the HW to Insert IPv4 Checksum 254 * bit 15 : ITC - Directs the HW to Insert TCP/UDP Checksum 255 * bit 16..20 : QID - The target QID that the packet should be stored 256 * in the MAC. 257 * bit 21 : PO - Pseudo header Offload: 258 * 0 - Use the pseudo header value from the TCP checksum field 259 * 1- Calculate Pseudo header Checksum 260 * bit 22 : NC - No UDP Checksum 261 * bit 23..29 : reserved 262 * bit 30..31 : L4T - Layer 4 Type: 00 - UDP , 10 - TCP , 10, 11 - Reserved 263 * If L4Len equal 0, no L4 at all 264 * [dword 1] 265 * bit 0..31 : addr_low:32 The payload buffer low address 266 * [dword 2] 267 * bit 0..15 : addr_high:16 The payload buffer high address 268 * bit 16..23 : ip_length:8 The IP header length for the TX IP checksum 269 * offload feature 270 * bit 24..30 : mac_length:7 271 * bit 31 : ip_version:1 1 - IPv4, 0 - IPv6 272 * [dword 3] 273 * [byte 12] error 274 * bit 0 2 : mac_status:3 275 * bit 3 7 : reserved:5 276 * [byte 13] status 277 * bit 0 : DU:1 Descriptor Used 278 * bit 1 7 : reserved:7 279 * [word 7] length 280 */ 281struct vring_tx_dma { 282 u32 d0; 283 struct wil_ring_dma_addr addr; 284 u8 ip_length; 285 u8 b11; /* 0..6: mac_length; 7:ip_version */ 286 u8 error; /* 0..2: err; 3..7: reserved; */ 287 u8 status; /* 0: used; 1..7; reserved */ 288 __le16 length; 289} __packed; 290 291/* TSO type used in dma descriptor d0 bits 11-12 */ 292enum { 293 wil_tso_type_hdr = 0, 294 wil_tso_type_first = 1, 295 wil_tso_type_mid = 2, 296 wil_tso_type_lst = 3, 297}; 298 299/* Rx descriptor - MAC part 300 * [dword 0] 301 * bit 0.. 3 : tid:4 The QoS (b3-0) TID Field 302 * bit 4.. 6 : cid:3 The Source index that was found during parsing the TA. 303 * This field is used to define the source of the packet 304 * bit 7 : MAC_id_valid:1, 1 if MAC virtual number is valid. 305 * bit 8.. 9 : mid:2 The MAC virtual number 306 * bit 10..11 : frame_type:2 : The FC (b3-2) - MPDU Type 307 * (management, data, control and extension) 308 * bit 12..15 : frame_subtype:4 : The FC (b7-4) - Frame Subtype 309 * bit 16..27 : seq_number:12 The received Sequence number field 310 * bit 28..31 : extended:4 extended subtype 311 * [dword 1] 312 * bit 0.. 3 : reserved 313 * bit 4.. 5 : key_id:2 314 * bit 6 : decrypt_bypass:1 315 * bit 7 : security:1 FC (b14) 316 * bit 8.. 9 : ds_bits:2 FC (b9-8) 317 * bit 10 : a_msdu_present:1 QoS (b7) 318 * bit 11 : a_msdu_type:1 QoS (b8) 319 * bit 12 : a_mpdu:1 part of AMPDU aggregation 320 * bit 13 : broadcast:1 321 * bit 14 : mutlicast:1 322 * bit 15 : reserved:1 323 * bit 16..20 : rx_mac_qid:5 The Queue Identifier that the packet 324 * is received from 325 * bit 21..24 : mcs:4 326 * bit 25..28 : mic_icr:4 this signal tells the DMA to assert an interrupt 327 * after it writes the packet 328 * bit 29..31 : reserved:3 329 * [dword 2] 330 * bit 0.. 2 : time_slot:3 The timeslot that the MPDU is received 331 * bit 3.. 4 : fc_protocol_ver:1 The FC (b1-0) - Protocol Version 332 * bit 5 : fc_order:1 The FC Control (b15) -Order 333 * bit 6.. 7 : qos_ack_policy:2 The QoS (b6-5) ack policy Field 334 * bit 8 : esop:1 The QoS (b4) ESOP field 335 * bit 9 : qos_rdg_more_ppdu:1 The QoS (b9) RDG field 336 * bit 10..14 : qos_reserved:5 The QoS (b14-10) Reserved field 337 * bit 15 : qos_ac_constraint:1 QoS (b15) 338 * bit 16..31 : pn_15_0:16 low 2 bytes of PN 339 * [dword 3] 340 * bit 0..31 : pn_47_16:32 high 4 bytes of PN 341 */ 342struct vring_rx_mac { 343 u32 d0; 344 u32 d1; 345 u16 w4; 346 u16 pn_15_0; 347 u32 pn_47_16; 348} __packed; 349 350/* Rx descriptor - DMA part 351 * [dword 0] 352 * bit 0.. 7 : l4_length:8 layer 4 length. The field is only valid if 353 * L4I bit is set 354 * bit 8 : cmd_eop:1 set to 1 355 * bit 9 : cmd_rt:1 set to 1 356 * bit 10 : cmd_dma_it:1 immediate interrupt 357 * bit 11..15 : reserved:5 358 * bit 16..29 : phy_info_length:14 It is valid when the PII is set. 359 * When the FFM bit is set bits 29-27 are used for for 360 * Flex Filter Match. Matching Index to one of the L2 361 * EtherType Flex Filter 362 * bit 30..31 : l4_type:2 valid if the L4I bit is set in the status field 363 * 00 - UDP, 01 - TCP, 10, 11 - reserved 364 * [dword 1] 365 * bit 0..31 : addr_low:32 The payload buffer low address 366 * [dword 2] 367 * bit 0..15 : addr_high:16 The payload buffer high address 368 * bit 16..23 : ip_length:8 The filed is valid only if the L3I bit is set 369 * bit 24..30 : mac_length:7 370 * bit 31 : ip_version:1 1 - IPv4, 0 - IPv6 371 * [dword 3] 372 * [byte 12] error 373 * bit 0 : FCS:1 374 * bit 1 : MIC:1 375 * bit 2 : Key miss:1 376 * bit 3 : Replay:1 377 * bit 4 : L3:1 IPv4 checksum 378 * bit 5 : L4:1 TCP/UDP checksum 379 * bit 6 7 : reserved:2 380 * [byte 13] status 381 * bit 0 : DU:1 Descriptor Used 382 * bit 1 : EOP:1 The descriptor indicates the End of Packet 383 * bit 2 : error:1 384 * bit 3 : MI:1 MAC Interrupt is asserted (according to parser decision) 385 * bit 4 : L3I:1 L3 identified and checksum calculated 386 * bit 5 : L4I:1 L4 identified and checksum calculated 387 * bit 6 : PII:1 PHY Info Included in the packet 388 * bit 7 : FFM:1 EtherType Flex Filter Match 389 * [word 7] length 390 */ 391 392#define RX_DMA_D0_CMD_DMA_EOP BIT(8) 393#define RX_DMA_D0_CMD_DMA_RT BIT(9) /* always 1 */ 394#define RX_DMA_D0_CMD_DMA_IT BIT(10) /* interrupt */ 395#define RX_MAC_D0_MAC_ID_VALID BIT(7) 396 397/* Error field */ 398#define RX_DMA_ERROR_FCS BIT(0) 399#define RX_DMA_ERROR_MIC BIT(1) 400#define RX_DMA_ERROR_KEY BIT(2) /* Key missing */ 401#define RX_DMA_ERROR_REPLAY BIT(3) 402#define RX_DMA_ERROR_L3_ERR BIT(4) 403#define RX_DMA_ERROR_L4_ERR BIT(5) 404 405/* Status field */ 406#define RX_DMA_STATUS_DU BIT(0) 407#define RX_DMA_STATUS_EOP BIT(1) 408#define RX_DMA_STATUS_ERROR BIT(2) 409#define RX_DMA_STATUS_MI BIT(3) /* MAC Interrupt is asserted */ 410#define RX_DMA_STATUS_L3I BIT(4) 411#define RX_DMA_STATUS_L4I BIT(5) 412#define RX_DMA_STATUS_PHY_INFO BIT(6) 413#define RX_DMA_STATUS_FFM BIT(7) /* EtherType Flex Filter Match */ 414 415/* IEEE 802.11, 8.5.2 EAPOL-Key frames */ 416#define WIL_KEY_INFO_KEY_TYPE BIT(3) /* val of 1 = Pairwise, 0 = Group key */ 417 418#define WIL_KEY_INFO_MIC BIT(8) 419#define WIL_KEY_INFO_ENCR_KEY_DATA BIT(12) /* for rsn only */ 420 421#define WIL_EAP_NONCE_LEN 32 422#define WIL_EAP_KEY_RSC_LEN 8 423#define WIL_EAP_REPLAY_COUNTER_LEN 8 424#define WIL_EAP_KEY_IV_LEN 16 425#define WIL_EAP_KEY_ID_LEN 8 426 427enum { 428 WIL_1X_TYPE_EAP_PACKET = 0, 429 WIL_1X_TYPE_EAPOL_START = 1, 430 WIL_1X_TYPE_EAPOL_LOGOFF = 2, 431 WIL_1X_TYPE_EAPOL_KEY = 3, 432}; 433 434#define WIL_EAPOL_KEY_TYPE_RSN 2 435#define WIL_EAPOL_KEY_TYPE_WPA 254 436 437struct wil_1x_hdr { 438 u8 version; 439 u8 type; 440 __be16 length; 441 /* followed by data */ 442} __packed; 443 444struct wil_eapol_key { 445 u8 type; 446 __be16 key_info; 447 __be16 key_length; 448 u8 replay_counter[WIL_EAP_REPLAY_COUNTER_LEN]; 449 u8 key_nonce[WIL_EAP_NONCE_LEN]; 450 u8 key_iv[WIL_EAP_KEY_IV_LEN]; 451 u8 key_rsc[WIL_EAP_KEY_RSC_LEN]; 452 u8 key_id[WIL_EAP_KEY_ID_LEN]; 453} __packed; 454 455struct vring_rx_dma { 456 u32 d0; 457 struct wil_ring_dma_addr addr; 458 u8 ip_length; 459 u8 b11; 460 u8 error; 461 u8 status; 462 __le16 length; 463} __packed; 464 465struct vring_tx_desc { 466 struct vring_tx_mac mac; 467 struct vring_tx_dma dma; 468} __packed; 469 470union wil_tx_desc { 471 struct vring_tx_desc legacy; 472 struct wil_tx_enhanced_desc enhanced; 473} __packed; 474 475struct vring_rx_desc { 476 struct vring_rx_mac mac; 477 struct vring_rx_dma dma; 478} __packed; 479 480union wil_rx_desc { 481 struct vring_rx_desc legacy; 482 struct wil_rx_enhanced_desc enhanced; 483} __packed; 484 485union wil_ring_desc { 486 union wil_tx_desc tx; 487 union wil_rx_desc rx; 488} __packed; 489 490struct packet_rx_info { 491 u8 cid; 492}; 493 494/* this struct will be stored in the skb cb buffer 495 * max length of the struct is limited to 48 bytes 496 */ 497struct skb_rx_info { 498 struct vring_rx_desc rx_desc; 499 struct packet_rx_info rx_info; 500}; 501 502static inline int wil_rxdesc_tid(struct vring_rx_desc *d) 503{ 504 return WIL_GET_BITS(d->mac.d0, 0, 3); 505} 506 507static inline int wil_rxdesc_cid(struct vring_rx_desc *d) 508{ 509 return WIL_GET_BITS(d->mac.d0, 4, 6); 510} 511 512static inline int wil_rxdesc_mid(struct vring_rx_desc *d) 513{ 514 return (d->mac.d0 & RX_MAC_D0_MAC_ID_VALID) ? 515 WIL_GET_BITS(d->mac.d0, 8, 9) : 0; 516} 517 518static inline int wil_rxdesc_ftype(struct vring_rx_desc *d) 519{ 520 return WIL_GET_BITS(d->mac.d0, 10, 11); 521} 522 523static inline int wil_rxdesc_subtype(struct vring_rx_desc *d) 524{ 525 return WIL_GET_BITS(d->mac.d0, 12, 15); 526} 527 528/* 1-st byte (with frame type/subtype) of FC field */ 529static inline u8 wil_rxdesc_fc1(struct vring_rx_desc *d) 530{ 531 return (u8)(WIL_GET_BITS(d->mac.d0, 10, 15) << 2); 532} 533 534static inline int wil_rxdesc_seq(struct vring_rx_desc *d) 535{ 536 return WIL_GET_BITS(d->mac.d0, 16, 27); 537} 538 539static inline int wil_rxdesc_ext_subtype(struct vring_rx_desc *d) 540{ 541 return WIL_GET_BITS(d->mac.d0, 28, 31); 542} 543 544static inline int wil_rxdesc_retry(struct vring_rx_desc *d) 545{ 546 return WIL_GET_BITS(d->mac.d0, 31, 31); 547} 548 549static inline int wil_rxdesc_key_id(struct vring_rx_desc *d) 550{ 551 return WIL_GET_BITS(d->mac.d1, 4, 5); 552} 553 554static inline int wil_rxdesc_security(struct vring_rx_desc *d) 555{ 556 return WIL_GET_BITS(d->mac.d1, 7, 7); 557} 558 559static inline int wil_rxdesc_ds_bits(struct vring_rx_desc *d) 560{ 561 return WIL_GET_BITS(d->mac.d1, 8, 9); 562} 563 564static inline int wil_rxdesc_mcs(struct vring_rx_desc *d) 565{ 566 return WIL_GET_BITS(d->mac.d1, 21, 24); 567} 568 569static inline int wil_rxdesc_mcast(struct vring_rx_desc *d) 570{ 571 return WIL_GET_BITS(d->mac.d1, 13, 14); 572} 573 574static inline struct vring_rx_desc *wil_skb_rxdesc(struct sk_buff *skb) 575{ 576 return (void *)skb->cb; 577} 578 579static inline int wil_ring_is_empty(struct wil_ring *ring) 580{ 581 return ring->swhead == ring->swtail; 582} 583 584static inline u32 wil_ring_next_tail(struct wil_ring *ring) 585{ 586 return (ring->swtail + 1) % ring->size; 587} 588 589static inline void wil_ring_advance_head(struct wil_ring *ring, int n) 590{ 591 ring->swhead = (ring->swhead + n) % ring->size; 592} 593 594static inline int wil_ring_is_full(struct wil_ring *ring) 595{ 596 return wil_ring_next_tail(ring) == ring->swhead; 597} 598 599static inline u8 *wil_skb_get_da(struct sk_buff *skb) 600{ 601 struct ethhdr *eth = (void *)skb->data; 602 603 return eth->h_dest; 604} 605 606static inline u8 *wil_skb_get_sa(struct sk_buff *skb) 607{ 608 struct ethhdr *eth = (void *)skb->data; 609 610 return eth->h_source; 611} 612 613static inline bool wil_need_txstat(struct sk_buff *skb) 614{ 615 const u8 *da = wil_skb_get_da(skb); 616 617 return is_unicast_ether_addr(da) && skb->sk && 618 (skb_shinfo(skb)->tx_flags & SKBTX_WIFI_STATUS); 619} 620 621static inline void wil_consume_skb(struct sk_buff *skb, bool acked) 622{ 623 if (unlikely(wil_need_txstat(skb))) 624 skb_complete_wifi_ack(skb, acked); 625 else 626 acked ? dev_consume_skb_any(skb) : dev_kfree_skb_any(skb); 627} 628 629/* Used space in Tx ring */ 630static inline int wil_ring_used_tx(struct wil_ring *ring) 631{ 632 u32 swhead = ring->swhead; 633 u32 swtail = ring->swtail; 634 635 return (ring->size + swhead - swtail) % ring->size; 636} 637 638/* Available space in Tx ring */ 639static inline int wil_ring_avail_tx(struct wil_ring *ring) 640{ 641 return ring->size - wil_ring_used_tx(ring) - 1; 642} 643 644static inline int wil_get_min_tx_ring_id(struct wil6210_priv *wil) 645{ 646 /* In Enhanced DMA ring 0 is reserved for RX */ 647 return wil->use_enhanced_dma_hw ? 1 : 0; 648} 649 650/* similar to ieee80211_ version, but FC contain only 1-st byte */ 651static inline int wil_is_back_req(u8 fc) 652{ 653 return (fc & (IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE)) == 654 (IEEE80211_FTYPE_CTL | IEEE80211_STYPE_BACK_REQ); 655} 656 657/* wil_val_in_range - check if value in [min,max) */ 658static inline bool wil_val_in_range(int val, int min, int max) 659{ 660 return val >= min && val < max; 661} 662 663static inline u8 wil_skb_get_cid(struct sk_buff *skb) 664{ 665 struct skb_rx_info *skb_rx_info = (void *)skb->cb; 666 667 return skb_rx_info->rx_info.cid; 668} 669 670static inline void wil_skb_set_cid(struct sk_buff *skb, u8 cid) 671{ 672 struct skb_rx_info *skb_rx_info = (void *)skb->cb; 673 674 skb_rx_info->rx_info.cid = cid; 675} 676 677void wil_netif_rx_any(struct sk_buff *skb, struct net_device *ndev); 678void wil_netif_rx(struct sk_buff *skb, struct net_device *ndev, int cid, 679 struct wil_net_stats *stats, bool gro); 680void wil_rx_reorder(struct wil6210_priv *wil, struct sk_buff *skb); 681void wil_rx_bar(struct wil6210_priv *wil, struct wil6210_vif *vif, 682 u8 cid, u8 tid, u16 seq); 683struct wil_tid_ampdu_rx *wil_tid_ampdu_rx_alloc(struct wil6210_priv *wil, 684 int size, u16 ssn); 685void wil_tid_ampdu_rx_free(struct wil6210_priv *wil, 686 struct wil_tid_ampdu_rx *r); 687void wil_tx_data_init(struct wil_ring_tx_data *txdata); 688void wil_init_txrx_ops_legacy_dma(struct wil6210_priv *wil); 689void wil_tx_latency_calc(struct wil6210_priv *wil, struct sk_buff *skb, 690 struct wil_sta_info *sta); 691 692#endif /* WIL6210_TXRX_H */