cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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binding.h (4376B)


      1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
      2/*
      3 * Copyright (C) 2012-2014, 2020 Intel Corporation
      4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
      5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
      6 */
      7#ifndef __iwl_fw_api_binding_h__
      8#define __iwl_fw_api_binding_h__
      9
     10#include <fw/file.h>
     11#include <fw/img.h>
     12
     13#define MAX_MACS_IN_BINDING	(3)
     14#define MAX_BINDINGS		(4)
     15
     16/**
     17 * struct iwl_binding_cmd_v1 - configuring bindings
     18 * ( BINDING_CONTEXT_CMD = 0x2b )
     19 * @id_and_color: ID and color of the relevant Binding,
     20 *	&enum iwl_ctxt_id_and_color
     21 * @action: action to perform, one of FW_CTXT_ACTION_*
     22 * @macs: array of MAC id and colors which belong to the binding,
     23 *	&enum iwl_ctxt_id_and_color
     24 * @phy: PHY id and color which belongs to the binding,
     25 *	&enum iwl_ctxt_id_and_color
     26 */
     27struct iwl_binding_cmd_v1 {
     28	/* COMMON_INDEX_HDR_API_S_VER_1 */
     29	__le32 id_and_color;
     30	__le32 action;
     31	/* BINDING_DATA_API_S_VER_1 */
     32	__le32 macs[MAX_MACS_IN_BINDING];
     33	__le32 phy;
     34} __packed; /* BINDING_CMD_API_S_VER_1 */
     35
     36/**
     37 * struct iwl_binding_cmd - configuring bindings
     38 * ( BINDING_CONTEXT_CMD = 0x2b )
     39 * @id_and_color: ID and color of the relevant Binding,
     40 *	&enum iwl_ctxt_id_and_color
     41 * @action: action to perform, one of FW_CTXT_ACTION_*
     42 * @macs: array of MAC id and colors which belong to the binding
     43 *	&enum iwl_ctxt_id_and_color
     44 * @phy: PHY id and color which belongs to the binding
     45 *	&enum iwl_ctxt_id_and_color
     46 * @lmac_id: the lmac id the binding belongs to
     47 */
     48struct iwl_binding_cmd {
     49	/* COMMON_INDEX_HDR_API_S_VER_1 */
     50	__le32 id_and_color;
     51	__le32 action;
     52	/* BINDING_DATA_API_S_VER_1 */
     53	__le32 macs[MAX_MACS_IN_BINDING];
     54	__le32 phy;
     55	__le32 lmac_id;
     56} __packed; /* BINDING_CMD_API_S_VER_2 */
     57
     58#define IWL_BINDING_CMD_SIZE_V1	sizeof(struct iwl_binding_cmd_v1)
     59#define IWL_LMAC_24G_INDEX		0
     60#define IWL_LMAC_5G_INDEX		1
     61
     62static inline u32 iwl_mvm_get_lmac_id(const struct iwl_fw *fw,
     63				      enum nl80211_band band){
     64	if (!fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_CDB_SUPPORT) ||
     65	    band == NL80211_BAND_2GHZ)
     66		return IWL_LMAC_24G_INDEX;
     67	return IWL_LMAC_5G_INDEX;
     68}
     69
     70/* The maximal number of fragments in the FW's schedule session */
     71#define IWL_MVM_MAX_QUOTA 128
     72
     73/**
     74 * struct iwl_time_quota_data_v1 - configuration of time quota per binding
     75 * @id_and_color: ID and color of the relevant Binding,
     76 *	&enum iwl_ctxt_id_and_color
     77 * @quota: absolute time quota in TU. The scheduler will try to divide the
     78 *	remainig quota (after Time Events) according to this quota.
     79 * @max_duration: max uninterrupted context duration in TU
     80 */
     81struct iwl_time_quota_data_v1 {
     82	__le32 id_and_color;
     83	__le32 quota;
     84	__le32 max_duration;
     85} __packed; /* TIME_QUOTA_DATA_API_S_VER_1 */
     86
     87/**
     88 * struct iwl_time_quota_cmd - configuration of time quota between bindings
     89 * ( TIME_QUOTA_CMD = 0x2c )
     90 * @quotas: allocations per binding
     91 * Note: on non-CDB the fourth one is the auxilary mac and is
     92 *	essentially zero.
     93 *	On CDB the fourth one is a regular binding.
     94 */
     95struct iwl_time_quota_cmd_v1 {
     96	struct iwl_time_quota_data_v1 quotas[MAX_BINDINGS];
     97} __packed; /* TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */
     98
     99enum iwl_quota_low_latency {
    100	IWL_QUOTA_LOW_LATENCY_NONE = 0,
    101	IWL_QUOTA_LOW_LATENCY_TX = BIT(0),
    102	IWL_QUOTA_LOW_LATENCY_RX = BIT(1),
    103	IWL_QUOTA_LOW_LATENCY_TX_RX =
    104		IWL_QUOTA_LOW_LATENCY_TX | IWL_QUOTA_LOW_LATENCY_RX,
    105};
    106
    107/**
    108 * struct iwl_time_quota_data - configuration of time quota per binding
    109 * @id_and_color: ID and color of the relevant Binding.
    110 * @quota: absolute time quota in TU. The scheduler will try to divide the
    111 *	remainig quota (after Time Events) according to this quota.
    112 * @max_duration: max uninterrupted context duration in TU
    113 * @low_latency: low latency status, &enum iwl_quota_low_latency
    114 */
    115struct iwl_time_quota_data {
    116	__le32 id_and_color;
    117	__le32 quota;
    118	__le32 max_duration;
    119	__le32 low_latency;
    120} __packed; /* TIME_QUOTA_DATA_API_S_VER_2 */
    121
    122/**
    123 * struct iwl_time_quota_cmd - configuration of time quota between bindings
    124 * ( TIME_QUOTA_CMD = 0x2c )
    125 * Note: on non-CDB the fourth one is the auxilary mac and is essentially zero.
    126 * On CDB the fourth one is a regular binding.
    127 *
    128 * @quotas: allocations per binding
    129 */
    130struct iwl_time_quota_cmd {
    131	struct iwl_time_quota_data quotas[MAX_BINDINGS];
    132} __packed; /* TIME_QUOTA_ALLOCATION_CMD_API_S_VER_2 */
    133
    134#endif /* __iwl_fw_api_binding_h__ */