cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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sf.h (2931B)


      1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
      2/*
      3 * Copyright (C) 2012-2014 Intel Corporation
      4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
      5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
      6 */
      7#ifndef __iwl_fw_api_sf_h__
      8#define __iwl_fw_api_sf_h__
      9
     10/* Smart Fifo state */
     11enum iwl_sf_state {
     12	SF_LONG_DELAY_ON = 0, /* should never be called by driver */
     13	SF_FULL_ON,
     14	SF_UNINIT,
     15	SF_INIT_OFF,
     16	SF_HW_NUM_STATES
     17};
     18
     19/* Smart Fifo possible scenario */
     20enum iwl_sf_scenario {
     21	SF_SCENARIO_SINGLE_UNICAST,
     22	SF_SCENARIO_AGG_UNICAST,
     23	SF_SCENARIO_MULTICAST,
     24	SF_SCENARIO_BA_RESP,
     25	SF_SCENARIO_TX_RESP,
     26	SF_NUM_SCENARIO
     27};
     28
     29#define SF_TRANSIENT_STATES_NUMBER 2	/* SF_LONG_DELAY_ON and SF_FULL_ON */
     30#define SF_NUM_TIMEOUT_TYPES 2		/* Aging timer and Idle timer */
     31
     32/* smart FIFO default values */
     33#define SF_W_MARK_SISO 6144
     34#define SF_W_MARK_MIMO2 8192
     35#define SF_W_MARK_MIMO3 6144
     36#define SF_W_MARK_LEGACY 4096
     37#define SF_W_MARK_SCAN 4096
     38
     39/* SF Scenarios timers for default configuration (aligned to 32 uSec) */
     40#define SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160	/* 150 uSec  */
     41#define SF_SINGLE_UNICAST_AGING_TIMER_DEF 400	/* 0.4 mSec */
     42#define SF_AGG_UNICAST_IDLE_TIMER_DEF 160		/* 150 uSec */
     43#define SF_AGG_UNICAST_AGING_TIMER_DEF 400		/* 0.4 mSec */
     44#define SF_MCAST_IDLE_TIMER_DEF 160		/* 150 mSec */
     45#define SF_MCAST_AGING_TIMER_DEF 400		/* 0.4 mSec */
     46#define SF_BA_IDLE_TIMER_DEF 160			/* 150 uSec */
     47#define SF_BA_AGING_TIMER_DEF 400			/* 0.4 mSec */
     48#define SF_TX_RE_IDLE_TIMER_DEF 160			/* 150 uSec */
     49#define SF_TX_RE_AGING_TIMER_DEF 400		/* 0.4 mSec */
     50
     51/* SF Scenarios timers for BSS MAC configuration (aligned to 32 uSec) */
     52#define SF_SINGLE_UNICAST_IDLE_TIMER 320	/* 300 uSec  */
     53#define SF_SINGLE_UNICAST_AGING_TIMER 2016	/* 2 mSec */
     54#define SF_AGG_UNICAST_IDLE_TIMER 320		/* 300 uSec */
     55#define SF_AGG_UNICAST_AGING_TIMER 2016		/* 2 mSec */
     56#define SF_MCAST_IDLE_TIMER 2016		/* 2 mSec */
     57#define SF_MCAST_AGING_TIMER 10016		/* 10 mSec */
     58#define SF_BA_IDLE_TIMER 320			/* 300 uSec */
     59#define SF_BA_AGING_TIMER 2016			/* 2 mSec */
     60#define SF_TX_RE_IDLE_TIMER 320			/* 300 uSec */
     61#define SF_TX_RE_AGING_TIMER 2016		/* 2 mSec */
     62
     63#define SF_LONG_DELAY_AGING_TIMER 1000000	/* 1 Sec */
     64
     65#define SF_CFG_DUMMY_NOTIF_OFF	BIT(16)
     66
     67/**
     68 * struct iwl_sf_cfg_cmd - Smart Fifo configuration command.
     69 * @state: smart fifo state, types listed in &enum iwl_sf_state.
     70 * @watermark: Minimum allowed available free space in RXF for transient state.
     71 * @long_delay_timeouts: aging and idle timer values for each scenario
     72 * in long delay state.
     73 * @full_on_timeouts: timer values for each scenario in full on state.
     74 */
     75struct iwl_sf_cfg_cmd {
     76	__le32 state;
     77	__le32 watermark[SF_TRANSIENT_STATES_NUMBER];
     78	__le32 long_delay_timeouts[SF_NUM_SCENARIO][SF_NUM_TIMEOUT_TYPES];
     79	__le32 full_on_timeouts[SF_NUM_SCENARIO][SF_NUM_TIMEOUT_TYPES];
     80} __packed; /* SF_CFG_API_S_VER_2 */
     81
     82#endif /* __iwl_fw_api_sf_h__ */