cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
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iwl-config.h (23204B)


      1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
      2/*
      3 * Copyright (C) 2005-2014, 2018-2021 Intel Corporation
      4 * Copyright (C) 2016-2017 Intel Deutschland GmbH
      5 */
      6#ifndef __IWL_CONFIG_H__
      7#define __IWL_CONFIG_H__
      8
      9#include <linux/types.h>
     10#include <linux/netdevice.h>
     11#include <linux/ieee80211.h>
     12#include <linux/nl80211.h>
     13#include "iwl-csr.h"
     14
     15enum iwl_device_family {
     16	IWL_DEVICE_FAMILY_UNDEFINED,
     17	IWL_DEVICE_FAMILY_1000,
     18	IWL_DEVICE_FAMILY_100,
     19	IWL_DEVICE_FAMILY_2000,
     20	IWL_DEVICE_FAMILY_2030,
     21	IWL_DEVICE_FAMILY_105,
     22	IWL_DEVICE_FAMILY_135,
     23	IWL_DEVICE_FAMILY_5000,
     24	IWL_DEVICE_FAMILY_5150,
     25	IWL_DEVICE_FAMILY_6000,
     26	IWL_DEVICE_FAMILY_6000i,
     27	IWL_DEVICE_FAMILY_6005,
     28	IWL_DEVICE_FAMILY_6030,
     29	IWL_DEVICE_FAMILY_6050,
     30	IWL_DEVICE_FAMILY_6150,
     31	IWL_DEVICE_FAMILY_7000,
     32	IWL_DEVICE_FAMILY_8000,
     33	IWL_DEVICE_FAMILY_9000,
     34	IWL_DEVICE_FAMILY_22000,
     35	IWL_DEVICE_FAMILY_AX210,
     36	IWL_DEVICE_FAMILY_BZ,
     37};
     38
     39/*
     40 * LED mode
     41 *    IWL_LED_DEFAULT:  use device default
     42 *    IWL_LED_RF_STATE: turn LED on/off based on RF state
     43 *			LED ON  = RF ON
     44 *			LED OFF = RF OFF
     45 *    IWL_LED_BLINK:    adjust led blink rate based on blink table
     46 *    IWL_LED_DISABLE:	led disabled
     47 */
     48enum iwl_led_mode {
     49	IWL_LED_DEFAULT,
     50	IWL_LED_RF_STATE,
     51	IWL_LED_BLINK,
     52	IWL_LED_DISABLE,
     53};
     54
     55/**
     56 * enum iwl_nvm_type - nvm formats
     57 * @IWL_NVM: the regular format
     58 * @IWL_NVM_EXT: extended NVM format
     59 * @IWL_NVM_SDP: NVM format used by 3168 series
     60 */
     61enum iwl_nvm_type {
     62	IWL_NVM,
     63	IWL_NVM_EXT,
     64	IWL_NVM_SDP,
     65};
     66
     67/*
     68 * This is the threshold value of plcp error rate per 100mSecs.  It is
     69 * used to set and check for the validity of plcp_delta.
     70 */
     71#define IWL_MAX_PLCP_ERR_THRESHOLD_MIN		1
     72#define IWL_MAX_PLCP_ERR_THRESHOLD_DEF		50
     73#define IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF	100
     74#define IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF	200
     75#define IWL_MAX_PLCP_ERR_THRESHOLD_MAX		255
     76#define IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE	0
     77
     78/* TX queue watchdog timeouts in mSecs */
     79#define IWL_WATCHDOG_DISABLED	0
     80#define IWL_DEF_WD_TIMEOUT	2500
     81#define IWL_LONG_WD_TIMEOUT	10000
     82#define IWL_MAX_WD_TIMEOUT	120000
     83
     84#define IWL_DEFAULT_MAX_TX_POWER 22
     85#define IWL_TX_CSUM_NETIF_FLAGS (NETIF_F_IPV6_CSUM | NETIF_F_IP_CSUM |\
     86				 NETIF_F_TSO | NETIF_F_TSO6)
     87#define IWL_TX_CSUM_NETIF_FLAGS_BZ (NETIF_F_HW_CSUM | NETIF_F_TSO | NETIF_F_TSO6)
     88#define IWL_CSUM_NETIF_FLAGS_MASK (IWL_TX_CSUM_NETIF_FLAGS | \
     89				   IWL_TX_CSUM_NETIF_FLAGS_BZ | \
     90				   NETIF_F_RXCSUM)
     91
     92/* Antenna presence definitions */
     93#define	ANT_NONE	0x0
     94#define	ANT_INVALID	0xff
     95#define	ANT_A		BIT(0)
     96#define	ANT_B		BIT(1)
     97#define ANT_C		BIT(2)
     98#define	ANT_AB		(ANT_A | ANT_B)
     99#define	ANT_AC		(ANT_A | ANT_C)
    100#define ANT_BC		(ANT_B | ANT_C)
    101#define ANT_ABC		(ANT_A | ANT_B | ANT_C)
    102
    103
    104static inline u8 num_of_ant(u8 mask)
    105{
    106	return  !!((mask) & ANT_A) +
    107		!!((mask) & ANT_B) +
    108		!!((mask) & ANT_C);
    109}
    110
    111/**
    112 * struct iwl_base_params - params not likely to change within a device family
    113 * @max_ll_items: max number of OTP blocks
    114 * @shadow_ram_support: shadow support for OTP memory
    115 * @led_compensation: compensate on the led on/off time per HW according
    116 *	to the deviation to achieve the desired led frequency.
    117 *	The detail algorithm is described in iwl-led.c
    118 * @wd_timeout: TX queues watchdog timeout
    119 * @max_event_log_size: size of event log buffer size for ucode event logging
    120 * @shadow_reg_enable: HW shadow register support
    121 * @apmg_wake_up_wa: should the MAC access REQ be asserted when a command
    122 *	is in flight. This is due to a HW bug in 7260, 3160 and 7265.
    123 * @scd_chain_ext_wa: should the chain extension feature in SCD be disabled.
    124 * @max_tfd_queue_size: max number of entries in tfd queue.
    125 */
    126struct iwl_base_params {
    127	unsigned int wd_timeout;
    128
    129	u16 eeprom_size;
    130	u16 max_event_log_size;
    131
    132	u8 pll_cfg:1, /* for iwl_pcie_apm_init() */
    133	   shadow_ram_support:1,
    134	   shadow_reg_enable:1,
    135	   pcie_l1_allowed:1,
    136	   apmg_wake_up_wa:1,
    137	   scd_chain_ext_wa:1;
    138
    139	u16 num_of_queues;	/* def: HW dependent */
    140	u32 max_tfd_queue_size;	/* def: HW dependent */
    141
    142	u8 max_ll_items;
    143	u8 led_compensation;
    144};
    145
    146/*
    147 * @stbc: support Tx STBC and 1*SS Rx STBC
    148 * @ldpc: support Tx/Rx with LDPC
    149 * @use_rts_for_aggregation: use rts/cts protection for HT traffic
    150 * @ht40_bands: bitmap of bands (using %NL80211_BAND_*) that support HT40
    151 */
    152struct iwl_ht_params {
    153	u8 ht_greenfield_support:1,
    154	   stbc:1,
    155	   ldpc:1,
    156	   use_rts_for_aggregation:1;
    157	u8 ht40_bands;
    158};
    159
    160/*
    161 * Tx-backoff threshold
    162 * @temperature: The threshold in Celsius
    163 * @backoff: The tx-backoff in uSec
    164 */
    165struct iwl_tt_tx_backoff {
    166	s32 temperature;
    167	u32 backoff;
    168};
    169
    170#define TT_TX_BACKOFF_SIZE 6
    171
    172/**
    173 * struct iwl_tt_params - thermal throttling parameters
    174 * @ct_kill_entry: CT Kill entry threshold
    175 * @ct_kill_exit: CT Kill exit threshold
    176 * @ct_kill_duration: The time  intervals (in uSec) in which the driver needs
    177 *	to checks whether to exit CT Kill.
    178 * @dynamic_smps_entry: Dynamic SMPS entry threshold
    179 * @dynamic_smps_exit: Dynamic SMPS exit threshold
    180 * @tx_protection_entry: TX protection entry threshold
    181 * @tx_protection_exit: TX protection exit threshold
    182 * @tx_backoff: Array of thresholds for tx-backoff , in ascending order.
    183 * @support_ct_kill: Support CT Kill?
    184 * @support_dynamic_smps: Support dynamic SMPS?
    185 * @support_tx_protection: Support tx protection?
    186 * @support_tx_backoff: Support tx-backoff?
    187 */
    188struct iwl_tt_params {
    189	u32 ct_kill_entry;
    190	u32 ct_kill_exit;
    191	u32 ct_kill_duration;
    192	u32 dynamic_smps_entry;
    193	u32 dynamic_smps_exit;
    194	u32 tx_protection_entry;
    195	u32 tx_protection_exit;
    196	struct iwl_tt_tx_backoff tx_backoff[TT_TX_BACKOFF_SIZE];
    197	u8 support_ct_kill:1,
    198	   support_dynamic_smps:1,
    199	   support_tx_protection:1,
    200	   support_tx_backoff:1;
    201};
    202
    203/*
    204 * information on how to parse the EEPROM
    205 */
    206#define EEPROM_REG_BAND_1_CHANNELS		0x08
    207#define EEPROM_REG_BAND_2_CHANNELS		0x26
    208#define EEPROM_REG_BAND_3_CHANNELS		0x42
    209#define EEPROM_REG_BAND_4_CHANNELS		0x5C
    210#define EEPROM_REG_BAND_5_CHANNELS		0x74
    211#define EEPROM_REG_BAND_24_HT40_CHANNELS	0x82
    212#define EEPROM_REG_BAND_52_HT40_CHANNELS	0x92
    213#define EEPROM_6000_REG_BAND_24_HT40_CHANNELS	0x80
    214#define EEPROM_REGULATORY_BAND_NO_HT40		0
    215
    216/* lower blocks contain EEPROM image and calibration data */
    217#define OTP_LOW_IMAGE_SIZE_2K		(2 * 512 * sizeof(u16))  /*  2 KB */
    218#define OTP_LOW_IMAGE_SIZE_16K		(16 * 512 * sizeof(u16)) /* 16 KB */
    219#define OTP_LOW_IMAGE_SIZE_32K		(32 * 512 * sizeof(u16)) /* 32 KB */
    220
    221struct iwl_eeprom_params {
    222	const u8 regulatory_bands[7];
    223	bool enhanced_txpower;
    224};
    225
    226/* Tx-backoff power threshold
    227 * @pwr: The power limit in mw
    228 * @backoff: The tx-backoff in uSec
    229 */
    230struct iwl_pwr_tx_backoff {
    231	u32 pwr;
    232	u32 backoff;
    233};
    234
    235enum iwl_cfg_trans_ltr_delay {
    236	IWL_CFG_TRANS_LTR_DELAY_NONE	= 0,
    237	IWL_CFG_TRANS_LTR_DELAY_200US	= 1,
    238	IWL_CFG_TRANS_LTR_DELAY_2500US	= 2,
    239	IWL_CFG_TRANS_LTR_DELAY_1820US	= 3,
    240};
    241
    242/**
    243 * struct iwl_cfg_trans - information needed to start the trans
    244 *
    245 * These values are specific to the device ID and do not change when
    246 * multiple configs are used for a single device ID.  They values are
    247 * used, among other things, to boot the NIC so that the HW REV or
    248 * RFID can be read before deciding the remaining parameters to use.
    249 *
    250 * @base_params: pointer to basic parameters
    251 * @csr: csr flags and addresses that are different across devices
    252 * @device_family: the device family
    253 * @umac_prph_offset: offset to add to UMAC periphery address
    254 * @xtal_latency: power up latency to get the xtal stabilized
    255 * @extra_phy_cfg_flags: extra configuration flags to pass to the PHY
    256 * @rf_id: need to read rf_id to determine the firmware image
    257 * @use_tfh: use TFH
    258 * @gen2: 22000 and on transport operation
    259 * @mq_rx_supported: multi-queue rx support
    260 * @integrated: discrete or integrated
    261 * @low_latency_xtal: use the low latency xtal if supported
    262 * @ltr_delay: LTR delay parameter, &enum iwl_cfg_trans_ltr_delay.
    263 * @imr_enabled: use the IMR if supported.
    264 */
    265struct iwl_cfg_trans_params {
    266	const struct iwl_base_params *base_params;
    267	enum iwl_device_family device_family;
    268	u32 umac_prph_offset;
    269	u32 xtal_latency;
    270	u32 extra_phy_cfg_flags;
    271	u32 rf_id:1,
    272	    use_tfh:1,
    273	    gen2:1,
    274	    mq_rx_supported:1,
    275	    integrated:1,
    276	    low_latency_xtal:1,
    277	    bisr_workaround:1,
    278	    ltr_delay:2,
    279	    imr_enabled:1;
    280};
    281
    282/**
    283 * struct iwl_fw_mon_reg - FW monitor register info
    284 * @addr: register address
    285 * @mask: register mask
    286 */
    287struct iwl_fw_mon_reg {
    288	u32 addr;
    289	u32 mask;
    290};
    291
    292/**
    293 * struct iwl_fw_mon_regs - FW monitor registers
    294 * @write_ptr: write pointer register
    295 * @cycle_cnt: cycle count register
    296 * @cur_frag: current fragment in use
    297 */
    298struct iwl_fw_mon_regs {
    299	struct iwl_fw_mon_reg write_ptr;
    300	struct iwl_fw_mon_reg cycle_cnt;
    301	struct iwl_fw_mon_reg cur_frag;
    302};
    303
    304/**
    305 * struct iwl_cfg
    306 * @trans: the trans-specific configuration part
    307 * @name: Official name of the device
    308 * @fw_name_pre: Firmware filename prefix. The api version and extension
    309 *	(.ucode) will be added to filename before loading from disk. The
    310 *	filename is constructed as fw_name_pre<api>.ucode.
    311 * @ucode_api_max: Highest version of uCode API supported by driver.
    312 * @ucode_api_min: Lowest version of uCode API supported by driver.
    313 * @max_inst_size: The maximal length of the fw inst section (only DVM)
    314 * @max_data_size: The maximal length of the fw data section (only DVM)
    315 * @valid_tx_ant: valid transmit antenna
    316 * @valid_rx_ant: valid receive antenna
    317 * @non_shared_ant: the antenna that is for WiFi only
    318 * @nvm_ver: NVM version
    319 * @nvm_calib_ver: NVM calibration version
    320 * @lib: pointer to the lib ops
    321 * @ht_params: point to ht parameters
    322 * @led_mode: 0=blinking, 1=On(RF On)/Off(RF Off)
    323 * @rx_with_siso_diversity: 1x1 device with rx antenna diversity
    324 * @tx_with_siso_diversity: 1x1 device with tx antenna diversity
    325 * @internal_wimax_coex: internal wifi/wimax combo device
    326 * @high_temp: Is this NIC is designated to be in high temperature.
    327 * @host_interrupt_operation_mode: device needs host interrupt operation
    328 *	mode set
    329 * @nvm_hw_section_num: the ID of the HW NVM section
    330 * @mac_addr_from_csr: read HW address from CSR registers at this offset
    331 * @features: hw features, any combination of feature_passlist
    332 * @pwr_tx_backoffs: translation table between power limits and backoffs
    333 * @max_tx_agg_size: max TX aggregation size of the ADDBA request/response
    334 * @dccm_offset: offset from which DCCM begins
    335 * @dccm_len: length of DCCM (including runtime stack CCM)
    336 * @dccm2_offset: offset from which the second DCCM begins
    337 * @dccm2_len: length of the second DCCM
    338 * @smem_offset: offset from which the SMEM begins
    339 * @smem_len: the length of SMEM
    340 * @vht_mu_mimo_supported: VHT MU-MIMO support
    341 * @cdb: CDB support
    342 * @nvm_type: see &enum iwl_nvm_type
    343 * @d3_debug_data_base_addr: base address where D3 debug data is stored
    344 * @d3_debug_data_length: length of the D3 debug data
    345 * @bisr_workaround: BISR hardware workaround (for 22260 series devices)
    346 * @min_txq_size: minimum number of slots required in a TX queue
    347 * @uhb_supported: ultra high band channels supported
    348 * @min_ba_txq_size: minimum number of slots required in a TX queue which
    349 *	based on hardware support (HE - 256, EHT - 1K).
    350 * @num_rbds: number of receive buffer descriptors to use
    351 *	(only used for multi-queue capable devices)
    352 * @mac_addr_csr_base: CSR base register for MAC address access, if not set
    353 *	assume 0x380
    354 *
    355 * We enable the driver to be backward compatible wrt. hardware features.
    356 * API differences in uCode shouldn't be handled here but through TLVs
    357 * and/or the uCode API version instead.
    358 */
    359struct iwl_cfg {
    360	struct iwl_cfg_trans_params trans;
    361	/* params specific to an individual device within a device family */
    362	const char *name;
    363	const char *fw_name_pre;
    364	/* params likely to change within a device family */
    365	const struct iwl_ht_params *ht_params;
    366	const struct iwl_eeprom_params *eeprom_params;
    367	const struct iwl_pwr_tx_backoff *pwr_tx_backoffs;
    368	const char *default_nvm_file_C_step;
    369	const struct iwl_tt_params *thermal_params;
    370	enum iwl_led_mode led_mode;
    371	enum iwl_nvm_type nvm_type;
    372	u32 max_data_size;
    373	u32 max_inst_size;
    374	netdev_features_t features;
    375	u32 dccm_offset;
    376	u32 dccm_len;
    377	u32 dccm2_offset;
    378	u32 dccm2_len;
    379	u32 smem_offset;
    380	u32 smem_len;
    381	u16 nvm_ver;
    382	u16 nvm_calib_ver;
    383	u32 rx_with_siso_diversity:1,
    384	    tx_with_siso_diversity:1,
    385	    bt_shared_single_ant:1,
    386	    internal_wimax_coex:1,
    387	    host_interrupt_operation_mode:1,
    388	    high_temp:1,
    389	    mac_addr_from_csr:10,
    390	    lp_xtal_workaround:1,
    391	    disable_dummy_notification:1,
    392	    apmg_not_supported:1,
    393	    vht_mu_mimo_supported:1,
    394	    cdb:1,
    395	    dbgc_supported:1,
    396	    uhb_supported:1;
    397	u8 valid_tx_ant;
    398	u8 valid_rx_ant;
    399	u8 non_shared_ant;
    400	u8 nvm_hw_section_num;
    401	u8 max_tx_agg_size;
    402	u8 ucode_api_max;
    403	u8 ucode_api_min;
    404	u16 num_rbds;
    405	u32 min_umac_error_event_table;
    406	u32 d3_debug_data_base_addr;
    407	u32 d3_debug_data_length;
    408	u32 min_txq_size;
    409	u32 gp2_reg_addr;
    410	u32 min_ba_txq_size;
    411	const struct iwl_fw_mon_regs mon_dram_regs;
    412	const struct iwl_fw_mon_regs mon_smem_regs;
    413	const struct iwl_fw_mon_regs mon_dbgi_regs;
    414};
    415
    416#define IWL_CFG_ANY (~0)
    417
    418#define IWL_CFG_MAC_TYPE_PU		0x31
    419#define IWL_CFG_MAC_TYPE_PNJ		0x32
    420#define IWL_CFG_MAC_TYPE_TH		0x32
    421#define IWL_CFG_MAC_TYPE_QU		0x33
    422#define IWL_CFG_MAC_TYPE_QUZ		0x35
    423#define IWL_CFG_MAC_TYPE_QNJ		0x36
    424#define IWL_CFG_MAC_TYPE_SO		0x37
    425#define IWL_CFG_MAC_TYPE_SNJ		0x42
    426#define IWL_CFG_MAC_TYPE_SOF		0x43
    427#define IWL_CFG_MAC_TYPE_MA		0x44
    428#define IWL_CFG_MAC_TYPE_BZ		0x46
    429#define IWL_CFG_MAC_TYPE_GL		0x47
    430
    431#define IWL_CFG_RF_TYPE_TH		0x105
    432#define IWL_CFG_RF_TYPE_TH1		0x108
    433#define IWL_CFG_RF_TYPE_JF2		0x105
    434#define IWL_CFG_RF_TYPE_JF1		0x108
    435#define IWL_CFG_RF_TYPE_HR2		0x10A
    436#define IWL_CFG_RF_TYPE_HR1		0x10C
    437#define IWL_CFG_RF_TYPE_GF		0x10D
    438#define IWL_CFG_RF_TYPE_MR		0x110
    439#define IWL_CFG_RF_TYPE_MS		0x111
    440#define IWL_CFG_RF_TYPE_FM		0x112
    441
    442#define IWL_CFG_RF_ID_TH		0x1
    443#define IWL_CFG_RF_ID_TH1		0x1
    444#define IWL_CFG_RF_ID_JF		0x3
    445#define IWL_CFG_RF_ID_JF1		0x6
    446#define IWL_CFG_RF_ID_JF1_DIV		0xA
    447#define IWL_CFG_RF_ID_HR		0x7
    448#define IWL_CFG_RF_ID_HR1		0x4
    449
    450#define IWL_CFG_NO_160			0x1
    451#define IWL_CFG_160			0x0
    452
    453#define IWL_CFG_CORES_BT		0x0
    454#define IWL_CFG_CORES_BT_GNSS		0x5
    455
    456#define IWL_CFG_NO_CDB			0x0
    457#define IWL_CFG_CDB			0x1
    458
    459#define IWL_CFG_NO_JACKET		0x0
    460#define IWL_CFG_IS_JACKET		0x1
    461
    462#define IWL_SUBDEVICE_RF_ID(subdevice)	((u16)((subdevice) & 0x00F0) >> 4)
    463#define IWL_SUBDEVICE_NO_160(subdevice)	((u16)((subdevice) & 0x0200) >> 9)
    464#define IWL_SUBDEVICE_CORES(subdevice)	((u16)((subdevice) & 0x1C00) >> 10)
    465
    466struct iwl_dev_info {
    467	u16 device;
    468	u16 subdevice;
    469	u16 mac_type;
    470	u16 rf_type;
    471	u8 mac_step;
    472	u8 rf_id;
    473	u8 no_160;
    474	u8 cores;
    475	u8 cdb;
    476	u8 jacket;
    477	const struct iwl_cfg *cfg;
    478	const char *name;
    479};
    480
    481/*
    482 * This list declares the config structures for all devices.
    483 */
    484extern const struct iwl_cfg_trans_params iwl9000_trans_cfg;
    485extern const struct iwl_cfg_trans_params iwl9560_trans_cfg;
    486extern const struct iwl_cfg_trans_params iwl9560_long_latency_trans_cfg;
    487extern const struct iwl_cfg_trans_params iwl9560_shared_clk_trans_cfg;
    488extern const struct iwl_cfg_trans_params iwl_qnj_trans_cfg;
    489extern const struct iwl_cfg_trans_params iwl_qu_trans_cfg;
    490extern const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg;
    491extern const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg;
    492extern const struct iwl_cfg_trans_params iwl_ax200_trans_cfg;
    493extern const struct iwl_cfg_trans_params iwl_snj_trans_cfg;
    494extern const struct iwl_cfg_trans_params iwl_so_trans_cfg;
    495extern const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg;
    496extern const struct iwl_cfg_trans_params iwl_so_long_latency_imr_trans_cfg;
    497extern const struct iwl_cfg_trans_params iwl_ma_trans_cfg;
    498extern const struct iwl_cfg_trans_params iwl_bz_trans_cfg;
    499extern const char iwl9162_name[];
    500extern const char iwl9260_name[];
    501extern const char iwl9260_1_name[];
    502extern const char iwl9270_name[];
    503extern const char iwl9461_name[];
    504extern const char iwl9462_name[];
    505extern const char iwl9560_name[];
    506extern const char iwl9162_160_name[];
    507extern const char iwl9260_160_name[];
    508extern const char iwl9270_160_name[];
    509extern const char iwl9461_160_name[];
    510extern const char iwl9462_160_name[];
    511extern const char iwl9560_160_name[];
    512extern const char iwl9260_killer_1550_name[];
    513extern const char iwl9560_killer_1550i_name[];
    514extern const char iwl9560_killer_1550s_name[];
    515extern const char iwl_ax200_name[];
    516extern const char iwl_ax203_name[];
    517extern const char iwl_ax204_name[];
    518extern const char iwl_ax201_name[];
    519extern const char iwl_ax101_name[];
    520extern const char iwl_ax200_killer_1650w_name[];
    521extern const char iwl_ax200_killer_1650x_name[];
    522extern const char iwl_ax201_killer_1650s_name[];
    523extern const char iwl_ax201_killer_1650i_name[];
    524extern const char iwl_ax210_killer_1675w_name[];
    525extern const char iwl_ax210_killer_1675x_name[];
    526extern const char iwl9560_killer_1550i_160_name[];
    527extern const char iwl9560_killer_1550s_160_name[];
    528extern const char iwl_ax211_killer_1675s_name[];
    529extern const char iwl_ax211_killer_1675i_name[];
    530extern const char iwl_ax411_killer_1690s_name[];
    531extern const char iwl_ax411_killer_1690i_name[];
    532extern const char iwl_ax211_name[];
    533extern const char iwl_ax221_name[];
    534extern const char iwl_ax231_name[];
    535extern const char iwl_ax411_name[];
    536extern const char iwl_bz_name[];
    537#if IS_ENABLED(CONFIG_IWLDVM)
    538extern const struct iwl_cfg iwl5300_agn_cfg;
    539extern const struct iwl_cfg iwl5100_agn_cfg;
    540extern const struct iwl_cfg iwl5350_agn_cfg;
    541extern const struct iwl_cfg iwl5100_bgn_cfg;
    542extern const struct iwl_cfg iwl5100_abg_cfg;
    543extern const struct iwl_cfg iwl5150_agn_cfg;
    544extern const struct iwl_cfg iwl5150_abg_cfg;
    545extern const struct iwl_cfg iwl6005_2agn_cfg;
    546extern const struct iwl_cfg iwl6005_2abg_cfg;
    547extern const struct iwl_cfg iwl6005_2bg_cfg;
    548extern const struct iwl_cfg iwl6005_2agn_sff_cfg;
    549extern const struct iwl_cfg iwl6005_2agn_d_cfg;
    550extern const struct iwl_cfg iwl6005_2agn_mow1_cfg;
    551extern const struct iwl_cfg iwl6005_2agn_mow2_cfg;
    552extern const struct iwl_cfg iwl1030_bgn_cfg;
    553extern const struct iwl_cfg iwl1030_bg_cfg;
    554extern const struct iwl_cfg iwl6030_2agn_cfg;
    555extern const struct iwl_cfg iwl6030_2abg_cfg;
    556extern const struct iwl_cfg iwl6030_2bgn_cfg;
    557extern const struct iwl_cfg iwl6030_2bg_cfg;
    558extern const struct iwl_cfg iwl6000i_2agn_cfg;
    559extern const struct iwl_cfg iwl6000i_2abg_cfg;
    560extern const struct iwl_cfg iwl6000i_2bg_cfg;
    561extern const struct iwl_cfg iwl6000_3agn_cfg;
    562extern const struct iwl_cfg iwl6050_2agn_cfg;
    563extern const struct iwl_cfg iwl6050_2abg_cfg;
    564extern const struct iwl_cfg iwl6150_bgn_cfg;
    565extern const struct iwl_cfg iwl6150_bg_cfg;
    566extern const struct iwl_cfg iwl1000_bgn_cfg;
    567extern const struct iwl_cfg iwl1000_bg_cfg;
    568extern const struct iwl_cfg iwl100_bgn_cfg;
    569extern const struct iwl_cfg iwl100_bg_cfg;
    570extern const struct iwl_cfg iwl130_bgn_cfg;
    571extern const struct iwl_cfg iwl130_bg_cfg;
    572extern const struct iwl_cfg iwl2000_2bgn_cfg;
    573extern const struct iwl_cfg iwl2000_2bgn_d_cfg;
    574extern const struct iwl_cfg iwl2030_2bgn_cfg;
    575extern const struct iwl_cfg iwl6035_2agn_cfg;
    576extern const struct iwl_cfg iwl6035_2agn_sff_cfg;
    577extern const struct iwl_cfg iwl105_bgn_cfg;
    578extern const struct iwl_cfg iwl105_bgn_d_cfg;
    579extern const struct iwl_cfg iwl135_bgn_cfg;
    580#endif /* CONFIG_IWLDVM */
    581#if IS_ENABLED(CONFIG_IWLMVM)
    582extern const struct iwl_cfg iwl7260_2ac_cfg;
    583extern const struct iwl_cfg iwl7260_2ac_cfg_high_temp;
    584extern const struct iwl_cfg iwl7260_2n_cfg;
    585extern const struct iwl_cfg iwl7260_n_cfg;
    586extern const struct iwl_cfg iwl3160_2ac_cfg;
    587extern const struct iwl_cfg iwl3160_2n_cfg;
    588extern const struct iwl_cfg iwl3160_n_cfg;
    589extern const struct iwl_cfg iwl3165_2ac_cfg;
    590extern const struct iwl_cfg iwl3168_2ac_cfg;
    591extern const struct iwl_cfg iwl7265_2ac_cfg;
    592extern const struct iwl_cfg iwl7265_2n_cfg;
    593extern const struct iwl_cfg iwl7265_n_cfg;
    594extern const struct iwl_cfg iwl7265d_2ac_cfg;
    595extern const struct iwl_cfg iwl7265d_2n_cfg;
    596extern const struct iwl_cfg iwl7265d_n_cfg;
    597extern const struct iwl_cfg iwl8260_2n_cfg;
    598extern const struct iwl_cfg iwl8260_2ac_cfg;
    599extern const struct iwl_cfg iwl8265_2ac_cfg;
    600extern const struct iwl_cfg iwl8275_2ac_cfg;
    601extern const struct iwl_cfg iwl4165_2ac_cfg;
    602extern const struct iwl_cfg iwl9260_2ac_cfg;
    603extern const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg;
    604extern const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg;
    605extern const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg;
    606extern const struct iwl_cfg iwl9560_qnj_b0_jf_b0_cfg;
    607extern const struct iwl_cfg iwl9560_2ac_cfg_soc;
    608extern const struct iwl_cfg iwl_qu_b0_hr1_b0;
    609extern const struct iwl_cfg iwl_qu_c0_hr1_b0;
    610extern const struct iwl_cfg iwl_quz_a0_hr1_b0;
    611extern const struct iwl_cfg iwl_qu_b0_hr_b0;
    612extern const struct iwl_cfg iwl_qu_c0_hr_b0;
    613extern const struct iwl_cfg iwl_ax200_cfg_cc;
    614extern const struct iwl_cfg iwl_ax201_cfg_qu_hr;
    615extern const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0;
    616extern const struct iwl_cfg iwl_ax201_cfg_quz_hr;
    617extern const struct iwl_cfg iwl_ax1650i_cfg_quz_hr;
    618extern const struct iwl_cfg iwl_ax1650s_cfg_quz_hr;
    619extern const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0;
    620extern const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0;
    621extern const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0;
    622extern const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0;
    623extern const struct iwl_cfg killer1650x_2ax_cfg;
    624extern const struct iwl_cfg killer1650w_2ax_cfg;
    625extern const struct iwl_cfg iwl_qnj_b0_hr_b0_cfg;
    626extern const struct iwl_cfg iwlax210_2ax_cfg_so_jf_b0;
    627extern const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0;
    628extern const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long;
    629extern const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0;
    630extern const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0;
    631extern const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long;
    632extern const struct iwl_cfg iwlax411_2ax_cfg_sosnj_gf4_a0;
    633extern const struct iwl_cfg iwlax211_cfg_snj_gf_a0;
    634extern const struct iwl_cfg iwl_cfg_snj_hr_b0;
    635extern const struct iwl_cfg iwl_cfg_snj_a0_jf_b0;
    636extern const struct iwl_cfg iwl_cfg_ma_a0_hr_b0;
    637extern const struct iwl_cfg iwl_cfg_ma_a0_gf_a0;
    638extern const struct iwl_cfg iwl_cfg_ma_a0_gf4_a0;
    639extern const struct iwl_cfg iwl_cfg_ma_a0_mr_a0;
    640extern const struct iwl_cfg iwl_cfg_ma_a0_ms_a0;
    641extern const struct iwl_cfg iwl_cfg_ma_a0_fm_a0;
    642extern const struct iwl_cfg iwl_cfg_snj_a0_mr_a0;
    643extern const struct iwl_cfg iwl_cfg_snj_a0_ms_a0;
    644extern const struct iwl_cfg iwl_cfg_so_a0_hr_a0;
    645extern const struct iwl_cfg iwl_cfg_so_a0_ms_a0;
    646extern const struct iwl_cfg iwl_cfg_quz_a0_hr_b0;
    647extern const struct iwl_cfg iwl_cfg_bz_a0_hr_b0;
    648extern const struct iwl_cfg iwl_cfg_bz_a0_gf_a0;
    649extern const struct iwl_cfg iwl_cfg_bz_a0_gf4_a0;
    650extern const struct iwl_cfg iwl_cfg_bz_a0_mr_a0;
    651extern const struct iwl_cfg iwl_cfg_bz_a0_fm_a0;
    652extern const struct iwl_cfg iwl_cfg_gl_a0_fm_a0;
    653extern const struct iwl_cfg iwl_cfg_bz_z0_gf_a0;
    654extern const struct iwl_cfg iwl_cfg_bnj_a0_fm_a0;
    655extern const struct iwl_cfg iwl_cfg_bnj_a0_fm4_a0;
    656extern const struct iwl_cfg iwl_cfg_bnj_a0_gf_a0;
    657extern const struct iwl_cfg iwl_cfg_bnj_a0_gf4_a0;
    658extern const struct iwl_cfg iwl_cfg_bnj_a0_hr_b0;
    659#endif /* CONFIG_IWLMVM */
    660
    661#endif /* __IWL_CONFIG_H__ */