cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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decl.h (7661B)

      1/*
      2 * NXP Wireless LAN device driver: generic data structures and APIs
      3 *
      4 * Copyright 2011-2020 NXP
      5 *
      6 * This software file (the "File") is distributed by NXP
      7 * under the terms of the GNU General Public License Version 2, June 1991
      8 * (the "License").  You may use, redistribute and/or modify this File in
      9 * accordance with the terms and conditions of the License, a copy of which
     10 * is available by writing to the Free Software Foundation, Inc.,
     11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
     12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
     13 *
     14 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
     15 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
     16 * ARE EXPRESSLY DISCLAIMED.  The License provides additional details about
     17 * this warranty disclaimer.
     18 */
     19
     20#ifndef _MWIFIEX_DECL_H_
     21#define _MWIFIEX_DECL_H_
     22
     23#undef pr_fmt
     24#define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt
     25
     26#include <linux/wait.h>
     27#include <linux/timer.h>
     28#include <linux/ieee80211.h>
     29#include <uapi/linux/if_arp.h>
     30#include <net/cfg80211.h>
     31
     32#define MWIFIEX_BSS_COEX_COUNT	     2
     33#define MWIFIEX_MAX_BSS_NUM         (3)
     34
     35#define MWIFIEX_DMA_ALIGN_SZ	    64
     36#define MWIFIEX_RX_HEADROOM	    64
     37#define MAX_TXPD_SZ		    32
     38#define INTF_HDR_ALIGN		     4
     39
     40#define MWIFIEX_MIN_DATA_HEADER_LEN (MWIFIEX_DMA_ALIGN_SZ + INTF_HDR_ALIGN + \
     41				     MAX_TXPD_SZ)
     42#define MWIFIEX_MGMT_FRAME_HEADER_SIZE	8	/* sizeof(pkt_type)
     43						 *   + sizeof(tx_control)
     44						 */
     45
     46#define MWIFIEX_MAX_TX_BASTREAM_SUPPORTED	2
     47#define MWIFIEX_MAX_RX_BASTREAM_SUPPORTED	16
     48#define MWIFIEX_MAX_TDLS_PEER_SUPPORTED 8
     49
     50#define MWIFIEX_STA_AMPDU_DEF_TXWINSIZE        64
     51#define MWIFIEX_STA_AMPDU_DEF_RXWINSIZE        64
     52#define MWIFIEX_STA_COEX_AMPDU_DEF_RXWINSIZE   16
     53
     54#define MWIFIEX_UAP_AMPDU_DEF_TXWINSIZE        32
     55
     56#define MWIFIEX_UAP_COEX_AMPDU_DEF_RXWINSIZE   16
     57
     58#define MWIFIEX_UAP_AMPDU_DEF_RXWINSIZE        16
     59#define MWIFIEX_11AC_STA_AMPDU_DEF_TXWINSIZE   64
     60#define MWIFIEX_11AC_STA_AMPDU_DEF_RXWINSIZE   64
     61#define MWIFIEX_11AC_UAP_AMPDU_DEF_TXWINSIZE   64
     62#define MWIFIEX_11AC_UAP_AMPDU_DEF_RXWINSIZE   64
     63
     64#define MWIFIEX_DEFAULT_BLOCK_ACK_TIMEOUT  0xffff
     65
     66#define MWIFIEX_RATE_BITMAP_MCS0   32
     67
     68#define MWIFIEX_RX_DATA_BUF_SIZE     (4 * 1024)
     69#define MWIFIEX_RX_CMD_BUF_SIZE	     (2 * 1024)
     70
     71#define MAX_BEACON_PERIOD                  (4000)
     72#define MIN_BEACON_PERIOD                  (50)
     73#define MAX_DTIM_PERIOD                    (100)
     74#define MIN_DTIM_PERIOD                    (1)
     75
     76#define MWIFIEX_RTS_MIN_VALUE              (0)
     77#define MWIFIEX_RTS_MAX_VALUE              (2347)
     78#define MWIFIEX_FRAG_MIN_VALUE             (256)
     79#define MWIFIEX_FRAG_MAX_VALUE             (2346)
     80#define MWIFIEX_WMM_VERSION                0x01
     81#define MWIFIEX_WMM_SUBTYPE                0x01
     82
     83#define MWIFIEX_RETRY_LIMIT                14
     84#define MWIFIEX_SDIO_BLOCK_SIZE            256
     85
     86#define MWIFIEX_BUF_FLAG_REQUEUED_PKT      BIT(0)
     87#define MWIFIEX_BUF_FLAG_BRIDGED_PKT	   BIT(1)
     88#define MWIFIEX_BUF_FLAG_TDLS_PKT	   BIT(2)
     89#define MWIFIEX_BUF_FLAG_EAPOL_TX_STATUS   BIT(3)
     90#define MWIFIEX_BUF_FLAG_ACTION_TX_STATUS  BIT(4)
     91#define MWIFIEX_BUF_FLAG_AGGR_PKT          BIT(5)
     92
     93#define MWIFIEX_BRIDGED_PKTS_THR_HIGH      1024
     94#define MWIFIEX_BRIDGED_PKTS_THR_LOW        128
     95
     96#define MWIFIEX_TDLS_DISABLE_LINK             0x00
     97#define MWIFIEX_TDLS_ENABLE_LINK              0x01
     98#define MWIFIEX_TDLS_CREATE_LINK              0x02
     99#define MWIFIEX_TDLS_CONFIG_LINK              0x03
    100
    101#define MWIFIEX_TDLS_RSSI_HIGH		50
    102#define MWIFIEX_TDLS_RSSI_LOW		55
    103#define MWIFIEX_TDLS_MAX_FAIL_COUNT      4
    104#define MWIFIEX_AUTO_TDLS_IDLE_TIME     10
    105
    106/* 54M rates, index from 0 to 11 */
    107#define MWIFIEX_RATE_INDEX_MCS0 12
    108/* 12-27=MCS0-15(BW20) */
    109#define MWIFIEX_BW20_MCS_NUM 15
    110
    111/* Rate index for OFDM 0 */
    112#define MWIFIEX_RATE_INDEX_OFDM0   4
    113
    114#define MWIFIEX_MAX_STA_NUM		3
    115#define MWIFIEX_MAX_UAP_NUM		3
    116#define MWIFIEX_MAX_P2P_NUM		3
    117
    118#define MWIFIEX_A_BAND_START_FREQ	5000
    119
    120/* SDIO Aggr data packet special info */
    121#define SDIO_MAX_AGGR_BUF_SIZE		(256 * 255)
    122#define BLOCK_NUMBER_OFFSET		15
    123#define SDIO_HEADER_OFFSET		28
    124
    125#define MWIFIEX_SIZE_4K 0x4000
    126
    127enum mwifiex_bss_type {
    128	MWIFIEX_BSS_TYPE_STA = 0,
    129	MWIFIEX_BSS_TYPE_UAP = 1,
    130	MWIFIEX_BSS_TYPE_P2P = 2,
    131	MWIFIEX_BSS_TYPE_ANY = 0xff,
    132};
    133
    134enum mwifiex_bss_role {
    135	MWIFIEX_BSS_ROLE_STA = 0,
    136	MWIFIEX_BSS_ROLE_UAP = 1,
    137	MWIFIEX_BSS_ROLE_ANY = 0xff,
    138};
    139
    140enum mwifiex_tdls_status {
    141	TDLS_NOT_SETUP = 0,
    142	TDLS_SETUP_INPROGRESS,
    143	TDLS_SETUP_COMPLETE,
    144	TDLS_SETUP_FAILURE,
    145	TDLS_LINK_TEARDOWN,
    146	TDLS_CHAN_SWITCHING,
    147	TDLS_IN_BASE_CHAN,
    148	TDLS_IN_OFF_CHAN,
    149};
    150
    151enum mwifiex_tdls_error_code {
    152	TDLS_ERR_NO_ERROR = 0,
    153	TDLS_ERR_INTERNAL_ERROR,
    154	TDLS_ERR_MAX_LINKS_EST,
    155	TDLS_ERR_LINK_EXISTS,
    156	TDLS_ERR_LINK_NONEXISTENT,
    157	TDLS_ERR_PEER_STA_UNREACHABLE = 25,
    158};
    159
    160#define BSS_ROLE_BIT_MASK    BIT(0)
    161
    162#define GET_BSS_ROLE(priv)   ((priv)->bss_role & BSS_ROLE_BIT_MASK)
    163
    164enum mwifiex_data_frame_type {
    165	MWIFIEX_DATA_FRAME_TYPE_ETH_II = 0,
    166	MWIFIEX_DATA_FRAME_TYPE_802_11,
    167};
    168
    169struct mwifiex_fw_image {
    170	u8 *helper_buf;
    171	u32 helper_len;
    172	u8 *fw_buf;
    173	u32 fw_len;
    174};
    175
    176struct mwifiex_802_11_ssid {
    177	u32 ssid_len;
    178	u8 ssid[IEEE80211_MAX_SSID_LEN];
    179};
    180
    181struct mwifiex_wait_queue {
    182	wait_queue_head_t wait;
    183	int status;
    184};
    185
    186struct mwifiex_rxinfo {
    187	struct sk_buff *parent;
    188	u8 bss_num;
    189	u8 bss_type;
    190	u8 use_count;
    191	u8 buf_type;
    192};
    193
    194struct mwifiex_txinfo {
    195	u32 status_code;
    196	u8 flags;
    197	u8 bss_num;
    198	u8 bss_type;
    199	u8 aggr_num;
    200	u32 pkt_len;
    201	u8 ack_frame_id;
    202	u64 cookie;
    203};
    204
    205enum mwifiex_wmm_ac_e {
    206	WMM_AC_BK,
    207	WMM_AC_BE,
    208	WMM_AC_VI,
    209	WMM_AC_VO
    210} __packed;
    211
    212struct ieee_types_wmm_ac_parameters {
    213	u8 aci_aifsn_bitmap;
    214	u8 ecw_bitmap;
    215	__le16 tx_op_limit;
    216} __packed;
    217
    218struct mwifiex_types_wmm_info {
    219	u8 oui[4];
    220	u8 subtype;
    221	u8 version;
    222	u8 qos_info;
    223	u8 reserved;
    224	struct ieee_types_wmm_ac_parameters ac_params[IEEE80211_NUM_ACS];
    225} __packed;
    226
    227struct mwifiex_arp_eth_header {
    228	struct arphdr hdr;
    229	u8 ar_sha[ETH_ALEN];
    230	u8 ar_sip[4];
    231	u8 ar_tha[ETH_ALEN];
    232	u8 ar_tip[4];
    233} __packed;
    234
    235struct mwifiex_chan_stats {
    236	u8 chan_num;
    237	u8 bandcfg;
    238	u8 flags;
    239	s8 noise;
    240	u16 total_bss;
    241	u16 cca_scan_dur;
    242	u16 cca_busy_dur;
    243} __packed;
    244
    245#define MWIFIEX_HIST_MAX_SAMPLES	1048576
    246#define MWIFIEX_MAX_RX_RATES		     44
    247#define MWIFIEX_MAX_AC_RX_RATES		     74
    248#define MWIFIEX_MAX_SNR			    256
    249#define MWIFIEX_MAX_NOISE_FLR		    256
    250#define MWIFIEX_MAX_SIG_STRENGTH	    256
    251
    252struct mwifiex_histogram_data {
    253	atomic_t rx_rate[MWIFIEX_MAX_AC_RX_RATES];
    254	atomic_t snr[MWIFIEX_MAX_SNR];
    255	atomic_t noise_flr[MWIFIEX_MAX_NOISE_FLR];
    256	atomic_t sig_str[MWIFIEX_MAX_SIG_STRENGTH];
    257	atomic_t num_samples;
    258};
    259
    260struct mwifiex_iface_comb {
    261	u8 sta_intf;
    262	u8 uap_intf;
    263	u8 p2p_intf;
    264};
    265
    266struct mwifiex_radar_params {
    267	struct cfg80211_chan_def *chandef;
    268	u32 cac_time_ms;
    269} __packed;
    270
    271struct mwifiex_11h_intf_state {
    272	bool is_11h_enabled;
    273	bool is_11h_active;
    274} __packed;
    275
    276#define MWIFIEX_FW_DUMP_IDX		0xff
    277#define MWIFIEX_FW_DUMP_MAX_MEMSIZE     0x160000
    278#define MWIFIEX_DRV_INFO_IDX		20
    279#define FW_DUMP_MAX_NAME_LEN		8
    280#define FW_DUMP_HOST_READY      0xEE
    281#define FW_DUMP_DONE			0xFF
    282#define FW_DUMP_READ_DONE		0xFE
    283
    284struct memory_type_mapping {
    285	u8 mem_name[FW_DUMP_MAX_NAME_LEN];
    286	u8 *mem_ptr;
    287	u32 mem_size;
    288	u8 done_flag;
    289};
    290
    291enum rdwr_status {
    292	RDWR_STATUS_SUCCESS = 0,
    293	RDWR_STATUS_FAILURE = 1,
    294	RDWR_STATUS_DONE = 2
    295};
    296
    297enum mwifiex_chan_width {
    298	CHAN_BW_20MHZ = 0,
    299	CHAN_BW_10MHZ,
    300	CHAN_BW_40MHZ,
    301	CHAN_BW_80MHZ,
    302	CHAN_BW_8080MHZ,
    303	CHAN_BW_160MHZ,
    304	CHAN_BW_5MHZ,
    305};
    306
    307enum mwifiex_chan_offset {
    308	SEC_CHAN_NONE = 0,
    309	SEC_CHAN_ABOVE = 1,
    310	SEC_CHAN_5MHZ = 2,
    311	SEC_CHAN_BELOW = 3
    312};
    313
    314#endif /* !_MWIFIEX_DECL_H_ */