pci_init.c (6800B)
1// SPDX-License-Identifier: ISC 2/* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6#include <linux/delay.h> 7#include "mt76x2.h" 8#include "eeprom.h" 9#include "mcu.h" 10#include "../mt76x02_mac.h" 11 12static void 13mt76x2_mac_pbf_init(struct mt76x02_dev *dev) 14{ 15 u32 val; 16 17 val = MT_PBF_SYS_CTRL_MCU_RESET | 18 MT_PBF_SYS_CTRL_DMA_RESET | 19 MT_PBF_SYS_CTRL_MAC_RESET | 20 MT_PBF_SYS_CTRL_PBF_RESET | 21 MT_PBF_SYS_CTRL_ASY_RESET; 22 23 mt76_set(dev, MT_PBF_SYS_CTRL, val); 24 mt76_clear(dev, MT_PBF_SYS_CTRL, val); 25 26 mt76_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f); 27 mt76_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf); 28} 29 30static void 31mt76x2_fixup_xtal(struct mt76x02_dev *dev) 32{ 33 u16 eep_val; 34 s8 offset = 0; 35 36 eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_2); 37 38 offset = eep_val & 0x7f; 39 if ((eep_val & 0xff) == 0xff) 40 offset = 0; 41 else if (eep_val & 0x80) 42 offset = 0 - offset; 43 44 eep_val >>= 8; 45 if (eep_val == 0x00 || eep_val == 0xff) { 46 eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_1); 47 eep_val &= 0xff; 48 49 if (eep_val == 0x00 || eep_val == 0xff) 50 eep_val = 0x14; 51 } 52 53 eep_val &= 0x7f; 54 mt76_rmw_field(dev, MT_XO_CTRL5, MT_XO_CTRL5_C2_VAL, eep_val + offset); 55 mt76_set(dev, MT_XO_CTRL6, MT_XO_CTRL6_C2_CTRL); 56 57 eep_val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_2); 58 switch (FIELD_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, eep_val)) { 59 case 0: 60 mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80); 61 break; 62 case 1: 63 mt76_wr(dev, MT_XO_CTRL7, 0x5c1feed0); 64 break; 65 default: 66 break; 67 } 68} 69 70int mt76x2_mac_reset(struct mt76x02_dev *dev, bool hard) 71{ 72 const u8 *macaddr = dev->mphy.macaddr; 73 u32 val; 74 int i, k; 75 76 if (!mt76x02_wait_for_mac(&dev->mt76)) 77 return -ETIMEDOUT; 78 79 val = mt76_rr(dev, MT_WPDMA_GLO_CFG); 80 81 val &= ~(MT_WPDMA_GLO_CFG_TX_DMA_EN | 82 MT_WPDMA_GLO_CFG_TX_DMA_BUSY | 83 MT_WPDMA_GLO_CFG_RX_DMA_EN | 84 MT_WPDMA_GLO_CFG_RX_DMA_BUSY | 85 MT_WPDMA_GLO_CFG_DMA_BURST_SIZE); 86 val |= FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3); 87 88 mt76_wr(dev, MT_WPDMA_GLO_CFG, val); 89 90 mt76x2_mac_pbf_init(dev); 91 mt76_write_mac_initvals(dev); 92 mt76x2_fixup_xtal(dev); 93 94 mt76_clear(dev, MT_MAC_SYS_CTRL, 95 MT_MAC_SYS_CTRL_RESET_CSR | 96 MT_MAC_SYS_CTRL_RESET_BBP); 97 98 if (is_mt7612(dev)) 99 mt76_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN); 100 101 mt76_set(dev, MT_EXT_CCA_CFG, 0x0000f000); 102 mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31)); 103 104 mt76_wr(dev, MT_RF_BYPASS_0, 0x06000000); 105 mt76_wr(dev, MT_RF_SETTING_0, 0x08800000); 106 usleep_range(5000, 10000); 107 mt76_wr(dev, MT_RF_BYPASS_0, 0x00000000); 108 109 mt76_wr(dev, MT_MCU_CLOCK_CTL, 0x1401); 110 mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN); 111 112 mt76x02_mac_setaddr(dev, macaddr); 113 mt76x02e_init_beacon_config(dev); 114 if (!hard) 115 return 0; 116 117 for (i = 0; i < 256 / 32; i++) 118 mt76_wr(dev, MT_WCID_DROP_BASE + i * 4, 0); 119 120 for (i = 0; i < 256; i++) { 121 mt76x02_mac_wcid_setup(dev, i, 0, NULL); 122 mt76_wr(dev, MT_WCID_TX_RATE(i), 0); 123 mt76_wr(dev, MT_WCID_TX_RATE(i) + 4, 0); 124 } 125 126 for (i = 0; i < MT_MAX_VIFS; i++) 127 mt76x02_mac_wcid_setup(dev, MT_VIF_WCID(i), i, NULL); 128 129 for (i = 0; i < 16; i++) 130 for (k = 0; k < 4; k++) 131 mt76x02_mac_shared_key_setup(dev, i, k, NULL); 132 133 for (i = 0; i < 16; i++) 134 mt76_rr(dev, MT_TX_STAT_FIFO); 135 136 mt76x02_set_tx_ackto(dev); 137 138 return 0; 139} 140 141static void 142mt76x2_power_on_rf_patch(struct mt76x02_dev *dev) 143{ 144 mt76_set(dev, 0x10130, BIT(0) | BIT(16)); 145 udelay(1); 146 147 mt76_clear(dev, 0x1001c, 0xff); 148 mt76_set(dev, 0x1001c, 0x30); 149 150 mt76_wr(dev, 0x10014, 0x484f); 151 udelay(1); 152 153 mt76_set(dev, 0x10130, BIT(17)); 154 udelay(125); 155 156 mt76_clear(dev, 0x10130, BIT(16)); 157 udelay(50); 158 159 mt76_set(dev, 0x1014c, BIT(19) | BIT(20)); 160} 161 162static void 163mt76x2_power_on_rf(struct mt76x02_dev *dev, int unit) 164{ 165 int shift = unit ? 8 : 0; 166 167 /* Enable RF BG */ 168 mt76_set(dev, 0x10130, BIT(0) << shift); 169 udelay(10); 170 171 /* Enable RFDIG LDO/AFE/ABB/ADDA */ 172 mt76_set(dev, 0x10130, (BIT(1) | BIT(3) | BIT(4) | BIT(5)) << shift); 173 udelay(10); 174 175 /* Switch RFDIG power to internal LDO */ 176 mt76_clear(dev, 0x10130, BIT(2) << shift); 177 udelay(10); 178 179 mt76x2_power_on_rf_patch(dev); 180 181 mt76_set(dev, 0x530, 0xf); 182} 183 184static void 185mt76x2_power_on(struct mt76x02_dev *dev) 186{ 187 u32 val; 188 189 /* Turn on WL MTCMOS */ 190 mt76_set(dev, MT_WLAN_MTC_CTRL, MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP); 191 192 val = MT_WLAN_MTC_CTRL_STATE_UP | 193 MT_WLAN_MTC_CTRL_PWR_ACK | 194 MT_WLAN_MTC_CTRL_PWR_ACK_S; 195 196 mt76_poll(dev, MT_WLAN_MTC_CTRL, val, val, 1000); 197 198 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0x7f << 16); 199 udelay(10); 200 201 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xf << 24); 202 udelay(10); 203 204 mt76_set(dev, MT_WLAN_MTC_CTRL, 0xf << 24); 205 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xfff); 206 207 /* Turn on AD/DA power down */ 208 mt76_clear(dev, 0x11204, BIT(3)); 209 210 /* WLAN function enable */ 211 mt76_set(dev, 0x10080, BIT(0)); 212 213 /* Release BBP software reset */ 214 mt76_clear(dev, 0x10064, BIT(18)); 215 216 mt76x2_power_on_rf(dev, 0); 217 mt76x2_power_on_rf(dev, 1); 218} 219 220int mt76x2_resume_device(struct mt76x02_dev *dev) 221{ 222 int err; 223 224 mt76x02_dma_disable(dev); 225 mt76x2_reset_wlan(dev, true); 226 mt76x2_power_on(dev); 227 228 err = mt76x2_mac_reset(dev, true); 229 if (err) 230 return err; 231 232 mt76x02_mac_start(dev); 233 234 return mt76x2_mcu_init(dev); 235} 236 237static int mt76x2_init_hardware(struct mt76x02_dev *dev) 238{ 239 int ret; 240 241 mt76x02_dma_disable(dev); 242 mt76x2_reset_wlan(dev, true); 243 mt76x2_power_on(dev); 244 245 ret = mt76x2_eeprom_init(dev); 246 if (ret) 247 return ret; 248 249 ret = mt76x2_mac_reset(dev, true); 250 if (ret) 251 return ret; 252 253 dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG); 254 255 ret = mt76x02_dma_init(dev); 256 if (ret) 257 return ret; 258 259 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); 260 mt76x02_mac_start(dev); 261 262 ret = mt76x2_mcu_init(dev); 263 if (ret) 264 return ret; 265 266 mt76x2_mac_stop(dev, false); 267 268 return 0; 269} 270 271void mt76x2_stop_hardware(struct mt76x02_dev *dev) 272{ 273 cancel_delayed_work_sync(&dev->cal_work); 274 cancel_delayed_work_sync(&dev->mphy.mac_work); 275 cancel_delayed_work_sync(&dev->wdt_work); 276 clear_bit(MT76_RESTART, &dev->mphy.state); 277 mt76x02_mcu_set_radio_state(dev, false); 278 mt76x2_mac_stop(dev, false); 279} 280 281void mt76x2_cleanup(struct mt76x02_dev *dev) 282{ 283 tasklet_disable(&dev->dfs_pd.dfs_tasklet); 284 tasklet_disable(&dev->mt76.pre_tbtt_tasklet); 285 mt76x2_stop_hardware(dev); 286 mt76_dma_cleanup(&dev->mt76); 287 mt76x02_mcu_cleanup(dev); 288} 289 290int mt76x2_register_device(struct mt76x02_dev *dev) 291{ 292 int ret; 293 294 INIT_DELAYED_WORK(&dev->cal_work, mt76x2_phy_calibrate); 295 ret = mt76x02_init_device(dev); 296 if (ret) 297 return ret; 298 299 ret = mt76x2_init_hardware(dev); 300 if (ret) 301 return ret; 302 303 mt76x02_config_mac_addr_list(dev); 304 305 ret = mt76_register_device(&dev->mt76, true, mt76x02_rates, 306 ARRAY_SIZE(mt76x02_rates)); 307 if (ret) 308 goto fail; 309 310 mt76x02_init_debugfs(dev); 311 mt76x2_init_txpower(dev, &dev->mphy.sband_2g.sband); 312 mt76x2_init_txpower(dev, &dev->mphy.sband_5g.sband); 313 314 return 0; 315 316fail: 317 mt76x2_stop_hardware(dev); 318 return ret; 319} 320