initvals.h (4922B)
1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * (c) Copyright 2002-2010, Ralink Technology, Inc. 4 * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl> 5 */ 6 7#ifndef __MT7601U_INITVALS_H 8#define __MT7601U_INITVALS_H 9 10static const struct mt76_reg_pair bbp_common_vals[] = { 11 { 65, 0x2c }, 12 { 66, 0x38 }, 13 { 68, 0x0b }, 14 { 69, 0x12 }, 15 { 70, 0x0a }, 16 { 73, 0x10 }, 17 { 81, 0x37 }, 18 { 82, 0x62 }, 19 { 83, 0x6a }, 20 { 84, 0x99 }, 21 { 86, 0x00 }, 22 { 91, 0x04 }, 23 { 92, 0x00 }, 24 { 103, 0x00 }, 25 { 105, 0x05 }, 26 { 106, 0x35 }, 27}; 28 29static const struct mt76_reg_pair bbp_chip_vals[] = { 30 { 1, 0x04 }, { 4, 0x40 }, { 20, 0x06 }, { 31, 0x08 }, 31 /* CCK Tx Control */ 32 { 178, 0xff }, 33 /* AGC/Sync controls */ 34 { 66, 0x14 }, { 68, 0x8b }, { 69, 0x12 }, { 70, 0x09 }, 35 { 73, 0x11 }, { 75, 0x60 }, { 76, 0x44 }, { 84, 0x9a }, 36 { 86, 0x38 }, { 91, 0x07 }, { 92, 0x02 }, 37 /* Rx Path Controls */ 38 { 99, 0x50 }, { 101, 0x00 }, { 103, 0xc0 }, { 104, 0x92 }, 39 { 105, 0x3c }, { 106, 0x03 }, { 128, 0x12 }, 40 /* Change RXWI content: Gain Report */ 41 { 142, 0x04 }, { 143, 0x37 }, 42 /* Change RXWI content: Antenna Report */ 43 { 142, 0x03 }, { 143, 0x99 }, 44 /* Calibration Index Register */ 45 /* CCK Receiver Control */ 46 { 160, 0xeb }, { 161, 0xc4 }, { 162, 0x77 }, { 163, 0xf9 }, 47 { 164, 0x88 }, { 165, 0x80 }, { 166, 0xff }, { 167, 0xe4 }, 48 /* Added AGC controls - these AGC/GLRT registers are accessed 49 * through R195 and R196. 50 */ 51 { 195, 0x00 }, { 196, 0x00 }, 52 { 195, 0x01 }, { 196, 0x04 }, 53 { 195, 0x02 }, { 196, 0x20 }, 54 { 195, 0x03 }, { 196, 0x0a }, 55 { 195, 0x06 }, { 196, 0x16 }, 56 { 195, 0x07 }, { 196, 0x05 }, 57 { 195, 0x08 }, { 196, 0x37 }, 58 { 195, 0x0a }, { 196, 0x15 }, 59 { 195, 0x0b }, { 196, 0x17 }, 60 { 195, 0x0c }, { 196, 0x06 }, 61 { 195, 0x0d }, { 196, 0x09 }, 62 { 195, 0x0e }, { 196, 0x05 }, 63 { 195, 0x0f }, { 196, 0x09 }, 64 { 195, 0x10 }, { 196, 0x20 }, 65 { 195, 0x20 }, { 196, 0x17 }, 66 { 195, 0x21 }, { 196, 0x06 }, 67 { 195, 0x22 }, { 196, 0x09 }, 68 { 195, 0x23 }, { 196, 0x17 }, 69 { 195, 0x24 }, { 196, 0x06 }, 70 { 195, 0x25 }, { 196, 0x09 }, 71 { 195, 0x26 }, { 196, 0x17 }, 72 { 195, 0x27 }, { 196, 0x06 }, 73 { 195, 0x28 }, { 196, 0x09 }, 74 { 195, 0x29 }, { 196, 0x05 }, 75 { 195, 0x2a }, { 196, 0x09 }, 76 { 195, 0x80 }, { 196, 0x8b }, 77 { 195, 0x81 }, { 196, 0x12 }, 78 { 195, 0x82 }, { 196, 0x09 }, 79 { 195, 0x83 }, { 196, 0x17 }, 80 { 195, 0x84 }, { 196, 0x11 }, 81 { 195, 0x85 }, { 196, 0x00 }, 82 { 195, 0x86 }, { 196, 0x00 }, 83 { 195, 0x87 }, { 196, 0x18 }, 84 { 195, 0x88 }, { 196, 0x60 }, 85 { 195, 0x89 }, { 196, 0x44 }, 86 { 195, 0x8a }, { 196, 0x8b }, 87 { 195, 0x8b }, { 196, 0x8b }, 88 { 195, 0x8c }, { 196, 0x8b }, 89 { 195, 0x8d }, { 196, 0x8b }, 90 { 195, 0x8e }, { 196, 0x09 }, 91 { 195, 0x8f }, { 196, 0x09 }, 92 { 195, 0x90 }, { 196, 0x09 }, 93 { 195, 0x91 }, { 196, 0x09 }, 94 { 195, 0x92 }, { 196, 0x11 }, 95 { 195, 0x93 }, { 196, 0x11 }, 96 { 195, 0x94 }, { 196, 0x11 }, 97 { 195, 0x95 }, { 196, 0x11 }, 98 /* PPAD */ 99 { 47, 0x80 }, { 60, 0x80 }, { 150, 0xd2 }, { 151, 0x32 }, 100 { 152, 0x23 }, { 153, 0x41 }, { 154, 0x00 }, { 155, 0x4f }, 101 { 253, 0x7e }, { 195, 0x30 }, { 196, 0x32 }, { 195, 0x31 }, 102 { 196, 0x23 }, { 195, 0x32 }, { 196, 0x45 }, { 195, 0x35 }, 103 { 196, 0x4a }, { 195, 0x36 }, { 196, 0x5a }, { 195, 0x37 }, 104 { 196, 0x5a }, 105}; 106 107static const struct mt76_reg_pair mac_common_vals[] = { 108 { MT_LEGACY_BASIC_RATE, 0x0000013f }, 109 { MT_HT_BASIC_RATE, 0x00008003 }, 110 { MT_MAC_SYS_CTRL, 0x00000000 }, 111 { MT_RX_FILTR_CFG, 0x00017f97 }, 112 { MT_BKOFF_SLOT_CFG, 0x00000209 }, 113 { MT_TX_SW_CFG0, 0x00000000 }, 114 { MT_TX_SW_CFG1, 0x00080606 }, 115 { MT_TX_LINK_CFG, 0x00001020 }, 116 { MT_TX_TIMEOUT_CFG, 0x000a2090 }, 117 { MT_MAX_LEN_CFG, 0x00003fff }, 118 { MT_PBF_TX_MAX_PCNT, 0x1fbf1f1f }, 119 { MT_PBF_RX_MAX_PCNT, 0x0000009f }, 120 { MT_TX_RETRY_CFG, 0x47d01f0f }, 121 { MT_AUTO_RSP_CFG, 0x00000013 }, 122 { MT_CCK_PROT_CFG, 0x05740003 }, 123 { MT_OFDM_PROT_CFG, 0x05740003 }, 124 { MT_MM40_PROT_CFG, 0x03f44084 }, 125 { MT_GF20_PROT_CFG, 0x01744004 }, 126 { MT_GF40_PROT_CFG, 0x03f44084 }, 127 { MT_MM20_PROT_CFG, 0x01744004 }, 128 { MT_TXOP_CTRL_CFG, 0x0000583f }, 129 { MT_TX_RTS_CFG, 0x01092b20 }, 130 { MT_EXP_ACK_TIME, 0x002400ca }, 131 { MT_TXOP_HLDR_ET, 0x00000002 }, 132 { MT_XIFS_TIME_CFG, 0x33a41010 }, 133 { MT_PWR_PIN_CFG, 0x00000000 }, 134 { MT_PN_PAD_MODE, 0x00000001 }, 135}; 136 137static const struct mt76_reg_pair mac_chip_vals[] = { 138 { MT_TSO_CTRL, 0x00006050 }, 139 { MT_BCN_OFFSET(0), 0x18100800 }, 140 { MT_BCN_OFFSET(1), 0x38302820 }, 141 { MT_PBF_SYS_CTRL, 0x00080c00 }, 142 { MT_PBF_CFG, 0x7f723c1f }, 143 { MT_FCE_PSE_CTRL, 0x00000001 }, 144 { MT_PAUSE_ENABLE_CONTROL1, 0x00000000 }, 145 { MT_TX0_RF_GAIN_CORR, 0x003b0005 }, 146 { MT_TX0_RF_GAIN_ATTEN, 0x00006900 }, 147 { MT_TX0_BB_GAIN_ATTEN, 0x00000400 }, 148 { MT_TX_ALC_VGA3, 0x00060006 }, 149 { MT_TX_SW_CFG0, 0x00000402 }, 150 { MT_TX_SW_CFG1, 0x00000000 }, 151 { MT_TX_SW_CFG2, 0x00000000 }, 152 { MT_HEADER_TRANS_CTRL_REG, 0x00000000 }, 153 { MT_FCE_CSO, 0x0000030f }, 154 { MT_FCE_PARAMETERS, 0x00256f0f }, 155}; 156 157#endif