cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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initvals_phy.h (7472B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * (c) Copyright 2002-2010, Ralink Technology, Inc.
      4 * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
      5 */
      6
      7#ifndef __MT7601U_PHY_INITVALS_H
      8#define __MT7601U_PHY_INITVALS_H
      9
     10#define RF_REG_PAIR(bank, reg, value)				\
     11	{ MT_MCU_MEMMAP_RF | (bank) << 16 | (reg), value }
     12
     13static const struct mt76_reg_pair rf_central[] = {
     14	/* Bank 0 - for central blocks: BG, PLL, XTAL, LO, ADC/DAC */
     15	RF_REG_PAIR(0,	 0, 0x02),
     16	RF_REG_PAIR(0,	 1, 0x01),
     17	RF_REG_PAIR(0,	 2, 0x11),
     18	RF_REG_PAIR(0,	 3, 0xff),
     19	RF_REG_PAIR(0,	 4, 0x0a),
     20	RF_REG_PAIR(0,	 5, 0x20),
     21	RF_REG_PAIR(0,	 6, 0x00),
     22	/* B/G */
     23	RF_REG_PAIR(0,	 7, 0x00),
     24	RF_REG_PAIR(0,	 8, 0x00),
     25	RF_REG_PAIR(0,	 9, 0x00),
     26	RF_REG_PAIR(0,	10, 0x00),
     27	RF_REG_PAIR(0,	11, 0x21),
     28	/* XO */
     29	RF_REG_PAIR(0,	13, 0x00),		/* 40mhz xtal */
     30	/* RF_REG_PAIR(0,	13, 0x13), */	/* 20mhz xtal */
     31	RF_REG_PAIR(0,	14, 0x7c),
     32	RF_REG_PAIR(0,	15, 0x22),
     33	RF_REG_PAIR(0,	16, 0x80),
     34	/* PLL */
     35	RF_REG_PAIR(0,	17, 0x99),
     36	RF_REG_PAIR(0,	18, 0x99),
     37	RF_REG_PAIR(0,	19, 0x09),
     38	RF_REG_PAIR(0,	20, 0x50),
     39	RF_REG_PAIR(0,	21, 0xb0),
     40	RF_REG_PAIR(0,	22, 0x00),
     41	RF_REG_PAIR(0,	23, 0xc5),
     42	RF_REG_PAIR(0,	24, 0xfc),
     43	RF_REG_PAIR(0,	25, 0x40),
     44	RF_REG_PAIR(0,	26, 0x4d),
     45	RF_REG_PAIR(0,	27, 0x02),
     46	RF_REG_PAIR(0,	28, 0x72),
     47	RF_REG_PAIR(0,	29, 0x01),
     48	RF_REG_PAIR(0,	30, 0x00),
     49	RF_REG_PAIR(0,	31, 0x00),
     50	/* test ports */
     51	RF_REG_PAIR(0,	32, 0x00),
     52	RF_REG_PAIR(0,	33, 0x00),
     53	RF_REG_PAIR(0,	34, 0x23),
     54	RF_REG_PAIR(0,	35, 0x01), /* change setting to reduce spurs */
     55	RF_REG_PAIR(0,	36, 0x00),
     56	RF_REG_PAIR(0,	37, 0x00),
     57	/* ADC/DAC */
     58	RF_REG_PAIR(0,	38, 0x00),
     59	RF_REG_PAIR(0,	39, 0x20),
     60	RF_REG_PAIR(0,	40, 0x00),
     61	RF_REG_PAIR(0,	41, 0xd0),
     62	RF_REG_PAIR(0,	42, 0x1b),
     63	RF_REG_PAIR(0,	43, 0x02),
     64	RF_REG_PAIR(0,	44, 0x00),
     65};
     66
     67static const struct mt76_reg_pair rf_channel[] = {
     68	RF_REG_PAIR(4,	 0, 0x01),
     69	RF_REG_PAIR(4,	 1, 0x00),
     70	RF_REG_PAIR(4,	 2, 0x00),
     71	RF_REG_PAIR(4,	 3, 0x00),
     72	/* LDO */
     73	RF_REG_PAIR(4,	 4, 0x00),
     74	RF_REG_PAIR(4,	 5, 0x08),
     75	RF_REG_PAIR(4,	 6, 0x00),
     76	/* RX */
     77	RF_REG_PAIR(4,	 7, 0x5b),
     78	RF_REG_PAIR(4,	 8, 0x52),
     79	RF_REG_PAIR(4,	 9, 0xb6),
     80	RF_REG_PAIR(4,	10, 0x57),
     81	RF_REG_PAIR(4,	11, 0x33),
     82	RF_REG_PAIR(4,	12, 0x22),
     83	RF_REG_PAIR(4,	13, 0x3d),
     84	RF_REG_PAIR(4,	14, 0x3e),
     85	RF_REG_PAIR(4,	15, 0x13),
     86	RF_REG_PAIR(4,	16, 0x22),
     87	RF_REG_PAIR(4,	17, 0x23),
     88	RF_REG_PAIR(4,	18, 0x02),
     89	RF_REG_PAIR(4,	19, 0xa4),
     90	RF_REG_PAIR(4,	20, 0x01),
     91	RF_REG_PAIR(4,	21, 0x12),
     92	RF_REG_PAIR(4,	22, 0x80),
     93	RF_REG_PAIR(4,	23, 0xb3),
     94	RF_REG_PAIR(4,	24, 0x00), /* reserved */
     95	RF_REG_PAIR(4,	25, 0x00), /* reserved */
     96	RF_REG_PAIR(4,	26, 0x00), /* reserved */
     97	RF_REG_PAIR(4,	27, 0x00), /* reserved */
     98	/* LOGEN */
     99	RF_REG_PAIR(4,	28, 0x18),
    100	RF_REG_PAIR(4,	29, 0xee),
    101	RF_REG_PAIR(4,	30, 0x6b),
    102	RF_REG_PAIR(4,	31, 0x31),
    103	RF_REG_PAIR(4,	32, 0x5d),
    104	RF_REG_PAIR(4,	33, 0x00), /* reserved */
    105	/* TX */
    106	RF_REG_PAIR(4,	34, 0x96),
    107	RF_REG_PAIR(4,	35, 0x55),
    108	RF_REG_PAIR(4,	36, 0x08),
    109	RF_REG_PAIR(4,	37, 0xbb),
    110	RF_REG_PAIR(4,	38, 0xb3),
    111	RF_REG_PAIR(4,	39, 0xb3),
    112	RF_REG_PAIR(4,	40, 0x03),
    113	RF_REG_PAIR(4,	41, 0x00), /* reserved */
    114	RF_REG_PAIR(4,	42, 0x00), /* reserved */
    115	RF_REG_PAIR(4,	43, 0xc5),
    116	RF_REG_PAIR(4,	44, 0xc5),
    117	RF_REG_PAIR(4,	45, 0xc5),
    118	RF_REG_PAIR(4,	46, 0x07),
    119	RF_REG_PAIR(4,	47, 0xa8),
    120	RF_REG_PAIR(4,	48, 0xef),
    121	RF_REG_PAIR(4,	49, 0x1a),
    122	/* PA */
    123	RF_REG_PAIR(4,	54, 0x07),
    124	RF_REG_PAIR(4,	55, 0xa7),
    125	RF_REG_PAIR(4,	56, 0xcc),
    126	RF_REG_PAIR(4,	57, 0x14),
    127	RF_REG_PAIR(4,	58, 0x07),
    128	RF_REG_PAIR(4,	59, 0xa8),
    129	RF_REG_PAIR(4,	60, 0xd7),
    130	RF_REG_PAIR(4,	61, 0x10),
    131	RF_REG_PAIR(4,	62, 0x1c),
    132	RF_REG_PAIR(4,	63, 0x00), /* reserved */
    133};
    134
    135static const struct mt76_reg_pair rf_vga[] = {
    136	RF_REG_PAIR(5,	 0, 0x47),
    137	RF_REG_PAIR(5,	 1, 0x00),
    138	RF_REG_PAIR(5,	 2, 0x00),
    139	RF_REG_PAIR(5,	 3, 0x08),
    140	RF_REG_PAIR(5,	 4, 0x04),
    141	RF_REG_PAIR(5,	 5, 0x20),
    142	RF_REG_PAIR(5,	 6, 0x3a),
    143	RF_REG_PAIR(5,	 7, 0x3a),
    144	RF_REG_PAIR(5,	 8, 0x00),
    145	RF_REG_PAIR(5,	 9, 0x00),
    146	RF_REG_PAIR(5,	10, 0x10),
    147	RF_REG_PAIR(5,	11, 0x10),
    148	RF_REG_PAIR(5,	12, 0x10),
    149	RF_REG_PAIR(5,	13, 0x10),
    150	RF_REG_PAIR(5,	14, 0x10),
    151	RF_REG_PAIR(5,	15, 0x20),
    152	RF_REG_PAIR(5,	16, 0x22),
    153	RF_REG_PAIR(5,	17, 0x7c),
    154	RF_REG_PAIR(5,	18, 0x00),
    155	RF_REG_PAIR(5,	19, 0x00),
    156	RF_REG_PAIR(5,	20, 0x00),
    157	RF_REG_PAIR(5,	21, 0xf1),
    158	RF_REG_PAIR(5,	22, 0x11),
    159	RF_REG_PAIR(5,	23, 0x02),
    160	RF_REG_PAIR(5,	24, 0x41),
    161	RF_REG_PAIR(5,	25, 0x20),
    162	RF_REG_PAIR(5,	26, 0x00),
    163	RF_REG_PAIR(5,	27, 0xd7),
    164	RF_REG_PAIR(5,	28, 0xa2),
    165	RF_REG_PAIR(5,	29, 0x20),
    166	RF_REG_PAIR(5,	30, 0x49),
    167	RF_REG_PAIR(5,	31, 0x20),
    168	RF_REG_PAIR(5,	32, 0x04),
    169	RF_REG_PAIR(5,	33, 0xf1),
    170	RF_REG_PAIR(5,	34, 0xa1),
    171	RF_REG_PAIR(5,	35, 0x01),
    172	RF_REG_PAIR(5,	41, 0x00),
    173	RF_REG_PAIR(5,	42, 0x00),
    174	RF_REG_PAIR(5,	43, 0x00),
    175	RF_REG_PAIR(5,	44, 0x00),
    176	RF_REG_PAIR(5,	45, 0x00),
    177	RF_REG_PAIR(5,	46, 0x00),
    178	RF_REG_PAIR(5,	47, 0x00),
    179	RF_REG_PAIR(5,	48, 0x00),
    180	RF_REG_PAIR(5,	49, 0x00),
    181	RF_REG_PAIR(5,	50, 0x00),
    182	RF_REG_PAIR(5,	51, 0x00),
    183	RF_REG_PAIR(5,	52, 0x00),
    184	RF_REG_PAIR(5,	53, 0x00),
    185	RF_REG_PAIR(5,	54, 0x00),
    186	RF_REG_PAIR(5,	55, 0x00),
    187	RF_REG_PAIR(5,	56, 0x00),
    188	RF_REG_PAIR(5,	57, 0x00),
    189	RF_REG_PAIR(5,	58, 0x31),
    190	RF_REG_PAIR(5,	59, 0x31),
    191	RF_REG_PAIR(5,	60, 0x0a),
    192	RF_REG_PAIR(5,	61, 0x02),
    193	RF_REG_PAIR(5,	62, 0x00),
    194	RF_REG_PAIR(5,	63, 0x00),
    195};
    196
    197/* TODO: BBP178 is set to 0xff for "CCK CH14 OBW" which overrides the settings
    198 *	 from channel switching. Seems stupid at best.
    199 */
    200static const struct mt76_reg_pair bbp_high_temp[] = {
    201	{  75, 0x60 },
    202	{  92, 0x02 },
    203	{ 178, 0xff }, /* For CCK CH14 OBW */
    204	{ 195, 0x88 }, { 196, 0x60 },
    205}, bbp_high_temp_bw20[] = {
    206	{  69, 0x12 },
    207	{  91, 0x07 },
    208	{ 195, 0x23 }, { 196, 0x17 },
    209	{ 195, 0x24 }, { 196, 0x06 },
    210	{ 195, 0x81 }, { 196, 0x12 },
    211	{ 195, 0x83 }, { 196, 0x17 },
    212}, bbp_high_temp_bw40[] = {
    213	{  69, 0x15 },
    214	{  91, 0x04 },
    215	{ 195, 0x23 }, { 196, 0x12 },
    216	{ 195, 0x24 }, { 196, 0x08 },
    217	{ 195, 0x81 }, { 196, 0x15 },
    218	{ 195, 0x83 }, { 196, 0x16 },
    219}, bbp_low_temp[] = {
    220	{ 178, 0xff }, /* For CCK CH14 OBW */
    221}, bbp_low_temp_bw20[] = {
    222	{  69, 0x12 },
    223	{  75, 0x5e },
    224	{  91, 0x07 },
    225	{  92, 0x02 },
    226	{ 195, 0x23 }, { 196, 0x17 },
    227	{ 195, 0x24 }, { 196, 0x06 },
    228	{ 195, 0x81 }, { 196, 0x12 },
    229	{ 195, 0x83 }, { 196, 0x17 },
    230	{ 195, 0x88 }, { 196, 0x5e },
    231}, bbp_low_temp_bw40[] = {
    232	{  69, 0x15 },
    233	{  75, 0x5c },
    234	{  91, 0x04 },
    235	{  92, 0x03 },
    236	{ 195, 0x23 }, { 196, 0x10 },
    237	{ 195, 0x24 }, { 196, 0x08 },
    238	{ 195, 0x81 }, { 196, 0x15 },
    239	{ 195, 0x83 }, { 196, 0x16 },
    240	{ 195, 0x88 }, { 196, 0x5b },
    241}, bbp_normal_temp[] = {
    242	{  75, 0x60 },
    243	{  92, 0x02 },
    244	{ 178, 0xff }, /* For CCK CH14 OBW */
    245	{ 195, 0x88 }, { 196, 0x60 },
    246}, bbp_normal_temp_bw20[] = {
    247	{  69, 0x12 },
    248	{  91, 0x07 },
    249	{ 195, 0x23 }, { 196, 0x17 },
    250	{ 195, 0x24 }, { 196, 0x06 },
    251	{ 195, 0x81 }, { 196, 0x12 },
    252	{ 195, 0x83 }, { 196, 0x17 },
    253}, bbp_normal_temp_bw40[] = {
    254	{  69, 0x15 },
    255	{  91, 0x04 },
    256	{ 195, 0x23 }, { 196, 0x12 },
    257	{ 195, 0x24 }, { 196, 0x08 },
    258	{ 195, 0x81 }, { 196, 0x15 },
    259	{ 195, 0x83 }, { 196, 0x16 },
    260};
    261
    262#define BBP_TABLE(arr) { arr, ARRAY_SIZE(arr), }
    263
    264static const struct reg_table {
    265	const struct mt76_reg_pair *regs;
    266	size_t n;
    267} bbp_mode_table[3][3] = {
    268	{
    269		BBP_TABLE(bbp_normal_temp_bw20),
    270		BBP_TABLE(bbp_normal_temp_bw40),
    271		BBP_TABLE(bbp_normal_temp),
    272	}, {
    273		BBP_TABLE(bbp_high_temp_bw20),
    274		BBP_TABLE(bbp_high_temp_bw40),
    275		BBP_TABLE(bbp_high_temp),
    276	}, {
    277		BBP_TABLE(bbp_low_temp_bw20),
    278		BBP_TABLE(bbp_low_temp_bw40),
    279		BBP_TABLE(bbp_low_temp),
    280	}
    281};
    282
    283#endif