cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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intf.h (1243B)


      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * Copyright (c) 2021 pureLiFi
      4 */
      5
      6#define PURELIFI_BYTE_NUM_ALIGNMENT 4
      7#define ETH_ALEN 6
      8#define AP_USER_LIMIT 8
      9
     10#define PLF_VNDR_FPGA_STATE_REQ 0x30
     11#define PLF_VNDR_FPGA_SET_REQ 0x33
     12#define PLF_VNDR_FPGA_SET_CMD 0x34
     13#define PLF_VNDR_FPGA_STATE_CMD 0x35
     14
     15#define PLF_VNDR_XL_FW_CMD 0x80
     16#define PLF_VNDR_XL_DATA_CMD 0x81
     17#define PLF_VNDR_XL_FILE_CMD 0x82
     18#define PLF_VNDR_XL_EX_CMD 0x83
     19
     20#define PLF_MAC_VENDOR_REQUEST 0x36
     21#define PLF_SERIAL_NUMBER_VENDOR_REQUEST 0x37
     22#define PLF_FIRMWARE_VERSION_VENDOR_REQUEST 0x39
     23#define PLF_SERIAL_LEN 14
     24#define PLF_FW_VER_LEN 8
     25
     26struct rx_status {
     27	__be16 rssi;
     28	u8     rate_idx;
     29	u8     pad;
     30	__be64 crc_error_count;
     31} __packed;
     32
     33enum plf_usb_req_enum {
     34	USB_REQ_TEST_WR            = 0,
     35	USB_REQ_MAC_WR             = 1,
     36	USB_REQ_POWER_WR           = 2,
     37	USB_REQ_RXTX_WR            = 3,
     38	USB_REQ_BEACON_WR          = 4,
     39	USB_REQ_BEACON_INTERVAL_WR = 5,
     40	USB_REQ_RTS_CTS_RATE_WR    = 6,
     41	USB_REQ_HASH_WR            = 7,
     42	USB_REQ_DATA_TX            = 8,
     43	USB_REQ_RATE_WR            = 9,
     44	USB_REQ_SET_FREQ           = 15
     45};
     46
     47struct plf_usb_req {
     48	__be32         id; /* should be plf_usb_req_enum */
     49	__be32	       len;
     50	u8             buf[512];
     51};
     52