rt2800pci.c (13248B)
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com> 4 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> 5 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> 6 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> 7 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> 8 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> 9 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> 10 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com> 11 <http://rt2x00.serialmonkey.com> 12 13 */ 14 15/* 16 Module: rt2800pci 17 Abstract: rt2800pci device specific routines. 18 Supported chipsets: RT2800E & RT2800ED. 19 */ 20 21#include <linux/delay.h> 22#include <linux/etherdevice.h> 23#include <linux/init.h> 24#include <linux/kernel.h> 25#include <linux/module.h> 26#include <linux/pci.h> 27#include <linux/eeprom_93cx6.h> 28 29#include "rt2x00.h" 30#include "rt2x00mmio.h" 31#include "rt2x00pci.h" 32#include "rt2800lib.h" 33#include "rt2800mmio.h" 34#include "rt2800.h" 35#include "rt2800pci.h" 36 37/* 38 * Allow hardware encryption to be disabled. 39 */ 40static bool modparam_nohwcrypt = false; 41module_param_named(nohwcrypt, modparam_nohwcrypt, bool, 0444); 42MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 43 44static bool rt2800pci_hwcrypt_disabled(struct rt2x00_dev *rt2x00dev) 45{ 46 return modparam_nohwcrypt; 47} 48 49static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token) 50{ 51 unsigned int i; 52 u32 reg; 53 54 /* 55 * SOC devices don't support MCU requests. 56 */ 57 if (rt2x00_is_soc(rt2x00dev)) 58 return; 59 60 for (i = 0; i < 200; i++) { 61 reg = rt2x00mmio_register_read(rt2x00dev, H2M_MAILBOX_CID); 62 63 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) || 64 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) || 65 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) || 66 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token)) 67 break; 68 69 udelay(REGISTER_BUSY_DELAY); 70 } 71 72 if (i == 200) 73 rt2x00_err(rt2x00dev, "MCU request failed, no response from hardware\n"); 74 75 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0); 76 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0); 77} 78 79static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom) 80{ 81 struct rt2x00_dev *rt2x00dev = eeprom->data; 82 u32 reg; 83 84 reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR); 85 86 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN); 87 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT); 88 eeprom->reg_data_clock = 89 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK); 90 eeprom->reg_chip_select = 91 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT); 92} 93 94static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom) 95{ 96 struct rt2x00_dev *rt2x00dev = eeprom->data; 97 u32 reg = 0; 98 99 rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in); 100 rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out); 101 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, 102 !!eeprom->reg_data_clock); 103 rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT, 104 !!eeprom->reg_chip_select); 105 106 rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg); 107} 108 109static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev) 110{ 111 struct eeprom_93cx6 eeprom; 112 u32 reg; 113 114 reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR); 115 116 eeprom.data = rt2x00dev; 117 eeprom.register_read = rt2800pci_eepromregister_read; 118 eeprom.register_write = rt2800pci_eepromregister_write; 119 switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE)) 120 { 121 case 0: 122 eeprom.width = PCI_EEPROM_WIDTH_93C46; 123 break; 124 case 1: 125 eeprom.width = PCI_EEPROM_WIDTH_93C66; 126 break; 127 default: 128 eeprom.width = PCI_EEPROM_WIDTH_93C86; 129 break; 130 } 131 eeprom.reg_data_in = 0; 132 eeprom.reg_data_out = 0; 133 eeprom.reg_data_clock = 0; 134 eeprom.reg_chip_select = 0; 135 136 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom, 137 EEPROM_SIZE / sizeof(u16)); 138 139 return 0; 140} 141 142static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev) 143{ 144 return rt2800_efuse_detect(rt2x00dev); 145} 146 147static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev) 148{ 149 return rt2800_read_eeprom_efuse(rt2x00dev); 150} 151 152/* 153 * Firmware functions 154 */ 155static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev) 156{ 157 /* 158 * Chip rt3290 use specific 4KB firmware named rt3290.bin. 159 */ 160 if (rt2x00_rt(rt2x00dev, RT3290)) 161 return FIRMWARE_RT3290; 162 else 163 return FIRMWARE_RT2860; 164} 165 166static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev, 167 const u8 *data, const size_t len) 168{ 169 u32 reg; 170 171 /* 172 * enable Host program ram write selection 173 */ 174 reg = 0; 175 rt2x00_set_field32(®, PBF_SYS_CTRL_HOST_RAM_WRITE, 1); 176 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, reg); 177 178 /* 179 * Write firmware to device. 180 */ 181 rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, 182 data, len); 183 184 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000); 185 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001); 186 187 rt2x00mmio_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 188 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 189 190 return 0; 191} 192 193/* 194 * Device state switch handlers. 195 */ 196static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev) 197{ 198 int retval; 199 200 retval = rt2800mmio_enable_radio(rt2x00dev); 201 if (retval) 202 return retval; 203 204 /* After resume MCU_BOOT_SIGNAL will trash these. */ 205 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0); 206 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0); 207 208 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02); 209 rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF); 210 211 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0); 212 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP); 213 214 return retval; 215} 216 217static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev, 218 enum dev_state state) 219{ 220 if (state == STATE_AWAKE) { 221 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 222 0, 0x02); 223 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP); 224 } else if (state == STATE_SLEEP) { 225 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, 226 0xffffffff); 227 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, 228 0xffffffff); 229 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP, 230 0xff, 0x01); 231 } 232 233 return 0; 234} 235 236static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev, 237 enum dev_state state) 238{ 239 int retval = 0; 240 241 switch (state) { 242 case STATE_RADIO_ON: 243 retval = rt2800pci_enable_radio(rt2x00dev); 244 break; 245 case STATE_RADIO_OFF: 246 /* 247 * After the radio has been disabled, the device should 248 * be put to sleep for powersaving. 249 */ 250 rt2800pci_set_state(rt2x00dev, STATE_SLEEP); 251 break; 252 case STATE_RADIO_IRQ_ON: 253 case STATE_RADIO_IRQ_OFF: 254 rt2800mmio_toggle_irq(rt2x00dev, state); 255 break; 256 case STATE_DEEP_SLEEP: 257 case STATE_SLEEP: 258 case STATE_STANDBY: 259 case STATE_AWAKE: 260 retval = rt2800pci_set_state(rt2x00dev, state); 261 break; 262 default: 263 retval = -ENOTSUPP; 264 break; 265 } 266 267 if (unlikely(retval)) 268 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n", 269 state, retval); 270 271 return retval; 272} 273 274/* 275 * Device probe functions. 276 */ 277static int rt2800pci_read_eeprom(struct rt2x00_dev *rt2x00dev) 278{ 279 int retval; 280 281 if (rt2800pci_efuse_detect(rt2x00dev)) 282 retval = rt2800pci_read_eeprom_efuse(rt2x00dev); 283 else 284 retval = rt2800pci_read_eeprom_pci(rt2x00dev); 285 286 return retval; 287} 288 289static const struct ieee80211_ops rt2800pci_mac80211_ops = { 290 .tx = rt2x00mac_tx, 291 .start = rt2x00mac_start, 292 .stop = rt2x00mac_stop, 293 .add_interface = rt2x00mac_add_interface, 294 .remove_interface = rt2x00mac_remove_interface, 295 .config = rt2x00mac_config, 296 .configure_filter = rt2x00mac_configure_filter, 297 .set_key = rt2x00mac_set_key, 298 .sw_scan_start = rt2x00mac_sw_scan_start, 299 .sw_scan_complete = rt2x00mac_sw_scan_complete, 300 .get_stats = rt2x00mac_get_stats, 301 .get_key_seq = rt2800_get_key_seq, 302 .set_rts_threshold = rt2800_set_rts_threshold, 303 .sta_add = rt2800_sta_add, 304 .sta_remove = rt2800_sta_remove, 305 .bss_info_changed = rt2x00mac_bss_info_changed, 306 .conf_tx = rt2800_conf_tx, 307 .get_tsf = rt2800_get_tsf, 308 .rfkill_poll = rt2x00mac_rfkill_poll, 309 .ampdu_action = rt2800_ampdu_action, 310 .flush = rt2x00mac_flush, 311 .get_survey = rt2800_get_survey, 312 .get_ringparam = rt2x00mac_get_ringparam, 313 .tx_frames_pending = rt2x00mac_tx_frames_pending, 314 .reconfig_complete = rt2x00mac_reconfig_complete, 315}; 316 317static const struct rt2800_ops rt2800pci_rt2800_ops = { 318 .register_read = rt2x00mmio_register_read, 319 .register_read_lock = rt2x00mmio_register_read, /* same for PCI */ 320 .register_write = rt2x00mmio_register_write, 321 .register_write_lock = rt2x00mmio_register_write, /* same for PCI */ 322 .register_multiread = rt2x00mmio_register_multiread, 323 .register_multiwrite = rt2x00mmio_register_multiwrite, 324 .regbusy_read = rt2x00mmio_regbusy_read, 325 .read_eeprom = rt2800pci_read_eeprom, 326 .hwcrypt_disabled = rt2800pci_hwcrypt_disabled, 327 .drv_write_firmware = rt2800pci_write_firmware, 328 .drv_init_registers = rt2800mmio_init_registers, 329 .drv_get_txwi = rt2800mmio_get_txwi, 330 .drv_get_dma_done = rt2800mmio_get_dma_done, 331}; 332 333static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = { 334 .irq_handler = rt2800mmio_interrupt, 335 .txstatus_tasklet = rt2800mmio_txstatus_tasklet, 336 .pretbtt_tasklet = rt2800mmio_pretbtt_tasklet, 337 .tbtt_tasklet = rt2800mmio_tbtt_tasklet, 338 .rxdone_tasklet = rt2800mmio_rxdone_tasklet, 339 .autowake_tasklet = rt2800mmio_autowake_tasklet, 340 .probe_hw = rt2800mmio_probe_hw, 341 .get_firmware_name = rt2800pci_get_firmware_name, 342 .check_firmware = rt2800_check_firmware, 343 .load_firmware = rt2800_load_firmware, 344 .initialize = rt2x00mmio_initialize, 345 .uninitialize = rt2x00mmio_uninitialize, 346 .get_entry_state = rt2800mmio_get_entry_state, 347 .clear_entry = rt2800mmio_clear_entry, 348 .set_device_state = rt2800pci_set_device_state, 349 .rfkill_poll = rt2800_rfkill_poll, 350 .link_stats = rt2800_link_stats, 351 .reset_tuner = rt2800_reset_tuner, 352 .link_tuner = rt2800_link_tuner, 353 .gain_calibration = rt2800_gain_calibration, 354 .vco_calibration = rt2800_vco_calibration, 355 .watchdog = rt2800_watchdog, 356 .start_queue = rt2800mmio_start_queue, 357 .kick_queue = rt2800mmio_kick_queue, 358 .stop_queue = rt2800mmio_stop_queue, 359 .flush_queue = rt2800mmio_flush_queue, 360 .write_tx_desc = rt2800mmio_write_tx_desc, 361 .write_tx_data = rt2800_write_tx_data, 362 .write_beacon = rt2800_write_beacon, 363 .clear_beacon = rt2800_clear_beacon, 364 .fill_rxdone = rt2800mmio_fill_rxdone, 365 .config_shared_key = rt2800_config_shared_key, 366 .config_pairwise_key = rt2800_config_pairwise_key, 367 .config_filter = rt2800_config_filter, 368 .config_intf = rt2800_config_intf, 369 .config_erp = rt2800_config_erp, 370 .config_ant = rt2800_config_ant, 371 .config = rt2800_config, 372 .pre_reset_hw = rt2800_pre_reset_hw, 373}; 374 375static const struct rt2x00_ops rt2800pci_ops = { 376 .name = KBUILD_MODNAME, 377 .drv_data_size = sizeof(struct rt2800_drv_data), 378 .max_ap_intf = 8, 379 .eeprom_size = EEPROM_SIZE, 380 .rf_size = RF_SIZE, 381 .tx_queues = NUM_TX_QUEUES, 382 .queue_init = rt2800mmio_queue_init, 383 .lib = &rt2800pci_rt2x00_ops, 384 .drv = &rt2800pci_rt2800_ops, 385 .hw = &rt2800pci_mac80211_ops, 386#ifdef CONFIG_RT2X00_LIB_DEBUGFS 387 .debugfs = &rt2800_rt2x00debug, 388#endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 389}; 390 391/* 392 * RT2800pci module information. 393 */ 394static const struct pci_device_id rt2800pci_device_table[] = { 395 { PCI_DEVICE(0x1814, 0x0601) }, 396 { PCI_DEVICE(0x1814, 0x0681) }, 397 { PCI_DEVICE(0x1814, 0x0701) }, 398 { PCI_DEVICE(0x1814, 0x0781) }, 399 { PCI_DEVICE(0x1814, 0x3090) }, 400 { PCI_DEVICE(0x1814, 0x3091) }, 401 { PCI_DEVICE(0x1814, 0x3092) }, 402 { PCI_DEVICE(0x1432, 0x7708) }, 403 { PCI_DEVICE(0x1432, 0x7727) }, 404 { PCI_DEVICE(0x1432, 0x7728) }, 405 { PCI_DEVICE(0x1432, 0x7738) }, 406 { PCI_DEVICE(0x1432, 0x7748) }, 407 { PCI_DEVICE(0x1432, 0x7758) }, 408 { PCI_DEVICE(0x1432, 0x7768) }, 409 { PCI_DEVICE(0x1462, 0x891a) }, 410 { PCI_DEVICE(0x1a3b, 0x1059) }, 411#ifdef CONFIG_RT2800PCI_RT3290 412 { PCI_DEVICE(0x1814, 0x3290) }, 413#endif 414#ifdef CONFIG_RT2800PCI_RT33XX 415 { PCI_DEVICE(0x1814, 0x3390) }, 416#endif 417#ifdef CONFIG_RT2800PCI_RT35XX 418 { PCI_DEVICE(0x1432, 0x7711) }, 419 { PCI_DEVICE(0x1432, 0x7722) }, 420 { PCI_DEVICE(0x1814, 0x3060) }, 421 { PCI_DEVICE(0x1814, 0x3062) }, 422 { PCI_DEVICE(0x1814, 0x3562) }, 423 { PCI_DEVICE(0x1814, 0x3592) }, 424 { PCI_DEVICE(0x1814, 0x3593) }, 425 { PCI_DEVICE(0x1814, 0x359f) }, 426#endif 427#ifdef CONFIG_RT2800PCI_RT53XX 428 { PCI_DEVICE(0x1814, 0x5360) }, 429 { PCI_DEVICE(0x1814, 0x5362) }, 430 { PCI_DEVICE(0x1814, 0x5390) }, 431 { PCI_DEVICE(0x1814, 0x5392) }, 432 { PCI_DEVICE(0x1814, 0x539a) }, 433 { PCI_DEVICE(0x1814, 0x539b) }, 434 { PCI_DEVICE(0x1814, 0x539f) }, 435#endif 436 { 0, } 437}; 438 439MODULE_AUTHOR(DRV_PROJECT); 440MODULE_VERSION(DRV_VERSION); 441MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver."); 442MODULE_FIRMWARE(FIRMWARE_RT2860); 443MODULE_DEVICE_TABLE(pci, rt2800pci_device_table); 444MODULE_LICENSE("GPL"); 445 446static int rt2800pci_probe(struct pci_dev *pci_dev, 447 const struct pci_device_id *id) 448{ 449 return rt2x00pci_probe(pci_dev, &rt2800pci_ops); 450} 451 452static struct pci_driver rt2800pci_driver = { 453 .name = KBUILD_MODNAME, 454 .id_table = rt2800pci_device_table, 455 .probe = rt2800pci_probe, 456 .remove = rt2x00pci_remove, 457 .driver.pm = &rt2x00pci_pm_ops, 458}; 459 460module_pci_driver(rt2800pci_driver);