cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dm.c (2542B)

      1// SPDX-License-Identifier: GPL-2.0
      2/* Copyright(c) 2009-2012  Realtek Corporation.*/
      3
      4#include "../wifi.h"
      5#include "../base.h"
      6#include "../pci.h"
      7#include "../core.h"
      8#include "reg.h"
      9#include "def.h"
     10#include "phy.h"
     11#include "dm.h"
     12#include "../rtl8192c/fw_common.h"
     13
     14void rtl92ce_dm_dynamic_txpower(struct ieee80211_hw *hw)
     15{
     16	struct rtl_priv *rtlpriv = rtl_priv(hw);
     17	struct rtl_phy *rtlphy = &(rtlpriv->phy);
     18	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
     19	long undec_sm_pwdb;
     20
     21	if (!rtlpriv->dm.dynamic_txpower_enable)
     22		return;
     23
     24	if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
     25		rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
     26		return;
     27	}
     28
     29	if ((mac->link_state < MAC80211_LINKED) &&
     30	    (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
     31		rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
     32			"Not connected to any\n");
     33
     34		rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
     35
     36		rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
     37		return;
     38	}
     39
     40	if (mac->link_state >= MAC80211_LINKED) {
     41		if (mac->opmode == NL80211_IFTYPE_ADHOC) {
     42			undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
     43			rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
     44				"AP Client PWDB = 0x%lx\n",
     45				undec_sm_pwdb);
     46		} else {
     47			undec_sm_pwdb = rtlpriv->dm.undec_sm_pwdb;
     48			rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
     49				"STA Default Port PWDB = 0x%lx\n",
     50				undec_sm_pwdb);
     51		}
     52	} else {
     53		undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
     54
     55		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
     56			"AP Ext Port PWDB = 0x%lx\n",
     57			undec_sm_pwdb);
     58	}
     59
     60	if (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
     61		rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
     62		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
     63			"TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n");
     64	} else if ((undec_sm_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
     65		   (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
     66
     67		rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
     68		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
     69			"TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n");
     70	} else if (undec_sm_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
     71		rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
     72		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
     73			"TXHIGHPWRLEVEL_NORMAL\n");
     74	}
     75
     76	if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) {
     77		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
     78			"PHY_SetTxPowerLevel8192S() Channel = %d\n",
     79			rtlphy->current_channel);
     80		rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
     81	}
     82
     83	rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
     84}