cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

dm.c (2790B)

      1// SPDX-License-Identifier: GPL-2.0
      2/* Copyright(c) 2009-2012  Realtek Corporation.*/
      3
      4#include "../wifi.h"
      5#include "../base.h"
      6#include "reg.h"
      7#include "def.h"
      8#include "phy.h"
      9#include "dm.h"
     10
     11void rtl92cu_dm_dynamic_txpower(struct ieee80211_hw *hw)
     12{
     13	struct rtl_priv *rtlpriv = rtl_priv(hw);
     14	struct rtl_phy *rtlphy = &(rtlpriv->phy);
     15	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
     16	long undec_sm_pwdb;
     17
     18	if (!rtlpriv->dm.dynamic_txpower_enable)
     19		return;
     20
     21	if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
     22		rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
     23		return;
     24	}
     25
     26	if ((mac->link_state < MAC80211_LINKED) &&
     27	    (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
     28		rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
     29			"Not connected to any\n");
     30
     31		rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
     32
     33		rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
     34		return;
     35	}
     36
     37	if (mac->link_state >= MAC80211_LINKED) {
     38		if (mac->opmode == NL80211_IFTYPE_ADHOC) {
     39			undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
     40			rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
     41				"AP Client PWDB = 0x%lx\n",
     42				undec_sm_pwdb);
     43		} else {
     44			undec_sm_pwdb = rtlpriv->dm.undec_sm_pwdb;
     45			rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
     46				"STA Default Port PWDB = 0x%lx\n",
     47				undec_sm_pwdb);
     48		}
     49	} else {
     50		undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
     51
     52		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
     53			"AP Ext Port PWDB = 0x%lx\n",
     54			undec_sm_pwdb);
     55	}
     56
     57	if (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
     58		rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
     59		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
     60			"TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n");
     61	} else if ((undec_sm_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
     62		   (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
     63
     64		rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
     65		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
     66			"TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n");
     67	} else if (undec_sm_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
     68		rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
     69		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
     70			"TXHIGHPWRLEVEL_NORMAL\n");
     71	}
     72
     73	if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) {
     74		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
     75			"PHY_SetTxPowerLevel8192S() Channel = %d\n",
     76			 rtlphy->current_channel);
     77		rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
     78		if (rtlpriv->dm.dynamic_txhighpower_lvl ==
     79		    TXHIGHPWRLEVEL_NORMAL)
     80			dm_restorepowerindex(hw);
     81		else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
     82			 TXHIGHPWRLEVEL_LEVEL1)
     83			dm_writepowerindex(hw, 0x14);
     84		else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
     85			 TXHIGHPWRLEVEL_LEVEL2)
     86			dm_writepowerindex(hw, 0x10);
     87	}
     88
     89	rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
     90}