cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dm.h (2145B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2/* Copyright(c) 2009-2012  Realtek Corporation.*/
      3
      4#ifndef	__RTL92C_DM_H__
      5#define __RTL92C_DM_H__
      6
      7#define HAL_DM_DIG_DISABLE			BIT(0)
      8#define HAL_DM_HIPWR_DISABLE			BIT(1)
      9
     10#define OFDM_TABLE_LENGTH			37
     11#define OFDM_TABLE_SIZE_92D			43
     12#define CCK_TABLE_LENGTH			33
     13
     14#define CCK_TABLE_SIZE				33
     15
     16#define BW_AUTO_SWITCH_HIGH_LOW			25
     17#define BW_AUTO_SWITCH_LOW_HIGH			30
     18
     19#define DM_DIG_FA_UPPER				0x32
     20#define DM_DIG_FA_LOWER				0x20
     21#define DM_DIG_FA_TH0				0x100
     22#define DM_DIG_FA_TH1				0x400
     23#define DM_DIG_FA_TH2				0x600
     24
     25#define RXPATHSELECTION_SS_TH_LOW		30
     26#define RXPATHSELECTION_DIFF_TH			18
     27
     28#define DM_RATR_STA_INIT			0
     29#define DM_RATR_STA_HIGH			1
     30#define DM_RATR_STA_MIDDLE			2
     31#define DM_RATR_STA_LOW				3
     32
     33#define CTS2SELF_THVAL				30
     34#define REGC38_TH				20
     35
     36#define WAIOTTHVAL				25
     37
     38#define TXHIGHPWRLEVEL_NORMAL			0
     39#define TXHIGHPWRLEVEL_LEVEL1			1
     40#define TXHIGHPWRLEVEL_LEVEL2			2
     41#define TXHIGHPWRLEVEL_BT1			3
     42#define TXHIGHPWRLEVEL_BT2			4
     43
     44#define DM_TYPE_BYFW				0
     45#define DM_TYPE_BYDRIVER			1
     46
     47#define TX_POWER_NEAR_FIELD_THRESH_LVL2		74
     48#define TX_POWER_NEAR_FIELD_THRESH_LVL1		67
     49#define INDEX_MAPPING_NUM			13
     50
     51struct swat {
     52	u8 failure_cnt;
     53	u8 try_flag;
     54	u8 stop_trying;
     55	long pre_rssi;
     56	long trying_threshold;
     57	u8 cur_antenna;
     58	u8 pre_antenna;
     59};
     60
     61enum tag_dynamic_init_gain_operation_type_definition {
     62	DIG_TYPE_THRESH_HIGH = 0,
     63	DIG_TYPE_THRESH_LOW = 1,
     64	DIG_TYPE_BACKOFF = 2,
     65	DIG_TYPE_RX_GAIN_MIN = 3,
     66	DIG_TYPE_RX_GAIN_MAX = 4,
     67	DIG_TYPE_ENABLE = 5,
     68	DIG_TYPE_DISABLE = 6,
     69	DIG_OP_TYPE_MAX
     70};
     71
     72enum dm_1r_cca {
     73	CCA_1R = 0,
     74	CCA_2R = 1,
     75	CCA_MAX = 2,
     76};
     77
     78enum dm_rf {
     79	RF_SAVE = 0,
     80	RF_NORMAL = 1,
     81	RF_MAX = 2,
     82};
     83
     84enum dm_sw_ant_switch {
     85	ANS_ANTENNA_B = 1,
     86	ANS_ANTENNA_A = 2,
     87	ANS_ANTENNA_MAX = 3,
     88};
     89
     90void rtl92d_dm_init(struct ieee80211_hw *hw);
     91void rtl92d_dm_watchdog(struct ieee80211_hw *hw);
     92void rtl92d_dm_init_edca_turbo(struct ieee80211_hw *hw);
     93void rtl92d_dm_write_dig(struct ieee80211_hw *hw);
     94void rtl92d_dm_check_txpower_tracking_thermal_meter(struct ieee80211_hw *hw);
     95void rtl92d_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
     96
     97#endif