cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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fw.h (8139B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2/* Copyright(c) 2009-2012  Realtek Corporation.*/
      3
      4#ifndef __REALTEK_FIRMWARE92S_H__
      5#define __REALTEK_FIRMWARE92S_H__
      6
      7#define RTL8190_MAX_FIRMWARE_CODE_SIZE		64000
      8#define RTL8190_MAX_RAW_FIRMWARE_CODE_SIZE	90000
      9#define RTL8190_CPU_START_OFFSET		0x80
     10/* Firmware Local buffer size. 64k */
     11#define	MAX_FIRMWARE_CODE_SIZE			0xFF00
     12
     13#define	RT_8192S_FIRMWARE_HDR_SIZE		80
     14#define RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE	32
     15
     16/* support till 64 bit bus width OS */
     17#define MAX_DEV_ADDR_SIZE			8
     18#define MAX_FIRMWARE_INFORMATION_SIZE		32
     19#define MAX_802_11_HEADER_LENGTH		(40 + \
     20						MAX_FIRMWARE_INFORMATION_SIZE)
     21#define ENCRYPTION_MAX_OVERHEAD			128
     22#define MAX_FRAGMENT_COUNT			8
     23#define MAX_TRANSMIT_BUFFER_SIZE		(1600 + \
     24						(MAX_802_11_HEADER_LENGTH + \
     25						ENCRYPTION_MAX_OVERHEAD) *\
     26						MAX_FRAGMENT_COUNT)
     27
     28#define H2C_TX_CMD_HDR_LEN			8
     29
     30/* The following DM control code are for Reg0x364, */
     31#define	FW_DIG_ENABLE_CTL			BIT(0)
     32#define	FW_HIGH_PWR_ENABLE_CTL			BIT(1)
     33#define	FW_SS_CTL				BIT(2)
     34#define	FW_RA_INIT_CTL				BIT(3)
     35#define	FW_RA_BG_CTL				BIT(4)
     36#define	FW_RA_N_CTL				BIT(5)
     37#define	FW_PWR_TRK_CTL				BIT(6)
     38#define	FW_IQK_CTL				BIT(7)
     39#define	FW_FA_CTL				BIT(8)
     40#define	FW_DRIVER_CTRL_DM_CTL			BIT(9)
     41#define	FW_PAPE_CTL_BY_SW_HW			BIT(10)
     42#define	FW_DISABLE_ALL_DM			0
     43#define	FW_PWR_TRK_PARAM_CLR			0x0000ffff
     44#define	FW_RA_PARAM_CLR				0xffff0000
     45
     46enum desc_packet_type {
     47	DESC_PACKET_TYPE_INIT = 0,
     48	DESC_PACKET_TYPE_NORMAL = 1,
     49};
     50
     51/* 8-bytes alignment required */
     52struct fw_priv {
     53	/* --- long word 0 ---- */
     54	/* 0x12: CE product, 0x92: IT product */
     55	u8 signature_0;
     56	/* 0x87: CE product, 0x81: IT product */
     57	u8 signature_1;
     58	/* 0x81: PCI-AP, 01:PCIe, 02: 92S-U,
     59	 * 0x82: USB-AP, 0x12: 72S-U, 03:SDIO */
     60	u8 hci_sel;
     61	/* the same value as reigster value  */
     62	u8 chip_version;
     63	/* customer  ID low byte */
     64	u8 customer_id_0;
     65	/* customer  ID high byte */
     66	u8 customer_id_1;
     67	/* 0x11:  1T1R, 0x12: 1T2R,
     68	 * 0x92: 1T2R turbo, 0x22: 2T2R */
     69	u8 rf_config;
     70	/* 4: 4EP, 6: 6EP, 11: 11EP */
     71	u8 usb_ep_num;
     72
     73	/* --- long word 1 ---- */
     74	/* regulatory class bit map 0 */
     75	u8 regulatory_class_0;
     76	/* regulatory class bit map 1 */
     77	u8 regulatory_class_1;
     78	/* regulatory class bit map 2 */
     79	u8 regulatory_class_2;
     80	/* regulatory class bit map 3 */
     81	u8 regulatory_class_3;
     82	/* 0:SWSI, 1:HWSI, 2:HWPI */
     83	u8 rfintfs;
     84	u8 def_nettype;
     85	u8 rsvd010;
     86	u8 rsvd011;
     87
     88	/* --- long word 2 ---- */
     89	/* 0x00: normal, 0x03: MACLBK, 0x01: PHYLBK */
     90	u8 lbk_mode;
     91	/* 1: for MP use, 0: for normal
     92	 * driver (to be discussed) */
     93	u8 mp_mode;
     94	u8 rsvd020;
     95	u8 rsvd021;
     96	u8 rsvd022;
     97	u8 rsvd023;
     98	u8 rsvd024;
     99	u8 rsvd025;
    100
    101	/* --- long word 3 ---- */
    102	/* QoS enable */
    103	u8 qos_en;
    104	/* 40MHz BW enable */
    105	/* 4181 convert AMSDU to AMPDU, 0: disable */
    106	u8 bw_40mhz_en;
    107	u8 amsdu2ampdu_en;
    108	/* 11n AMPDU enable */
    109	u8 ampdu_en;
    110	/* FW offloads, 0: driver handles */
    111	u8 rate_control_offload;
    112	/* FW offloads, 0: driver handles */
    113	u8 aggregation_offload;
    114	u8 rsvd030;
    115	u8 rsvd031;
    116
    117	/* --- long word 4 ---- */
    118	/* 1. FW offloads, 0: driver handles */
    119	u8 beacon_offload;
    120	/* 2. FW offloads, 0: driver handles */
    121	u8 mlme_offload;
    122	/* 3. FW offloads, 0: driver handles */
    123	u8 hwpc_offload;
    124	/* 4. FW offloads, 0: driver handles */
    125	u8 tcp_checksum_offload;
    126	/* 5. FW offloads, 0: driver handles */
    127	u8 tcp_offload;
    128	/* 6. FW offloads, 0: driver handles */
    129	u8 ps_control_offload;
    130	/* 7. FW offloads, 0: driver handles */
    131	u8 wwlan_offload;
    132	u8 rsvd040;
    133
    134	/* --- long word 5 ---- */
    135	/* tcp tx packet length low byte */
    136	u8 tcp_tx_frame_len_L;
    137	/* tcp tx packet length high byte */
    138	u8 tcp_tx_frame_len_H;
    139	/* tcp rx packet length low byte */
    140	u8 tcp_rx_frame_len_L;
    141	/* tcp rx packet length high byte */
    142	u8 tcp_rx_frame_len_H;
    143	u8 rsvd050;
    144	u8 rsvd051;
    145	u8 rsvd052;
    146	u8 rsvd053;
    147};
    148
    149/* 8-byte alinment required */
    150struct fw_hdr {
    151
    152	/* --- LONG WORD 0 ---- */
    153	u16 signature;
    154	/* 0x8000 ~ 0x8FFF for FPGA version,
    155	 * 0x0000 ~ 0x7FFF for ASIC version, */
    156	u16 version;
    157	/* define the size of boot loader */
    158	u32 dmem_size;
    159
    160
    161	/* --- LONG WORD 1 ---- */
    162	/* define the size of FW in IMEM */
    163	u32 img_imem_size;
    164	/* define the size of FW in SRAM */
    165	u32 img_sram_size;
    166
    167	/* --- LONG WORD 2 ---- */
    168	/* define the size of DMEM variable */
    169	u32 fw_priv_size;
    170	u32 rsvd0;
    171
    172	/* --- LONG WORD 3 ---- */
    173	u32 rsvd1;
    174	u32 rsvd2;
    175
    176	struct fw_priv fwpriv;
    177
    178} ;
    179
    180enum fw_status {
    181	FW_STATUS_INIT = 0,
    182	FW_STATUS_LOAD_IMEM = 1,
    183	FW_STATUS_LOAD_EMEM = 2,
    184	FW_STATUS_LOAD_DMEM = 3,
    185	FW_STATUS_READY = 4,
    186};
    187
    188struct rt_firmware {
    189	struct fw_hdr *pfwheader;
    190	enum fw_status fwstatus;
    191	u16 firmwareversion;
    192	u8 fw_imem[RTL8190_MAX_FIRMWARE_CODE_SIZE];
    193	u8 fw_emem[RTL8190_MAX_FIRMWARE_CODE_SIZE];
    194	u32 fw_imem_len;
    195	u32 fw_emem_len;
    196	u8 sz_fw_tmpbuffer[RTL8190_MAX_RAW_FIRMWARE_CODE_SIZE];
    197	u32 sz_fw_tmpbufferlen;
    198	u16 cmdpacket_fragthresold;
    199};
    200
    201struct h2c_set_pwrmode_parm {
    202	u8 mode;
    203	u8 flag_low_traffic_en;
    204	u8 flag_lpnav_en;
    205	u8 flag_rf_low_snr_en;
    206	/* 1: dps, 0: 32k */
    207	u8 flag_dps_en;
    208	u8 bcn_rx_en;
    209	u8 bcn_pass_cnt;
    210	/* beacon TO (ms). ¡§=0¡¨ no limit. */
    211	u8 bcn_to;
    212	u16	bcn_itv;
    213	/* only for VOIP mode. */
    214	u8 app_itv;
    215	u8 awake_bcn_itvl;
    216	u8 smart_ps;
    217	/* unit: 100 ms */
    218	u8 bcn_pass_period;
    219};
    220
    221struct h2c_joinbss_rpt_parm {
    222	u8 opmode;
    223	u8 ps_qos_info;
    224	u8 bssid[6];
    225	u16 bcnitv;
    226	u16 aid;
    227} ;
    228
    229struct h2c_wpa_ptk {
    230	/* EAPOL-Key Key Confirmation Key (KCK) */
    231	u8 kck[16];
    232	/* EAPOL-Key Key Encryption Key (KEK) */
    233	u8 kek[16];
    234	/* Temporal Key 1 (TK1) */
    235	u8 tk1[16];
    236	union {
    237		/* Temporal Key 2 (TK2) */
    238		u8 tk2[16];
    239		struct {
    240			u8 tx_mic_key[8];
    241			u8 rx_mic_key[8];
    242		} athu;
    243	} u;
    244};
    245
    246struct h2c_wpa_two_way_parm {
    247	/* algorithm TKIP or AES */
    248	u8 pairwise_en_alg;
    249	u8 group_en_alg;
    250	struct h2c_wpa_ptk wpa_ptk_value;
    251} ;
    252
    253enum h2c_cmd {
    254	FW_H2C_SETPWRMODE = 0,
    255	FW_H2C_JOINBSSRPT = 1,
    256	FW_H2C_WOWLAN_UPDATE_GTK = 2,
    257	FW_H2C_WOWLAN_UPDATE_IV = 3,
    258	FW_H2C_WOWLAN_OFFLOAD = 4,
    259};
    260
    261enum fw_h2c_cmd {
    262	H2C_READ_MACREG_CMD,				/*0*/
    263	H2C_WRITE_MACREG_CMD,
    264	H2C_READBB_CMD,
    265	H2C_WRITEBB_CMD,
    266	H2C_READRF_CMD,
    267	H2C_WRITERF_CMD,				/*5*/
    268	H2C_READ_EEPROM_CMD,
    269	H2C_WRITE_EEPROM_CMD,
    270	H2C_READ_EFUSE_CMD,
    271	H2C_WRITE_EFUSE_CMD,
    272	H2C_READ_CAM_CMD,				/*10*/
    273	H2C_WRITE_CAM_CMD,
    274	H2C_SETBCNITV_CMD,
    275	H2C_SETMBIDCFG_CMD,
    276	H2C_JOINBSS_CMD,
    277	H2C_DISCONNECT_CMD,				/*15*/
    278	H2C_CREATEBSS_CMD,
    279	H2C_SETOPMODE_CMD,
    280	H2C_SITESURVEY_CMD,
    281	H2C_SETAUTH_CMD,
    282	H2C_SETKEY_CMD,					/*20*/
    283	H2C_SETSTAKEY_CMD,
    284	H2C_SETASSOCSTA_CMD,
    285	H2C_DELASSOCSTA_CMD,
    286	H2C_SETSTAPWRSTATE_CMD,
    287	H2C_SETBASICRATE_CMD,				/*25*/
    288	H2C_GETBASICRATE_CMD,
    289	H2C_SETDATARATE_CMD,
    290	H2C_GETDATARATE_CMD,
    291	H2C_SETPHYINFO_CMD,
    292	H2C_GETPHYINFO_CMD,				/*30*/
    293	H2C_SETPHY_CMD,
    294	H2C_GETPHY_CMD,
    295	H2C_READRSSI_CMD,
    296	H2C_READGAIN_CMD,
    297	H2C_SETATIM_CMD,				/*35*/
    298	H2C_SETPWRMODE_CMD,
    299	H2C_JOINBSSRPT_CMD,
    300	H2C_SETRATABLE_CMD,
    301	H2C_GETRATABLE_CMD,
    302	H2C_GETCCXREPORT_CMD,				/*40*/
    303	H2C_GETDTMREPORT_CMD,
    304	H2C_GETTXRATESTATICS_CMD,
    305	H2C_SETUSBSUSPEND_CMD,
    306	H2C_SETH2CLBK_CMD,
    307	H2C_TMP1,					/*45*/
    308	H2C_WOWLAN_UPDATE_GTK_CMD,
    309	H2C_WOWLAN_FW_OFFLOAD,
    310	H2C_TMP2,
    311	H2C_TMP3,
    312	H2C_WOWLAN_UPDATE_IV_CMD,			/*50*/
    313	H2C_TMP4,
    314};
    315
    316/* The following macros are used for FW
    317 * CMD map and parameter updated. */
    318#define FW_CMD_IO_CLR(rtlpriv, _bit)				\
    319	do {							\
    320		udelay(1000);					\
    321		rtlpriv->rtlhal.fwcmd_iomap &= (~_bit);		\
    322	} while (0)
    323
    324#define FW_CMD_IO_UPDATE(rtlpriv, _val)				\
    325	rtlpriv->rtlhal.fwcmd_iomap = _val;
    326
    327#define FW_CMD_IO_SET(rtlpriv, _val)				\
    328	do {							\
    329		rtl_write_word(rtlpriv, LBUS_MON_ADDR, (u16)_val);	\
    330		FW_CMD_IO_UPDATE(rtlpriv, _val);		\
    331	} while (0)
    332
    333#define FW_CMD_PARA_SET(rtlpriv, _val)				\
    334	do {							\
    335		rtl_write_dword(rtlpriv, LBUS_ADDR_MASK, _val);	\
    336		rtlpriv->rtlhal.fwcmd_ioparam = _val;		\
    337	} while (0)
    338
    339#define FW_CMD_IO_QUERY(rtlpriv)				\
    340	(u16)(rtlpriv->rtlhal.fwcmd_iomap)
    341#define FW_CMD_IO_PARA_QUERY(rtlpriv)				\
    342	((u32)(rtlpriv->rtlhal.fwcmd_ioparam))
    343
    344int rtl92s_download_fw(struct ieee80211_hw *hw);
    345void rtl92s_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
    346void rtl92s_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw,
    347				      u8 mstatus, u8 ps_qosinfo);
    348
    349#endif
    350