cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dm.h (7929B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2/* Copyright(c) 2009-2014  Realtek Corporation.*/
      3
      4#ifndef	__RTL8723BE_DM_H__
      5#define __RTL8723BE_DM_H__
      6
      7#define	MAIN_ANT		0
      8#define	AUX_ANT			1
      9#define	MAIN_ANT_CG_TRX		1
     10#define	AUX_ANT_CG_TRX		0
     11#define	MAIN_ANT_CGCS_RX	0
     12#define	AUX_ANT_CGCS_RX		1
     13
     14#define	TXSCALE_TABLE_SIZE	30
     15
     16/*RF REG LIST*/
     17#define	DM_REG_RF_MODE_11N			0x00
     18#define	DM_REG_RF_0B_11N			0x0B
     19#define	DM_REG_CHNBW_11N			0x18
     20#define	DM_REG_T_METER_11N			0x24
     21#define	DM_REG_RF_25_11N			0x25
     22#define	DM_REG_RF_26_11N			0x26
     23#define	DM_REG_RF_27_11N			0x27
     24#define	DM_REG_RF_2B_11N			0x2B
     25#define	DM_REG_RF_2C_11N			0x2C
     26#define	DM_REG_RXRF_A3_11N			0x3C
     27#define	DM_REG_T_METER_92D_11N			0x42
     28#define	DM_REG_T_METER_88E_11N			0x42
     29
     30/*BB REG LIST*/
     31/*PAGE 8 */
     32#define	DM_REG_BB_CTRL_11N			0x800
     33#define	DM_REG_RF_PIN_11N			0x804
     34#define	DM_REG_PSD_CTRL_11N			0x808
     35#define	DM_REG_TX_ANT_CTRL_11N			0x80C
     36#define	DM_REG_BB_PWR_SAV5_11N			0x818
     37#define	DM_REG_CCK_RPT_FORMAT_11N		0x824
     38#define	DM_REG_RX_DEFUALT_A_11N			0x858
     39#define	DM_REG_RX_DEFUALT_B_11N			0x85A
     40#define	DM_REG_BB_PWR_SAV3_11N			0x85C
     41#define	DM_REG_ANTSEL_CTRL_11N			0x860
     42#define	DM_REG_RX_ANT_CTRL_11N			0x864
     43#define	DM_REG_PIN_CTRL_11N			0x870
     44#define	DM_REG_BB_PWR_SAV1_11N			0x874
     45#define	DM_REG_ANTSEL_PATH_11N			0x878
     46#define	DM_REG_BB_3WIRE_11N			0x88C
     47#define	DM_REG_SC_CNT_11N			0x8C4
     48#define	DM_REG_PSD_DATA_11N			0x8B4
     49/*PAGE 9*/
     50#define	DM_REG_ANT_MAPPING1_11N			0x914
     51#define	DM_REG_ANT_MAPPING2_11N			0x918
     52/*PAGE A*/
     53#define	DM_REG_CCK_ANTDIV_PARA1_11N		0xA00
     54#define	DM_REG_CCK_CCA_11N			0xA0A
     55#define	DM_REG_CCK_ANTDIV_PARA2_11N		0xA0C
     56#define	DM_REG_CCK_ANTDIV_PARA3_11N		0xA10
     57#define	DM_REG_CCK_ANTDIV_PARA4_11N		0xA14
     58#define	DM_REG_CCK_FILTER_PARA1_11N		0xA22
     59#define	DM_REG_CCK_FILTER_PARA2_11N		0xA23
     60#define	DM_REG_CCK_FILTER_PARA3_11N		0xA24
     61#define	DM_REG_CCK_FILTER_PARA4_11N		0xA25
     62#define	DM_REG_CCK_FILTER_PARA5_11N		0xA26
     63#define	DM_REG_CCK_FILTER_PARA6_11N		0xA27
     64#define	DM_REG_CCK_FILTER_PARA7_11N		0xA28
     65#define	DM_REG_CCK_FILTER_PARA8_11N		0xA29
     66#define	DM_REG_CCK_FA_RST_11N			0xA2C
     67#define	DM_REG_CCK_FA_MSB_11N			0xA58
     68#define	DM_REG_CCK_FA_LSB_11N			0xA5C
     69#define	DM_REG_CCK_CCA_CNT_11N			0xA60
     70#define	DM_REG_BB_PWR_SAV4_11N			0xA74
     71/*PAGE B */
     72#define	DM_REG_LNA_SWITCH_11N			0xB2C
     73#define	DM_REG_PATH_SWITCH_11N			0xB30
     74#define	DM_REG_RSSI_CTRL_11N			0xB38
     75#define	DM_REG_CONFIG_ANTA_11N			0xB68
     76#define	DM_REG_RSSI_BT_11N			0xB9C
     77/*PAGE C */
     78#define	DM_REG_OFDM_FA_HOLDC_11N		0xC00
     79#define	DM_REG_RX_PATH_11N			0xC04
     80#define	DM_REG_TRMUX_11N			0xC08
     81#define	DM_REG_OFDM_FA_RSTC_11N			0xC0C
     82#define	DM_REG_RXIQI_MATRIX_11N			0xC14
     83#define	DM_REG_TXIQK_MATRIX_LSB1_11N		0xC4C
     84#define	DM_REG_IGI_A_11N			0xC50
     85#define	DM_REG_ANTDIV_PARA2_11N			0xC54
     86#define	DM_REG_IGI_B_11N			0xC58
     87#define	DM_REG_ANTDIV_PARA3_11N			0xC5C
     88#define	DM_REG_BB_PWR_SAV2_11N			0xC70
     89#define	DM_REG_RX_OFF_11N			0xC7C
     90#define	DM_REG_TXIQK_MATRIXA_11N		0xC80
     91#define	DM_REG_TXIQK_MATRIXB_11N		0xC88
     92#define	DM_REG_TXIQK_MATRIXA_LSB2_11N		0xC94
     93#define	DM_REG_TXIQK_MATRIXB_LSB2_11N		0xC9C
     94#define	DM_REG_RXIQK_MATRIX_LSB_11N		0xCA0
     95#define	DM_REG_ANTDIV_PARA1_11N			0xCA4
     96#define	DM_REG_OFDM_FA_TYPE1_11N		0xCF0
     97/*PAGE D */
     98#define	DM_REG_OFDM_FA_RSTD_11N			0xD00
     99#define	DM_REG_OFDM_FA_TYPE2_11N		0xDA0
    100#define	DM_REG_OFDM_FA_TYPE3_11N		0xDA4
    101#define	DM_REG_OFDM_FA_TYPE4_11N		0xDA8
    102/*PAGE E */
    103#define	DM_REG_TXAGC_A_6_18_11N			0xE00
    104#define	DM_REG_TXAGC_A_24_54_11N		0xE04
    105#define	DM_REG_TXAGC_A_1_MCS32_11N		0xE08
    106#define	DM_REG_TXAGC_A_MCS0_3_11N		0xE10
    107#define	DM_REG_TXAGC_A_MCS4_7_11N		0xE14
    108#define	DM_REG_TXAGC_A_MCS8_11_11N		0xE18
    109#define	DM_REG_TXAGC_A_MCS12_15_11N		0xE1C
    110#define	DM_REG_FPGA0_IQK_11N			0xE28
    111#define	DM_REG_TXIQK_TONE_A_11N			0xE30
    112#define	DM_REG_RXIQK_TONE_A_11N			0xE34
    113#define	DM_REG_TXIQK_PI_A_11N			0xE38
    114#define	DM_REG_RXIQK_PI_A_11N			0xE3C
    115#define	DM_REG_TXIQK_11N			0xE40
    116#define	DM_REG_RXIQK_11N			0xE44
    117#define	DM_REG_IQK_AGC_PTS_11N			0xE48
    118#define	DM_REG_IQK_AGC_RSP_11N			0xE4C
    119#define	DM_REG_BLUETOOTH_11N			0xE6C
    120#define	DM_REG_RX_WAIT_CCA_11N			0xE70
    121#define	DM_REG_TX_CCK_RFON_11N			0xE74
    122#define	DM_REG_TX_CCK_BBON_11N			0xE78
    123#define	DM_REG_OFDM_RFON_11N			0xE7C
    124#define	DM_REG_OFDM_BBON_11N			0xE80
    125#define		DM_REG_TX2RX_11N		0xE84
    126#define	DM_REG_TX2TX_11N			0xE88
    127#define	DM_REG_RX_CCK_11N			0xE8C
    128#define	DM_REG_RX_OFDM_11N			0xED0
    129#define	DM_REG_RX_WAIT_RIFS_11N			0xED4
    130#define	DM_REG_RX2RX_11N			0xED8
    131#define	DM_REG_STANDBY_11N			0xEDC
    132#define	DM_REG_SLEEP_11N			0xEE0
    133#define	DM_REG_PMPD_ANAEN_11N			0xEEC
    134
    135/*MAC REG LIST*/
    136#define	DM_REG_BB_RST_11N			0x02
    137#define	DM_REG_ANTSEL_PIN_11N			0x4C
    138#define	DM_REG_EARLY_MODE_11N			0x4D0
    139#define	DM_REG_RSSI_MONITOR_11N			0x4FE
    140#define	DM_REG_EDCA_VO_11N			0x500
    141#define	DM_REG_EDCA_VI_11N			0x504
    142#define	DM_REG_EDCA_BE_11N			0x508
    143#define	DM_REG_EDCA_BK_11N			0x50C
    144#define	DM_REG_TXPAUSE_11N			0x522
    145#define	DM_REG_RESP_TX_11N			0x6D8
    146#define	DM_REG_ANT_TRAIN_PARA1_11N		0x7b0
    147#define	DM_REG_ANT_TRAIN_PARA2_11N		0x7b4
    148
    149/*DIG Related*/
    150#define	DM_BIT_IGI_11N				0x0000007F
    151
    152#define HAL_DM_DIG_DISABLE			BIT(0)
    153#define HAL_DM_HIPWR_DISABLE			BIT(1)
    154
    155#define OFDM_TABLE_LENGTH			43
    156#define CCK_TABLE_LENGTH			33
    157
    158#define OFDM_TABLE_SIZE				37
    159#define CCK_TABLE_SIZE				33
    160
    161#define BW_AUTO_SWITCH_HIGH_LOW			25
    162#define BW_AUTO_SWITCH_LOW_HIGH			30
    163
    164#define DM_DIG_FA_UPPER				0x3e
    165#define DM_DIG_FA_LOWER				0x1e
    166#define DM_DIG_FA_TH0				0x200
    167#define DM_DIG_FA_TH1				0x300
    168#define DM_DIG_FA_TH2				0x400
    169
    170#define RXPATHSELECTION_SS_TH_LOW		30
    171#define RXPATHSELECTION_DIFF_TH			18
    172
    173#define DM_RATR_STA_INIT			0
    174#define DM_RATR_STA_HIGH			1
    175#define DM_RATR_STA_MIDDLE			2
    176#define DM_RATR_STA_LOW				3
    177
    178#define CTS2SELF_THVAL				30
    179#define REGC38_TH				20
    180
    181#define WAIOTTHVAL				25
    182
    183#define TXHIGHPWRLEVEL_NORMAL			0
    184#define TXHIGHPWRLEVEL_LEVEL1			1
    185#define TXHIGHPWRLEVEL_LEVEL2			2
    186#define TXHIGHPWRLEVEL_BT1			3
    187#define TXHIGHPWRLEVEL_BT2			4
    188
    189#define DM_TYPE_BYFW				0
    190#define DM_TYPE_BYDRIVER			1
    191
    192#define TX_POWER_NEAR_FIELD_THRESH_LVL2		74
    193#define TX_POWER_NEAR_FIELD_THRESH_LVL1		67
    194#define TXPWRTRACK_MAX_IDX			6
    195
    196/* Dynamic ATC switch */
    197#define ATC_STATUS_OFF				0x0 /* enable */
    198#define	ATC_STATUS_ON				0x1 /* disable */
    199#define	CFO_THRESHOLD_XTAL			10 /* kHz */
    200#define	CFO_THRESHOLD_ATC			80 /* kHz */
    201
    202enum dm_1r_cca_e {
    203	CCA_1R		= 0,
    204	CCA_2R		= 1,
    205	CCA_MAX		= 2,
    206};
    207
    208enum dm_rf_e {
    209	RF_SAVE		= 0,
    210	RF_NORMAL	= 1,
    211	RF_MAX		= 2,
    212};
    213
    214enum dm_sw_ant_switch_e {
    215	ANS_ANTENNA_B	= 1,
    216	ANS_ANTENNA_A	= 2,
    217	ANS_ANTENNA_MAX	= 3,
    218};
    219
    220enum pwr_track_control_method {
    221	BBSWING,
    222	TXAGC
    223};
    224
    225#define BT_RSSI_STATE_NORMAL_POWER      BIT_OFFSET_LEN_MASK_32(0, 1)
    226#define BT_RSSI_STATE_AMDPU_OFF         BIT_OFFSET_LEN_MASK_32(1, 1)
    227#define BT_RSSI_STATE_SPECIAL_LOW       BIT_OFFSET_LEN_MASK_32(2, 1)
    228#define BT_RSSI_STATE_BG_EDCA_LOW       BIT_OFFSET_LEN_MASK_32(3, 1)
    229#define BT_RSSI_STATE_TXPOWER_LOW       BIT_OFFSET_LEN_MASK_32(4, 1)
    230#define GET_UNDECORATED_AVERAGE_RSSI(_priv)     \
    231	((((struct rtl_priv *)(_priv))->mac80211.opmode == \
    232		NL80211_IFTYPE_ADHOC) ? \
    233	(((struct rtl_priv *)(_priv))->dm.entry_min_undecoratedsmoothed_pwdb) :\
    234	(((struct rtl_priv *)(_priv))->dm.undecorated_smoothed_pwdb))
    235
    236void rtl8723be_dm_set_tx_ant_by_tx_info(struct ieee80211_hw *hw, u8 *pdesc,
    237					u32 mac_id);
    238void rtl8723be_dm_ant_sel_statistics(struct ieee80211_hw *hw, u8 antsel_tr_mux,
    239				     u32 mac_id, u32 rx_pwdb_all);
    240void rtl8723be_dm_fast_antenna_training_callback(unsigned long data);
    241void rtl8723be_dm_init(struct ieee80211_hw *hw);
    242void rtl8723be_dm_watchdog(struct ieee80211_hw *hw);
    243void rtl8723be_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi);
    244void rtl8723be_dm_check_txpower_tracking(struct ieee80211_hw *hw);
    245void rtl8723be_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
    246void rtl8723be_dm_txpower_track_adjust(struct ieee80211_hw *hw, u8 type,
    247				       u8 *pdirection, u32 *poutwrite_val);
    248#endif