cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

main.c (58354B)


      1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
      2/* Copyright(c) 2018-2019  Realtek Corporation
      3 */
      4
      5#include <linux/devcoredump.h>
      6
      7#include "main.h"
      8#include "regd.h"
      9#include "fw.h"
     10#include "ps.h"
     11#include "sec.h"
     12#include "mac.h"
     13#include "coex.h"
     14#include "phy.h"
     15#include "reg.h"
     16#include "efuse.h"
     17#include "tx.h"
     18#include "debug.h"
     19#include "bf.h"
     20#include "sar.h"
     21
     22bool rtw_disable_lps_deep_mode;
     23EXPORT_SYMBOL(rtw_disable_lps_deep_mode);
     24bool rtw_bf_support = true;
     25unsigned int rtw_debug_mask;
     26EXPORT_SYMBOL(rtw_debug_mask);
     27/* EDCCA is enabled during normal behavior. For debugging purpose in
     28 * a noisy environment, it can be disabled via edcca debugfs. Because
     29 * all rtw88 devices will probably be affected if environment is noisy,
     30 * rtw_edcca_enabled is just declared by driver instead of by device.
     31 * So, turning it off will take effect for all rtw88 devices before
     32 * there is a tough reason to maintain rtw_edcca_enabled by device.
     33 */
     34bool rtw_edcca_enabled = true;
     35
     36module_param_named(disable_lps_deep, rtw_disable_lps_deep_mode, bool, 0644);
     37module_param_named(support_bf, rtw_bf_support, bool, 0644);
     38module_param_named(debug_mask, rtw_debug_mask, uint, 0644);
     39
     40MODULE_PARM_DESC(disable_lps_deep, "Set Y to disable Deep PS");
     41MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support");
     42MODULE_PARM_DESC(debug_mask, "Debugging mask");
     43
     44static struct ieee80211_channel rtw_channeltable_2g[] = {
     45	{.center_freq = 2412, .hw_value = 1,},
     46	{.center_freq = 2417, .hw_value = 2,},
     47	{.center_freq = 2422, .hw_value = 3,},
     48	{.center_freq = 2427, .hw_value = 4,},
     49	{.center_freq = 2432, .hw_value = 5,},
     50	{.center_freq = 2437, .hw_value = 6,},
     51	{.center_freq = 2442, .hw_value = 7,},
     52	{.center_freq = 2447, .hw_value = 8,},
     53	{.center_freq = 2452, .hw_value = 9,},
     54	{.center_freq = 2457, .hw_value = 10,},
     55	{.center_freq = 2462, .hw_value = 11,},
     56	{.center_freq = 2467, .hw_value = 12,},
     57	{.center_freq = 2472, .hw_value = 13,},
     58	{.center_freq = 2484, .hw_value = 14,},
     59};
     60
     61static struct ieee80211_channel rtw_channeltable_5g[] = {
     62	{.center_freq = 5180, .hw_value = 36,},
     63	{.center_freq = 5200, .hw_value = 40,},
     64	{.center_freq = 5220, .hw_value = 44,},
     65	{.center_freq = 5240, .hw_value = 48,},
     66	{.center_freq = 5260, .hw_value = 52,},
     67	{.center_freq = 5280, .hw_value = 56,},
     68	{.center_freq = 5300, .hw_value = 60,},
     69	{.center_freq = 5320, .hw_value = 64,},
     70	{.center_freq = 5500, .hw_value = 100,},
     71	{.center_freq = 5520, .hw_value = 104,},
     72	{.center_freq = 5540, .hw_value = 108,},
     73	{.center_freq = 5560, .hw_value = 112,},
     74	{.center_freq = 5580, .hw_value = 116,},
     75	{.center_freq = 5600, .hw_value = 120,},
     76	{.center_freq = 5620, .hw_value = 124,},
     77	{.center_freq = 5640, .hw_value = 128,},
     78	{.center_freq = 5660, .hw_value = 132,},
     79	{.center_freq = 5680, .hw_value = 136,},
     80	{.center_freq = 5700, .hw_value = 140,},
     81	{.center_freq = 5720, .hw_value = 144,},
     82	{.center_freq = 5745, .hw_value = 149,},
     83	{.center_freq = 5765, .hw_value = 153,},
     84	{.center_freq = 5785, .hw_value = 157,},
     85	{.center_freq = 5805, .hw_value = 161,},
     86	{.center_freq = 5825, .hw_value = 165,
     87	 .flags = IEEE80211_CHAN_NO_HT40MINUS},
     88};
     89
     90static struct ieee80211_rate rtw_ratetable[] = {
     91	{.bitrate = 10, .hw_value = 0x00,},
     92	{.bitrate = 20, .hw_value = 0x01,},
     93	{.bitrate = 55, .hw_value = 0x02,},
     94	{.bitrate = 110, .hw_value = 0x03,},
     95	{.bitrate = 60, .hw_value = 0x04,},
     96	{.bitrate = 90, .hw_value = 0x05,},
     97	{.bitrate = 120, .hw_value = 0x06,},
     98	{.bitrate = 180, .hw_value = 0x07,},
     99	{.bitrate = 240, .hw_value = 0x08,},
    100	{.bitrate = 360, .hw_value = 0x09,},
    101	{.bitrate = 480, .hw_value = 0x0a,},
    102	{.bitrate = 540, .hw_value = 0x0b,},
    103};
    104
    105u16 rtw_desc_to_bitrate(u8 desc_rate)
    106{
    107	struct ieee80211_rate rate;
    108
    109	if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n"))
    110		return 0;
    111
    112	rate = rtw_ratetable[desc_rate];
    113
    114	return rate.bitrate;
    115}
    116
    117static struct ieee80211_supported_band rtw_band_2ghz = {
    118	.band = NL80211_BAND_2GHZ,
    119
    120	.channels = rtw_channeltable_2g,
    121	.n_channels = ARRAY_SIZE(rtw_channeltable_2g),
    122
    123	.bitrates = rtw_ratetable,
    124	.n_bitrates = ARRAY_SIZE(rtw_ratetable),
    125
    126	.ht_cap = {0},
    127	.vht_cap = {0},
    128};
    129
    130static struct ieee80211_supported_band rtw_band_5ghz = {
    131	.band = NL80211_BAND_5GHZ,
    132
    133	.channels = rtw_channeltable_5g,
    134	.n_channels = ARRAY_SIZE(rtw_channeltable_5g),
    135
    136	/* 5G has no CCK rates */
    137	.bitrates = rtw_ratetable + 4,
    138	.n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4,
    139
    140	.ht_cap = {0},
    141	.vht_cap = {0},
    142};
    143
    144struct rtw_watch_dog_iter_data {
    145	struct rtw_dev *rtwdev;
    146	struct rtw_vif *rtwvif;
    147};
    148
    149static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif)
    150{
    151	struct rtw_bf_info *bf_info = &rtwdev->bf_info;
    152	u8 fix_rate_enable = 0;
    153	u8 new_csi_rate_idx;
    154
    155	if (rtwvif->bfee.role != RTW_BFEE_SU &&
    156	    rtwvif->bfee.role != RTW_BFEE_MU)
    157		return;
    158
    159	rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi,
    160			      bf_info->cur_csi_rpt_rate,
    161			      fix_rate_enable, &new_csi_rate_idx);
    162
    163	if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate)
    164		bf_info->cur_csi_rpt_rate = new_csi_rate_idx;
    165}
    166
    167static void rtw_vif_watch_dog_iter(void *data, u8 *mac,
    168				   struct ieee80211_vif *vif)
    169{
    170	struct rtw_watch_dog_iter_data *iter_data = data;
    171	struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
    172
    173	if (vif->type == NL80211_IFTYPE_STATION)
    174		if (vif->bss_conf.assoc)
    175			iter_data->rtwvif = rtwvif;
    176
    177	rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif);
    178
    179	rtwvif->stats.tx_unicast = 0;
    180	rtwvif->stats.rx_unicast = 0;
    181	rtwvif->stats.tx_cnt = 0;
    182	rtwvif->stats.rx_cnt = 0;
    183}
    184
    185/* process TX/RX statistics periodically for hardware,
    186 * the information helps hardware to enhance performance
    187 */
    188static void rtw_watch_dog_work(struct work_struct *work)
    189{
    190	struct rtw_dev *rtwdev = container_of(work, struct rtw_dev,
    191					      watch_dog_work.work);
    192	struct rtw_traffic_stats *stats = &rtwdev->stats;
    193	struct rtw_watch_dog_iter_data data = {};
    194	bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
    195	bool ps_active;
    196
    197	mutex_lock(&rtwdev->mutex);
    198
    199	if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags))
    200		goto unlock;
    201
    202	ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work,
    203				     RTW_WATCH_DOG_DELAY_TIME);
    204
    205	if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100)
    206		set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
    207	else
    208		clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
    209
    210	rtw_coex_wl_status_check(rtwdev);
    211	rtw_coex_query_bt_hid_list(rtwdev);
    212
    213	if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags))
    214		rtw_coex_wl_status_change_notify(rtwdev, 0);
    215
    216	if (stats->tx_cnt > RTW_LPS_THRESHOLD ||
    217	    stats->rx_cnt > RTW_LPS_THRESHOLD)
    218		ps_active = true;
    219	else
    220		ps_active = false;
    221
    222	ewma_tp_add(&stats->tx_ewma_tp,
    223		    (u32)(stats->tx_unicast >> RTW_TP_SHIFT));
    224	ewma_tp_add(&stats->rx_ewma_tp,
    225		    (u32)(stats->rx_unicast >> RTW_TP_SHIFT));
    226	stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp);
    227	stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp);
    228
    229	/* reset tx/rx statictics */
    230	stats->tx_unicast = 0;
    231	stats->rx_unicast = 0;
    232	stats->tx_cnt = 0;
    233	stats->rx_cnt = 0;
    234
    235	if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
    236		goto unlock;
    237
    238	/* make sure BB/RF is working for dynamic mech */
    239	rtw_leave_lps(rtwdev);
    240
    241	rtw_phy_dynamic_mechanism(rtwdev);
    242
    243	data.rtwdev = rtwdev;
    244	/* use atomic version to avoid taking local->iflist_mtx mutex */
    245	rtw_iterate_vifs_atomic(rtwdev, rtw_vif_watch_dog_iter, &data);
    246
    247	/* fw supports only one station associated to enter lps, if there are
    248	 * more than two stations associated to the AP, then we can not enter
    249	 * lps, because fw does not handle the overlapped beacon interval
    250	 *
    251	 * mac80211 should iterate vifs and determine if driver can enter
    252	 * ps by passing IEEE80211_CONF_PS to us, all we need to do is to
    253	 * get that vif and check if device is having traffic more than the
    254	 * threshold.
    255	 */
    256	if (rtwdev->ps_enabled && data.rtwvif && !ps_active &&
    257	    !rtwdev->beacon_loss)
    258		rtw_enter_lps(rtwdev, data.rtwvif->port);
    259
    260	rtwdev->watch_dog_cnt++;
    261
    262unlock:
    263	mutex_unlock(&rtwdev->mutex);
    264}
    265
    266static void rtw_c2h_work(struct work_struct *work)
    267{
    268	struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work);
    269	struct sk_buff *skb, *tmp;
    270
    271	skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) {
    272		skb_unlink(skb, &rtwdev->c2h_queue);
    273		rtw_fw_c2h_cmd_handle(rtwdev, skb);
    274		dev_kfree_skb_any(skb);
    275	}
    276}
    277
    278static void rtw_ips_work(struct work_struct *work)
    279{
    280	struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ips_work);
    281
    282	mutex_lock(&rtwdev->mutex);
    283	if (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)
    284		rtw_enter_ips(rtwdev);
    285	mutex_unlock(&rtwdev->mutex);
    286}
    287
    288static u8 rtw_acquire_macid(struct rtw_dev *rtwdev)
    289{
    290	unsigned long mac_id;
    291
    292	mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM);
    293	if (mac_id < RTW_MAX_MAC_ID_NUM)
    294		set_bit(mac_id, rtwdev->mac_id_map);
    295
    296	return mac_id;
    297}
    298
    299int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
    300		struct ieee80211_vif *vif)
    301{
    302	struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
    303	int i;
    304
    305	si->mac_id = rtw_acquire_macid(rtwdev);
    306	if (si->mac_id >= RTW_MAX_MAC_ID_NUM)
    307		return -ENOSPC;
    308
    309	si->sta = sta;
    310	si->vif = vif;
    311	si->init_ra_lv = 1;
    312	ewma_rssi_init(&si->avg_rssi);
    313	for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
    314		rtw_txq_init(rtwdev, sta->txq[i]);
    315
    316	rtw_update_sta_info(rtwdev, si, true);
    317	rtw_fw_media_status_report(rtwdev, si->mac_id, true);
    318
    319	rtwdev->sta_cnt++;
    320	rtwdev->beacon_loss = false;
    321	rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM joined with macid %d\n",
    322		sta->addr, si->mac_id);
    323
    324	return 0;
    325}
    326
    327void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
    328		    bool fw_exist)
    329{
    330	struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
    331	int i;
    332
    333	rtw_release_macid(rtwdev, si->mac_id);
    334	if (fw_exist)
    335		rtw_fw_media_status_report(rtwdev, si->mac_id, false);
    336
    337	for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
    338		rtw_txq_cleanup(rtwdev, sta->txq[i]);
    339
    340	kfree(si->mask);
    341
    342	rtwdev->sta_cnt--;
    343	rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM with macid %d left\n",
    344		sta->addr, si->mac_id);
    345}
    346
    347struct rtw_fwcd_hdr {
    348	u32 item;
    349	u32 size;
    350	u32 padding1;
    351	u32 padding2;
    352} __packed;
    353
    354static int rtw_fwcd_prep(struct rtw_dev *rtwdev)
    355{
    356	struct rtw_chip_info *chip = rtwdev->chip;
    357	struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
    358	const struct rtw_fwcd_segs *segs = chip->fwcd_segs;
    359	u32 prep_size = chip->fw_rxff_size + sizeof(struct rtw_fwcd_hdr);
    360	u8 i;
    361
    362	if (segs) {
    363		prep_size += segs->num * sizeof(struct rtw_fwcd_hdr);
    364
    365		for (i = 0; i < segs->num; i++)
    366			prep_size += segs->segs[i];
    367	}
    368
    369	desc->data = vmalloc(prep_size);
    370	if (!desc->data)
    371		return -ENOMEM;
    372
    373	desc->size = prep_size;
    374	desc->next = desc->data;
    375
    376	return 0;
    377}
    378
    379static u8 *rtw_fwcd_next(struct rtw_dev *rtwdev, u32 item, u32 size)
    380{
    381	struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
    382	struct rtw_fwcd_hdr *hdr;
    383	u8 *next;
    384
    385	if (!desc->data) {
    386		rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared successfully\n");
    387		return NULL;
    388	}
    389
    390	next = desc->next + sizeof(struct rtw_fwcd_hdr);
    391	if (next - desc->data + size > desc->size) {
    392		rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared enough\n");
    393		return NULL;
    394	}
    395
    396	hdr = (struct rtw_fwcd_hdr *)(desc->next);
    397	hdr->item = item;
    398	hdr->size = size;
    399	hdr->padding1 = 0x01234567;
    400	hdr->padding2 = 0x89abcdef;
    401	desc->next = next + size;
    402
    403	return next;
    404}
    405
    406static void rtw_fwcd_dump(struct rtw_dev *rtwdev)
    407{
    408	struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
    409
    410	rtw_dbg(rtwdev, RTW_DBG_FW, "dump fwcd\n");
    411
    412	/* Data will be freed after lifetime of device coredump. After calling
    413	 * dev_coredump, data is supposed to be handled by the device coredump
    414	 * framework. Note that a new dump will be discarded if a previous one
    415	 * hasn't been released yet.
    416	 */
    417	dev_coredumpv(rtwdev->dev, desc->data, desc->size, GFP_KERNEL);
    418}
    419
    420static void rtw_fwcd_free(struct rtw_dev *rtwdev, bool free_self)
    421{
    422	struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
    423
    424	if (free_self) {
    425		rtw_dbg(rtwdev, RTW_DBG_FW, "free fwcd by self\n");
    426		vfree(desc->data);
    427	}
    428
    429	desc->data = NULL;
    430	desc->next = NULL;
    431}
    432
    433static int rtw_fw_dump_crash_log(struct rtw_dev *rtwdev)
    434{
    435	u32 size = rtwdev->chip->fw_rxff_size;
    436	u32 *buf;
    437	u8 seq;
    438
    439	buf = (u32 *)rtw_fwcd_next(rtwdev, RTW_FWCD_TLV, size);
    440	if (!buf)
    441		return -ENOMEM;
    442
    443	if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) {
    444		rtw_dbg(rtwdev, RTW_DBG_FW, "dump fw fifo fail\n");
    445		return -EINVAL;
    446	}
    447
    448	if (GET_FW_DUMP_LEN(buf) == 0) {
    449		rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's length is 0\n");
    450		return -EINVAL;
    451	}
    452
    453	seq = GET_FW_DUMP_SEQ(buf);
    454	if (seq > 0) {
    455		rtw_dbg(rtwdev, RTW_DBG_FW,
    456			"fw crash dump's seq is wrong: %d\n", seq);
    457		return -EINVAL;
    458	}
    459
    460	return 0;
    461}
    462
    463int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size,
    464		u32 fwcd_item)
    465{
    466	u32 rxff = rtwdev->chip->fw_rxff_size;
    467	u32 dump_size, done_size = 0;
    468	u8 *buf;
    469	int ret;
    470
    471	buf = rtw_fwcd_next(rtwdev, fwcd_item, size);
    472	if (!buf)
    473		return -ENOMEM;
    474
    475	while (size) {
    476		dump_size = size > rxff ? rxff : size;
    477
    478		ret = rtw_ddma_to_fw_fifo(rtwdev, ocp_src + done_size,
    479					  dump_size);
    480		if (ret) {
    481			rtw_err(rtwdev,
    482				"ddma fw 0x%x [+0x%x] to fw fifo fail\n",
    483				ocp_src, done_size);
    484			return ret;
    485		}
    486
    487		ret = rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0,
    488				       dump_size, (u32 *)(buf + done_size));
    489		if (ret) {
    490			rtw_err(rtwdev,
    491				"dump fw 0x%x [+0x%x] from fw fifo fail\n",
    492				ocp_src, done_size);
    493			return ret;
    494		}
    495
    496		size -= dump_size;
    497		done_size += dump_size;
    498	}
    499
    500	return 0;
    501}
    502EXPORT_SYMBOL(rtw_dump_fw);
    503
    504int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size)
    505{
    506	u8 *buf;
    507	u32 i;
    508
    509	if (addr & 0x3) {
    510		WARN(1, "should be 4-byte aligned, addr = 0x%08x\n", addr);
    511		return -EINVAL;
    512	}
    513
    514	buf = rtw_fwcd_next(rtwdev, RTW_FWCD_REG, size);
    515	if (!buf)
    516		return -ENOMEM;
    517
    518	for (i = 0; i < size; i += 4)
    519		*(u32 *)(buf + i) = rtw_read32(rtwdev, addr + i);
    520
    521	return 0;
    522}
    523EXPORT_SYMBOL(rtw_dump_reg);
    524
    525void rtw_vif_assoc_changed(struct rtw_vif *rtwvif,
    526			   struct ieee80211_bss_conf *conf)
    527{
    528	if (conf && conf->assoc) {
    529		rtwvif->aid = conf->aid;
    530		rtwvif->net_type = RTW_NET_MGD_LINKED;
    531	} else {
    532		rtwvif->aid = 0;
    533		rtwvif->net_type = RTW_NET_NO_LINK;
    534	}
    535}
    536
    537static void rtw_reset_key_iter(struct ieee80211_hw *hw,
    538			       struct ieee80211_vif *vif,
    539			       struct ieee80211_sta *sta,
    540			       struct ieee80211_key_conf *key,
    541			       void *data)
    542{
    543	struct rtw_dev *rtwdev = (struct rtw_dev *)data;
    544	struct rtw_sec_desc *sec = &rtwdev->sec;
    545
    546	rtw_sec_clear_cam(rtwdev, sec, key->hw_key_idx);
    547}
    548
    549static void rtw_reset_sta_iter(void *data, struct ieee80211_sta *sta)
    550{
    551	struct rtw_dev *rtwdev = (struct rtw_dev *)data;
    552
    553	if (rtwdev->sta_cnt == 0) {
    554		rtw_warn(rtwdev, "sta count before reset should not be 0\n");
    555		return;
    556	}
    557	rtw_sta_remove(rtwdev, sta, false);
    558}
    559
    560static void rtw_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
    561{
    562	struct rtw_dev *rtwdev = (struct rtw_dev *)data;
    563	struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
    564
    565	rtw_bf_disassoc(rtwdev, vif, NULL);
    566	rtw_vif_assoc_changed(rtwvif, NULL);
    567	rtw_txq_cleanup(rtwdev, vif->txq);
    568}
    569
    570void rtw_fw_recovery(struct rtw_dev *rtwdev)
    571{
    572	if (!test_bit(RTW_FLAG_RESTARTING, rtwdev->flags))
    573		ieee80211_queue_work(rtwdev->hw, &rtwdev->fw_recovery_work);
    574}
    575
    576static void __fw_recovery_work(struct rtw_dev *rtwdev)
    577{
    578	int ret = 0;
    579
    580	set_bit(RTW_FLAG_RESTARTING, rtwdev->flags);
    581	clear_bit(RTW_FLAG_RESTART_TRIGGERING, rtwdev->flags);
    582
    583	ret = rtw_fwcd_prep(rtwdev);
    584	if (ret)
    585		goto free;
    586	ret = rtw_fw_dump_crash_log(rtwdev);
    587	if (ret)
    588		goto free;
    589	ret = rtw_chip_dump_fw_crash(rtwdev);
    590	if (ret)
    591		goto free;
    592
    593	rtw_fwcd_dump(rtwdev);
    594free:
    595	rtw_fwcd_free(rtwdev, !!ret);
    596	rtw_write8(rtwdev, REG_MCU_TST_CFG, 0);
    597
    598	WARN(1, "firmware crash, start reset and recover\n");
    599
    600	rcu_read_lock();
    601	rtw_iterate_keys_rcu(rtwdev, NULL, rtw_reset_key_iter, rtwdev);
    602	rcu_read_unlock();
    603	rtw_iterate_stas_atomic(rtwdev, rtw_reset_sta_iter, rtwdev);
    604	rtw_iterate_vifs_atomic(rtwdev, rtw_reset_vif_iter, rtwdev);
    605	rtw_enter_ips(rtwdev);
    606}
    607
    608static void rtw_fw_recovery_work(struct work_struct *work)
    609{
    610	struct rtw_dev *rtwdev = container_of(work, struct rtw_dev,
    611					      fw_recovery_work);
    612
    613	mutex_lock(&rtwdev->mutex);
    614	__fw_recovery_work(rtwdev);
    615	mutex_unlock(&rtwdev->mutex);
    616
    617	ieee80211_restart_hw(rtwdev->hw);
    618}
    619
    620struct rtw_txq_ba_iter_data {
    621};
    622
    623static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta)
    624{
    625	struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
    626	int ret;
    627	u8 tid;
    628
    629	tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS);
    630	while (tid != IEEE80211_NUM_TIDS) {
    631		clear_bit(tid, si->tid_ba);
    632		ret = ieee80211_start_tx_ba_session(sta, tid, 0);
    633		if (ret == -EINVAL) {
    634			struct ieee80211_txq *txq;
    635			struct rtw_txq *rtwtxq;
    636
    637			txq = sta->txq[tid];
    638			rtwtxq = (struct rtw_txq *)txq->drv_priv;
    639			set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags);
    640		}
    641
    642		tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS);
    643	}
    644}
    645
    646static void rtw_txq_ba_work(struct work_struct *work)
    647{
    648	struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work);
    649	struct rtw_txq_ba_iter_data data;
    650
    651	rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data);
    652}
    653
    654void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel)
    655{
    656	if (IS_CH_2G_BAND(channel))
    657		pkt_stat->band = NL80211_BAND_2GHZ;
    658	else if (IS_CH_5G_BAND(channel))
    659		pkt_stat->band = NL80211_BAND_5GHZ;
    660	else
    661		return;
    662
    663	pkt_stat->freq = ieee80211_channel_to_frequency(channel, pkt_stat->band);
    664}
    665EXPORT_SYMBOL(rtw_set_rx_freq_band);
    666
    667void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period)
    668{
    669	rtw_write32_set(rtwdev, REG_TCR, BIT_TCR_UPDATE_TIMIE);
    670	rtw_write8(rtwdev, REG_DTIM_COUNTER_ROOT, dtim_period - 1);
    671}
    672
    673void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
    674			    struct rtw_channel_params *chan_params)
    675{
    676	struct ieee80211_channel *channel = chandef->chan;
    677	enum nl80211_chan_width width = chandef->width;
    678	u8 *cch_by_bw = chan_params->cch_by_bw;
    679	u32 primary_freq, center_freq;
    680	u8 center_chan;
    681	u8 bandwidth = RTW_CHANNEL_WIDTH_20;
    682	u8 primary_chan_idx = 0;
    683	u8 i;
    684
    685	center_chan = channel->hw_value;
    686	primary_freq = channel->center_freq;
    687	center_freq = chandef->center_freq1;
    688
    689	/* assign the center channel used while 20M bw is selected */
    690	cch_by_bw[RTW_CHANNEL_WIDTH_20] = channel->hw_value;
    691
    692	switch (width) {
    693	case NL80211_CHAN_WIDTH_20_NOHT:
    694	case NL80211_CHAN_WIDTH_20:
    695		bandwidth = RTW_CHANNEL_WIDTH_20;
    696		primary_chan_idx = RTW_SC_DONT_CARE;
    697		break;
    698	case NL80211_CHAN_WIDTH_40:
    699		bandwidth = RTW_CHANNEL_WIDTH_40;
    700		if (primary_freq > center_freq) {
    701			primary_chan_idx = RTW_SC_20_UPPER;
    702			center_chan -= 2;
    703		} else {
    704			primary_chan_idx = RTW_SC_20_LOWER;
    705			center_chan += 2;
    706		}
    707		break;
    708	case NL80211_CHAN_WIDTH_80:
    709		bandwidth = RTW_CHANNEL_WIDTH_80;
    710		if (primary_freq > center_freq) {
    711			if (primary_freq - center_freq == 10) {
    712				primary_chan_idx = RTW_SC_20_UPPER;
    713				center_chan -= 2;
    714			} else {
    715				primary_chan_idx = RTW_SC_20_UPMOST;
    716				center_chan -= 6;
    717			}
    718			/* assign the center channel used
    719			 * while 40M bw is selected
    720			 */
    721			cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan + 4;
    722		} else {
    723			if (center_freq - primary_freq == 10) {
    724				primary_chan_idx = RTW_SC_20_LOWER;
    725				center_chan += 2;
    726			} else {
    727				primary_chan_idx = RTW_SC_20_LOWEST;
    728				center_chan += 6;
    729			}
    730			/* assign the center channel used
    731			 * while 40M bw is selected
    732			 */
    733			cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan - 4;
    734		}
    735		break;
    736	default:
    737		center_chan = 0;
    738		break;
    739	}
    740
    741	chan_params->center_chan = center_chan;
    742	chan_params->bandwidth = bandwidth;
    743	chan_params->primary_chan_idx = primary_chan_idx;
    744
    745	/* assign the center channel used while current bw is selected */
    746	cch_by_bw[bandwidth] = center_chan;
    747
    748	for (i = bandwidth + 1; i <= RTW_MAX_CHANNEL_WIDTH; i++)
    749		cch_by_bw[i] = 0;
    750}
    751
    752void rtw_set_channel(struct rtw_dev *rtwdev)
    753{
    754	struct ieee80211_hw *hw = rtwdev->hw;
    755	struct rtw_hal *hal = &rtwdev->hal;
    756	struct rtw_chip_info *chip = rtwdev->chip;
    757	struct rtw_channel_params ch_param;
    758	u8 center_chan, bandwidth, primary_chan_idx;
    759	u8 i;
    760
    761	rtw_get_channel_params(&hw->conf.chandef, &ch_param);
    762	if (WARN(ch_param.center_chan == 0, "Invalid channel\n"))
    763		return;
    764
    765	center_chan = ch_param.center_chan;
    766	bandwidth = ch_param.bandwidth;
    767	primary_chan_idx = ch_param.primary_chan_idx;
    768
    769	hal->current_band_width = bandwidth;
    770	hal->current_channel = center_chan;
    771	hal->current_primary_channel_index = primary_chan_idx;
    772	hal->current_band_type = center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G;
    773
    774	switch (center_chan) {
    775	case 1 ... 14:
    776		hal->sar_band = RTW_SAR_BAND_0;
    777		break;
    778	case 36 ... 64:
    779		hal->sar_band = RTW_SAR_BAND_1;
    780		break;
    781	case 100 ... 144:
    782		hal->sar_band = RTW_SAR_BAND_3;
    783		break;
    784	case 149 ... 177:
    785		hal->sar_band = RTW_SAR_BAND_4;
    786		break;
    787	default:
    788		WARN(1, "unknown ch(%u) to SAR band\n", center_chan);
    789		hal->sar_band = RTW_SAR_BAND_0;
    790		break;
    791	}
    792
    793	for (i = RTW_CHANNEL_WIDTH_20; i <= RTW_MAX_CHANNEL_WIDTH; i++)
    794		hal->cch_by_bw[i] = ch_param.cch_by_bw[i];
    795
    796	chip->ops->set_channel(rtwdev, center_chan, bandwidth, primary_chan_idx);
    797
    798	if (hal->current_band_type == RTW_BAND_5G) {
    799		rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G);
    800	} else {
    801		if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
    802			rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G);
    803		else
    804			rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN);
    805	}
    806
    807	rtw_phy_set_tx_power_level(rtwdev, center_chan);
    808
    809	/* if the channel isn't set for scanning, we will do RF calibration
    810	 * in ieee80211_ops::mgd_prepare_tx(). Performing the calibration
    811	 * during scanning on each channel takes too long.
    812	 */
    813	if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
    814		rtwdev->need_rfk = true;
    815}
    816
    817void rtw_chip_prepare_tx(struct rtw_dev *rtwdev)
    818{
    819	struct rtw_chip_info *chip = rtwdev->chip;
    820
    821	if (rtwdev->need_rfk) {
    822		rtwdev->need_rfk = false;
    823		chip->ops->phy_calibration(rtwdev);
    824	}
    825}
    826
    827static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr)
    828{
    829	int i;
    830
    831	for (i = 0; i < ETH_ALEN; i++)
    832		rtw_write8(rtwdev, start + i, addr[i]);
    833}
    834
    835void rtw_vif_port_config(struct rtw_dev *rtwdev,
    836			 struct rtw_vif *rtwvif,
    837			 u32 config)
    838{
    839	u32 addr, mask;
    840
    841	if (config & PORT_SET_MAC_ADDR) {
    842		addr = rtwvif->conf->mac_addr.addr;
    843		rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr);
    844	}
    845	if (config & PORT_SET_BSSID) {
    846		addr = rtwvif->conf->bssid.addr;
    847		rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid);
    848	}
    849	if (config & PORT_SET_NET_TYPE) {
    850		addr = rtwvif->conf->net_type.addr;
    851		mask = rtwvif->conf->net_type.mask;
    852		rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type);
    853	}
    854	if (config & PORT_SET_AID) {
    855		addr = rtwvif->conf->aid.addr;
    856		mask = rtwvif->conf->aid.mask;
    857		rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid);
    858	}
    859	if (config & PORT_SET_BCN_CTRL) {
    860		addr = rtwvif->conf->bcn_ctrl.addr;
    861		mask = rtwvif->conf->bcn_ctrl.mask;
    862		rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl);
    863	}
    864}
    865
    866static u8 hw_bw_cap_to_bitamp(u8 bw_cap)
    867{
    868	u8 bw = 0;
    869
    870	switch (bw_cap) {
    871	case EFUSE_HW_CAP_IGNORE:
    872	case EFUSE_HW_CAP_SUPP_BW80:
    873		bw |= BIT(RTW_CHANNEL_WIDTH_80);
    874		fallthrough;
    875	case EFUSE_HW_CAP_SUPP_BW40:
    876		bw |= BIT(RTW_CHANNEL_WIDTH_40);
    877		fallthrough;
    878	default:
    879		bw |= BIT(RTW_CHANNEL_WIDTH_20);
    880		break;
    881	}
    882
    883	return bw;
    884}
    885
    886static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num)
    887{
    888	struct rtw_hal *hal = &rtwdev->hal;
    889	struct rtw_chip_info *chip = rtwdev->chip;
    890
    891	if (hw_ant_num == EFUSE_HW_CAP_IGNORE ||
    892	    hw_ant_num >= hal->rf_path_num)
    893		return;
    894
    895	switch (hw_ant_num) {
    896	case 1:
    897		hal->rf_type = RF_1T1R;
    898		hal->rf_path_num = 1;
    899		if (!chip->fix_rf_phy_num)
    900			hal->rf_phy_num = hal->rf_path_num;
    901		hal->antenna_tx = BB_PATH_A;
    902		hal->antenna_rx = BB_PATH_A;
    903		break;
    904	default:
    905		WARN(1, "invalid hw configuration from efuse\n");
    906		break;
    907	}
    908}
    909
    910static u64 get_vht_ra_mask(struct ieee80211_sta *sta)
    911{
    912	u64 ra_mask = 0;
    913	u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map);
    914	u8 vht_mcs_cap;
    915	int i, nss;
    916
    917	/* 4SS, every two bits for MCS7/8/9 */
    918	for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) {
    919		vht_mcs_cap = mcs_map & 0x3;
    920		switch (vht_mcs_cap) {
    921		case 2: /* MCS9 */
    922			ra_mask |= 0x3ffULL << nss;
    923			break;
    924		case 1: /* MCS8 */
    925			ra_mask |= 0x1ffULL << nss;
    926			break;
    927		case 0: /* MCS7 */
    928			ra_mask |= 0x0ffULL << nss;
    929			break;
    930		default:
    931			break;
    932		}
    933	}
    934
    935	return ra_mask;
    936}
    937
    938static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num)
    939{
    940	u8 rate_id = 0;
    941
    942	switch (wireless_set) {
    943	case WIRELESS_CCK:
    944		rate_id = RTW_RATEID_B_20M;
    945		break;
    946	case WIRELESS_OFDM:
    947		rate_id = RTW_RATEID_G;
    948		break;
    949	case WIRELESS_CCK | WIRELESS_OFDM:
    950		rate_id = RTW_RATEID_BG;
    951		break;
    952	case WIRELESS_OFDM | WIRELESS_HT:
    953		if (tx_num == 1)
    954			rate_id = RTW_RATEID_GN_N1SS;
    955		else if (tx_num == 2)
    956			rate_id = RTW_RATEID_GN_N2SS;
    957		else if (tx_num == 3)
    958			rate_id = RTW_RATEID_ARFR5_N_3SS;
    959		break;
    960	case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT:
    961		if (bw_mode == RTW_CHANNEL_WIDTH_40) {
    962			if (tx_num == 1)
    963				rate_id = RTW_RATEID_BGN_40M_1SS;
    964			else if (tx_num == 2)
    965				rate_id = RTW_RATEID_BGN_40M_2SS;
    966			else if (tx_num == 3)
    967				rate_id = RTW_RATEID_ARFR5_N_3SS;
    968			else if (tx_num == 4)
    969				rate_id = RTW_RATEID_ARFR7_N_4SS;
    970		} else {
    971			if (tx_num == 1)
    972				rate_id = RTW_RATEID_BGN_20M_1SS;
    973			else if (tx_num == 2)
    974				rate_id = RTW_RATEID_BGN_20M_2SS;
    975			else if (tx_num == 3)
    976				rate_id = RTW_RATEID_ARFR5_N_3SS;
    977			else if (tx_num == 4)
    978				rate_id = RTW_RATEID_ARFR7_N_4SS;
    979		}
    980		break;
    981	case WIRELESS_OFDM | WIRELESS_VHT:
    982		if (tx_num == 1)
    983			rate_id = RTW_RATEID_ARFR1_AC_1SS;
    984		else if (tx_num == 2)
    985			rate_id = RTW_RATEID_ARFR0_AC_2SS;
    986		else if (tx_num == 3)
    987			rate_id = RTW_RATEID_ARFR4_AC_3SS;
    988		else if (tx_num == 4)
    989			rate_id = RTW_RATEID_ARFR6_AC_4SS;
    990		break;
    991	case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT:
    992		if (bw_mode >= RTW_CHANNEL_WIDTH_80) {
    993			if (tx_num == 1)
    994				rate_id = RTW_RATEID_ARFR1_AC_1SS;
    995			else if (tx_num == 2)
    996				rate_id = RTW_RATEID_ARFR0_AC_2SS;
    997			else if (tx_num == 3)
    998				rate_id = RTW_RATEID_ARFR4_AC_3SS;
    999			else if (tx_num == 4)
   1000				rate_id = RTW_RATEID_ARFR6_AC_4SS;
   1001		} else {
   1002			if (tx_num == 1)
   1003				rate_id = RTW_RATEID_ARFR2_AC_2G_1SS;
   1004			else if (tx_num == 2)
   1005				rate_id = RTW_RATEID_ARFR3_AC_2G_2SS;
   1006			else if (tx_num == 3)
   1007				rate_id = RTW_RATEID_ARFR4_AC_3SS;
   1008			else if (tx_num == 4)
   1009				rate_id = RTW_RATEID_ARFR6_AC_4SS;
   1010		}
   1011		break;
   1012	default:
   1013		break;
   1014	}
   1015
   1016	return rate_id;
   1017}
   1018
   1019#define RA_MASK_CCK_RATES	0x0000f
   1020#define RA_MASK_OFDM_RATES	0x00ff0
   1021#define RA_MASK_HT_RATES_1SS	(0xff000ULL << 0)
   1022#define RA_MASK_HT_RATES_2SS	(0xff000ULL << 8)
   1023#define RA_MASK_HT_RATES_3SS	(0xff000ULL << 16)
   1024#define RA_MASK_HT_RATES	(RA_MASK_HT_RATES_1SS | \
   1025				 RA_MASK_HT_RATES_2SS | \
   1026				 RA_MASK_HT_RATES_3SS)
   1027#define RA_MASK_VHT_RATES_1SS	(0x3ff000ULL << 0)
   1028#define RA_MASK_VHT_RATES_2SS	(0x3ff000ULL << 10)
   1029#define RA_MASK_VHT_RATES_3SS	(0x3ff000ULL << 20)
   1030#define RA_MASK_VHT_RATES	(RA_MASK_VHT_RATES_1SS | \
   1031				 RA_MASK_VHT_RATES_2SS | \
   1032				 RA_MASK_VHT_RATES_3SS)
   1033#define RA_MASK_CCK_IN_BG	0x00005
   1034#define RA_MASK_CCK_IN_HT	0x00005
   1035#define RA_MASK_CCK_IN_VHT	0x00005
   1036#define RA_MASK_OFDM_IN_VHT	0x00010
   1037#define RA_MASK_OFDM_IN_HT_2G	0x00010
   1038#define RA_MASK_OFDM_IN_HT_5G	0x00030
   1039
   1040static u64 rtw_rate_mask_rssi(struct rtw_sta_info *si, u8 wireless_set)
   1041{
   1042	u8 rssi_level = si->rssi_level;
   1043
   1044	if (wireless_set == WIRELESS_CCK)
   1045		return 0xffffffffffffffffULL;
   1046
   1047	if (rssi_level == 0)
   1048		return 0xffffffffffffffffULL;
   1049	else if (rssi_level == 1)
   1050		return 0xfffffffffffffff0ULL;
   1051	else if (rssi_level == 2)
   1052		return 0xffffffffffffefe0ULL;
   1053	else if (rssi_level == 3)
   1054		return 0xffffffffffffcfc0ULL;
   1055	else if (rssi_level == 4)
   1056		return 0xffffffffffff8f80ULL;
   1057	else
   1058		return 0xffffffffffff0f00ULL;
   1059}
   1060
   1061static u64 rtw_rate_mask_recover(u64 ra_mask, u64 ra_mask_bak)
   1062{
   1063	if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0)
   1064		ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
   1065
   1066	if (ra_mask == 0)
   1067		ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
   1068
   1069	return ra_mask;
   1070}
   1071
   1072static u64 rtw_rate_mask_cfg(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
   1073			     u64 ra_mask, bool is_vht_enable)
   1074{
   1075	struct rtw_hal *hal = &rtwdev->hal;
   1076	const struct cfg80211_bitrate_mask *mask = si->mask;
   1077	u64 cfg_mask = GENMASK_ULL(63, 0);
   1078	u8 band;
   1079
   1080	if (!si->use_cfg_mask)
   1081		return ra_mask;
   1082
   1083	band = hal->current_band_type;
   1084	if (band == RTW_BAND_2G) {
   1085		band = NL80211_BAND_2GHZ;
   1086		cfg_mask = mask->control[band].legacy;
   1087	} else if (band == RTW_BAND_5G) {
   1088		band = NL80211_BAND_5GHZ;
   1089		cfg_mask = u64_encode_bits(mask->control[band].legacy,
   1090					   RA_MASK_OFDM_RATES);
   1091	}
   1092
   1093	if (!is_vht_enable) {
   1094		if (ra_mask & RA_MASK_HT_RATES_1SS)
   1095			cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0],
   1096						    RA_MASK_HT_RATES_1SS);
   1097		if (ra_mask & RA_MASK_HT_RATES_2SS)
   1098			cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1],
   1099						    RA_MASK_HT_RATES_2SS);
   1100	} else {
   1101		if (ra_mask & RA_MASK_VHT_RATES_1SS)
   1102			cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0],
   1103						    RA_MASK_VHT_RATES_1SS);
   1104		if (ra_mask & RA_MASK_VHT_RATES_2SS)
   1105			cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1],
   1106						    RA_MASK_VHT_RATES_2SS);
   1107	}
   1108
   1109	ra_mask &= cfg_mask;
   1110
   1111	return ra_mask;
   1112}
   1113
   1114void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
   1115			 bool reset_ra_mask)
   1116{
   1117	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
   1118	struct ieee80211_sta *sta = si->sta;
   1119	struct rtw_efuse *efuse = &rtwdev->efuse;
   1120	struct rtw_hal *hal = &rtwdev->hal;
   1121	u8 wireless_set;
   1122	u8 bw_mode;
   1123	u8 rate_id;
   1124	u8 rf_type = RF_1T1R;
   1125	u8 stbc_en = 0;
   1126	u8 ldpc_en = 0;
   1127	u8 tx_num = 1;
   1128	u64 ra_mask = 0;
   1129	u64 ra_mask_bak = 0;
   1130	bool is_vht_enable = false;
   1131	bool is_support_sgi = false;
   1132
   1133	if (sta->deflink.vht_cap.vht_supported) {
   1134		is_vht_enable = true;
   1135		ra_mask |= get_vht_ra_mask(sta);
   1136		if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK)
   1137			stbc_en = VHT_STBC_EN;
   1138		if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC)
   1139			ldpc_en = VHT_LDPC_EN;
   1140	} else if (sta->deflink.ht_cap.ht_supported) {
   1141		ra_mask |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20) |
   1142			   (sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
   1143		if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC)
   1144			stbc_en = HT_STBC_EN;
   1145		if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING)
   1146			ldpc_en = HT_LDPC_EN;
   1147	}
   1148
   1149	if (efuse->hw_cap.nss == 1 || rtwdev->hal.txrx_1ss)
   1150		ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS;
   1151
   1152	if (hal->current_band_type == RTW_BAND_5G) {
   1153		ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4;
   1154		ra_mask_bak = ra_mask;
   1155		if (sta->deflink.vht_cap.vht_supported) {
   1156			ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT;
   1157			wireless_set = WIRELESS_OFDM | WIRELESS_VHT;
   1158		} else if (sta->deflink.ht_cap.ht_supported) {
   1159			ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G;
   1160			wireless_set = WIRELESS_OFDM | WIRELESS_HT;
   1161		} else {
   1162			wireless_set = WIRELESS_OFDM;
   1163		}
   1164		dm_info->rrsr_val_init = RRSR_INIT_5G;
   1165	} else if (hal->current_band_type == RTW_BAND_2G) {
   1166		ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ];
   1167		ra_mask_bak = ra_mask;
   1168		if (sta->deflink.vht_cap.vht_supported) {
   1169			ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT |
   1170				   RA_MASK_OFDM_IN_VHT;
   1171			wireless_set = WIRELESS_CCK | WIRELESS_OFDM |
   1172				       WIRELESS_HT | WIRELESS_VHT;
   1173		} else if (sta->deflink.ht_cap.ht_supported) {
   1174			ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT |
   1175				   RA_MASK_OFDM_IN_HT_2G;
   1176			wireless_set = WIRELESS_CCK | WIRELESS_OFDM |
   1177				       WIRELESS_HT;
   1178		} else if (sta->deflink.supp_rates[0] <= 0xf) {
   1179			wireless_set = WIRELESS_CCK;
   1180		} else {
   1181			ra_mask &= RA_MASK_OFDM_RATES | RA_MASK_CCK_IN_BG;
   1182			wireless_set = WIRELESS_CCK | WIRELESS_OFDM;
   1183		}
   1184		dm_info->rrsr_val_init = RRSR_INIT_2G;
   1185	} else {
   1186		rtw_err(rtwdev, "Unknown band type\n");
   1187		ra_mask_bak = ra_mask;
   1188		wireless_set = 0;
   1189	}
   1190
   1191	switch (sta->deflink.bandwidth) {
   1192	case IEEE80211_STA_RX_BW_80:
   1193		bw_mode = RTW_CHANNEL_WIDTH_80;
   1194		is_support_sgi = sta->deflink.vht_cap.vht_supported &&
   1195				 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80);
   1196		break;
   1197	case IEEE80211_STA_RX_BW_40:
   1198		bw_mode = RTW_CHANNEL_WIDTH_40;
   1199		is_support_sgi = sta->deflink.ht_cap.ht_supported &&
   1200				 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40);
   1201		break;
   1202	default:
   1203		bw_mode = RTW_CHANNEL_WIDTH_20;
   1204		is_support_sgi = sta->deflink.ht_cap.ht_supported &&
   1205				 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20);
   1206		break;
   1207	}
   1208
   1209	if (sta->deflink.vht_cap.vht_supported && ra_mask & 0xffc00000) {
   1210		tx_num = 2;
   1211		rf_type = RF_2T2R;
   1212	} else if (sta->deflink.ht_cap.ht_supported && ra_mask & 0xfff00000) {
   1213		tx_num = 2;
   1214		rf_type = RF_2T2R;
   1215	}
   1216
   1217	rate_id = get_rate_id(wireless_set, bw_mode, tx_num);
   1218
   1219	ra_mask &= rtw_rate_mask_rssi(si, wireless_set);
   1220	ra_mask = rtw_rate_mask_recover(ra_mask, ra_mask_bak);
   1221	ra_mask = rtw_rate_mask_cfg(rtwdev, si, ra_mask, is_vht_enable);
   1222
   1223	si->bw_mode = bw_mode;
   1224	si->stbc_en = stbc_en;
   1225	si->ldpc_en = ldpc_en;
   1226	si->rf_type = rf_type;
   1227	si->wireless_set = wireless_set;
   1228	si->sgi_enable = is_support_sgi;
   1229	si->vht_enable = is_vht_enable;
   1230	si->ra_mask = ra_mask;
   1231	si->rate_id = rate_id;
   1232
   1233	rtw_fw_send_ra_info(rtwdev, si, reset_ra_mask);
   1234}
   1235
   1236static int rtw_wait_firmware_completion(struct rtw_dev *rtwdev)
   1237{
   1238	struct rtw_chip_info *chip = rtwdev->chip;
   1239	struct rtw_fw_state *fw;
   1240
   1241	fw = &rtwdev->fw;
   1242	wait_for_completion(&fw->completion);
   1243	if (!fw->firmware)
   1244		return -EINVAL;
   1245
   1246	if (chip->wow_fw_name) {
   1247		fw = &rtwdev->wow_fw;
   1248		wait_for_completion(&fw->completion);
   1249		if (!fw->firmware)
   1250			return -EINVAL;
   1251	}
   1252
   1253	return 0;
   1254}
   1255
   1256static enum rtw_lps_deep_mode rtw_update_lps_deep_mode(struct rtw_dev *rtwdev,
   1257						       struct rtw_fw_state *fw)
   1258{
   1259	struct rtw_chip_info *chip = rtwdev->chip;
   1260
   1261	if (rtw_disable_lps_deep_mode || !chip->lps_deep_mode_supported ||
   1262	    !fw->feature)
   1263		return LPS_DEEP_MODE_NONE;
   1264
   1265	if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_PG)) &&
   1266	    rtw_fw_feature_check(fw, FW_FEATURE_PG))
   1267		return LPS_DEEP_MODE_PG;
   1268
   1269	if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_LCLK)) &&
   1270	    rtw_fw_feature_check(fw, FW_FEATURE_LCLK))
   1271		return LPS_DEEP_MODE_LCLK;
   1272
   1273	return LPS_DEEP_MODE_NONE;
   1274}
   1275
   1276static int rtw_power_on(struct rtw_dev *rtwdev)
   1277{
   1278	struct rtw_chip_info *chip = rtwdev->chip;
   1279	struct rtw_fw_state *fw = &rtwdev->fw;
   1280	bool wifi_only;
   1281	int ret;
   1282
   1283	ret = rtw_hci_setup(rtwdev);
   1284	if (ret) {
   1285		rtw_err(rtwdev, "failed to setup hci\n");
   1286		goto err;
   1287	}
   1288
   1289	/* power on MAC before firmware downloaded */
   1290	ret = rtw_mac_power_on(rtwdev);
   1291	if (ret) {
   1292		rtw_err(rtwdev, "failed to power on mac\n");
   1293		goto err;
   1294	}
   1295
   1296	ret = rtw_wait_firmware_completion(rtwdev);
   1297	if (ret) {
   1298		rtw_err(rtwdev, "failed to wait firmware completion\n");
   1299		goto err_off;
   1300	}
   1301
   1302	ret = rtw_download_firmware(rtwdev, fw);
   1303	if (ret) {
   1304		rtw_err(rtwdev, "failed to download firmware\n");
   1305		goto err_off;
   1306	}
   1307
   1308	/* config mac after firmware downloaded */
   1309	ret = rtw_mac_init(rtwdev);
   1310	if (ret) {
   1311		rtw_err(rtwdev, "failed to configure mac\n");
   1312		goto err_off;
   1313	}
   1314
   1315	chip->ops->phy_set_param(rtwdev);
   1316
   1317	ret = rtw_hci_start(rtwdev);
   1318	if (ret) {
   1319		rtw_err(rtwdev, "failed to start hci\n");
   1320		goto err_off;
   1321	}
   1322
   1323	/* send H2C after HCI has started */
   1324	rtw_fw_send_general_info(rtwdev);
   1325	rtw_fw_send_phydm_info(rtwdev);
   1326
   1327	wifi_only = !rtwdev->efuse.btcoex;
   1328	rtw_coex_power_on_setting(rtwdev);
   1329	rtw_coex_init_hw_config(rtwdev, wifi_only);
   1330
   1331	return 0;
   1332
   1333err_off:
   1334	rtw_mac_power_off(rtwdev);
   1335
   1336err:
   1337	return ret;
   1338}
   1339
   1340void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start)
   1341{
   1342	if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_NOTIFY_SCAN))
   1343		return;
   1344
   1345	if (start) {
   1346		rtw_fw_scan_notify(rtwdev, true);
   1347	} else {
   1348		reinit_completion(&rtwdev->fw_scan_density);
   1349		rtw_fw_scan_notify(rtwdev, false);
   1350		if (!wait_for_completion_timeout(&rtwdev->fw_scan_density,
   1351						 SCAN_NOTIFY_TIMEOUT))
   1352			rtw_warn(rtwdev, "firmware failed to report density after scan\n");
   1353	}
   1354}
   1355
   1356void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
   1357			 const u8 *mac_addr, bool hw_scan)
   1358{
   1359	u32 config = 0;
   1360	int ret = 0;
   1361
   1362	rtw_leave_lps(rtwdev);
   1363
   1364	if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) {
   1365		ret = rtw_leave_ips(rtwdev);
   1366		if (ret) {
   1367			rtw_err(rtwdev, "failed to leave idle state\n");
   1368			return;
   1369		}
   1370	}
   1371
   1372	ether_addr_copy(rtwvif->mac_addr, mac_addr);
   1373	config |= PORT_SET_MAC_ADDR;
   1374	rtw_vif_port_config(rtwdev, rtwvif, config);
   1375
   1376	rtw_coex_scan_notify(rtwdev, COEX_SCAN_START);
   1377	rtw_core_fw_scan_notify(rtwdev, true);
   1378
   1379	set_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags);
   1380	set_bit(RTW_FLAG_SCANNING, rtwdev->flags);
   1381}
   1382
   1383void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
   1384			    bool hw_scan)
   1385{
   1386	struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
   1387	u32 config = 0;
   1388
   1389	clear_bit(RTW_FLAG_SCANNING, rtwdev->flags);
   1390	clear_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags);
   1391
   1392	rtw_core_fw_scan_notify(rtwdev, false);
   1393
   1394	ether_addr_copy(rtwvif->mac_addr, vif->addr);
   1395	config |= PORT_SET_MAC_ADDR;
   1396	rtw_vif_port_config(rtwdev, rtwvif, config);
   1397
   1398	rtw_coex_scan_notify(rtwdev, COEX_SCAN_FINISH);
   1399
   1400	if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE))
   1401		ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work);
   1402}
   1403
   1404int rtw_core_start(struct rtw_dev *rtwdev)
   1405{
   1406	int ret;
   1407
   1408	ret = rtw_power_on(rtwdev);
   1409	if (ret)
   1410		return ret;
   1411
   1412	rtw_sec_enable_sec_engine(rtwdev);
   1413
   1414	rtwdev->lps_conf.deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->fw);
   1415	rtwdev->lps_conf.wow_deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->wow_fw);
   1416
   1417	/* rcr reset after powered on */
   1418	rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr);
   1419
   1420	ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work,
   1421				     RTW_WATCH_DOG_DELAY_TIME);
   1422
   1423	set_bit(RTW_FLAG_RUNNING, rtwdev->flags);
   1424
   1425	return 0;
   1426}
   1427
   1428static void rtw_power_off(struct rtw_dev *rtwdev)
   1429{
   1430	rtw_hci_stop(rtwdev);
   1431	rtw_coex_power_off_setting(rtwdev);
   1432	rtw_mac_power_off(rtwdev);
   1433}
   1434
   1435void rtw_core_stop(struct rtw_dev *rtwdev)
   1436{
   1437	struct rtw_coex *coex = &rtwdev->coex;
   1438
   1439	clear_bit(RTW_FLAG_RUNNING, rtwdev->flags);
   1440	clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags);
   1441
   1442	mutex_unlock(&rtwdev->mutex);
   1443
   1444	cancel_work_sync(&rtwdev->c2h_work);
   1445	cancel_work_sync(&rtwdev->update_beacon_work);
   1446	cancel_delayed_work_sync(&rtwdev->watch_dog_work);
   1447	cancel_delayed_work_sync(&coex->bt_relink_work);
   1448	cancel_delayed_work_sync(&coex->bt_reenable_work);
   1449	cancel_delayed_work_sync(&coex->defreeze_work);
   1450	cancel_delayed_work_sync(&coex->wl_remain_work);
   1451	cancel_delayed_work_sync(&coex->bt_remain_work);
   1452	cancel_delayed_work_sync(&coex->wl_connecting_work);
   1453	cancel_delayed_work_sync(&coex->bt_multi_link_remain_work);
   1454	cancel_delayed_work_sync(&coex->wl_ccklock_work);
   1455
   1456	mutex_lock(&rtwdev->mutex);
   1457
   1458	rtw_power_off(rtwdev);
   1459}
   1460
   1461static void rtw_init_ht_cap(struct rtw_dev *rtwdev,
   1462			    struct ieee80211_sta_ht_cap *ht_cap)
   1463{
   1464	struct rtw_efuse *efuse = &rtwdev->efuse;
   1465	struct rtw_chip_info *chip = rtwdev->chip;
   1466
   1467	ht_cap->ht_supported = true;
   1468	ht_cap->cap = 0;
   1469	ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 |
   1470			IEEE80211_HT_CAP_MAX_AMSDU |
   1471			(1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
   1472
   1473	if (rtw_chip_has_rx_ldpc(rtwdev))
   1474		ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING;
   1475	if (rtw_chip_has_tx_stbc(rtwdev))
   1476		ht_cap->cap |= IEEE80211_HT_CAP_TX_STBC;
   1477
   1478	if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40))
   1479		ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
   1480				IEEE80211_HT_CAP_DSSSCCK40 |
   1481				IEEE80211_HT_CAP_SGI_40;
   1482	ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
   1483	ht_cap->ampdu_density = chip->ampdu_density;
   1484	ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
   1485	if (efuse->hw_cap.nss > 1) {
   1486		ht_cap->mcs.rx_mask[0] = 0xFF;
   1487		ht_cap->mcs.rx_mask[1] = 0xFF;
   1488		ht_cap->mcs.rx_mask[4] = 0x01;
   1489		ht_cap->mcs.rx_highest = cpu_to_le16(300);
   1490	} else {
   1491		ht_cap->mcs.rx_mask[0] = 0xFF;
   1492		ht_cap->mcs.rx_mask[1] = 0x00;
   1493		ht_cap->mcs.rx_mask[4] = 0x01;
   1494		ht_cap->mcs.rx_highest = cpu_to_le16(150);
   1495	}
   1496}
   1497
   1498static void rtw_init_vht_cap(struct rtw_dev *rtwdev,
   1499			     struct ieee80211_sta_vht_cap *vht_cap)
   1500{
   1501	struct rtw_efuse *efuse = &rtwdev->efuse;
   1502	u16 mcs_map;
   1503	__le16 highest;
   1504
   1505	if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE &&
   1506	    efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT)
   1507		return;
   1508
   1509	vht_cap->vht_supported = true;
   1510	vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
   1511		       IEEE80211_VHT_CAP_SHORT_GI_80 |
   1512		       IEEE80211_VHT_CAP_RXSTBC_1 |
   1513		       IEEE80211_VHT_CAP_HTC_VHT |
   1514		       IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK |
   1515		       0;
   1516	if (rtwdev->hal.rf_path_num > 1)
   1517		vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
   1518	vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
   1519			IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE;
   1520	vht_cap->cap |= (rtwdev->hal.bfee_sts_cap <<
   1521			IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT);
   1522
   1523	if (rtw_chip_has_rx_ldpc(rtwdev))
   1524		vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
   1525
   1526	mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
   1527		  IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
   1528		  IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
   1529		  IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
   1530		  IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
   1531		  IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
   1532		  IEEE80211_VHT_MCS_NOT_SUPPORTED << 14;
   1533	if (efuse->hw_cap.nss > 1) {
   1534		highest = cpu_to_le16(780);
   1535		mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << 2;
   1536	} else {
   1537		highest = cpu_to_le16(390);
   1538		mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << 2;
   1539	}
   1540
   1541	vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map);
   1542	vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map);
   1543	vht_cap->vht_mcs.rx_highest = highest;
   1544	vht_cap->vht_mcs.tx_highest = highest;
   1545}
   1546
   1547static void rtw_set_supported_band(struct ieee80211_hw *hw,
   1548				   struct rtw_chip_info *chip)
   1549{
   1550	struct rtw_dev *rtwdev = hw->priv;
   1551	struct ieee80211_supported_band *sband;
   1552
   1553	if (chip->band & RTW_BAND_2G) {
   1554		sband = kmemdup(&rtw_band_2ghz, sizeof(*sband), GFP_KERNEL);
   1555		if (!sband)
   1556			goto err_out;
   1557		if (chip->ht_supported)
   1558			rtw_init_ht_cap(rtwdev, &sband->ht_cap);
   1559		hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
   1560	}
   1561
   1562	if (chip->band & RTW_BAND_5G) {
   1563		sband = kmemdup(&rtw_band_5ghz, sizeof(*sband), GFP_KERNEL);
   1564		if (!sband)
   1565			goto err_out;
   1566		if (chip->ht_supported)
   1567			rtw_init_ht_cap(rtwdev, &sband->ht_cap);
   1568		if (chip->vht_supported)
   1569			rtw_init_vht_cap(rtwdev, &sband->vht_cap);
   1570		hw->wiphy->bands[NL80211_BAND_5GHZ] = sband;
   1571	}
   1572
   1573	return;
   1574
   1575err_out:
   1576	rtw_err(rtwdev, "failed to set supported band\n");
   1577}
   1578
   1579static void rtw_unset_supported_band(struct ieee80211_hw *hw,
   1580				     struct rtw_chip_info *chip)
   1581{
   1582	kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]);
   1583	kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]);
   1584}
   1585
   1586static void rtw_vif_smps_iter(void *data, u8 *mac,
   1587			      struct ieee80211_vif *vif)
   1588{
   1589	struct rtw_dev *rtwdev = (struct rtw_dev *)data;
   1590
   1591	if (vif->type != NL80211_IFTYPE_STATION || !vif->bss_conf.assoc)
   1592		return;
   1593
   1594	if (rtwdev->hal.txrx_1ss)
   1595		ieee80211_request_smps(vif, IEEE80211_SMPS_STATIC);
   1596	else
   1597		ieee80211_request_smps(vif, IEEE80211_SMPS_OFF);
   1598}
   1599
   1600void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool txrx_1ss)
   1601{
   1602	struct rtw_chip_info *chip = rtwdev->chip;
   1603	struct rtw_hal *hal = &rtwdev->hal;
   1604
   1605	if (!chip->ops->config_txrx_mode || rtwdev->hal.txrx_1ss == txrx_1ss)
   1606		return;
   1607
   1608	rtwdev->hal.txrx_1ss = txrx_1ss;
   1609	if (txrx_1ss)
   1610		chip->ops->config_txrx_mode(rtwdev, BB_PATH_A, BB_PATH_A, false);
   1611	else
   1612		chip->ops->config_txrx_mode(rtwdev, hal->antenna_tx,
   1613					    hal->antenna_rx, false);
   1614	rtw_iterate_vifs_atomic(rtwdev, rtw_vif_smps_iter, rtwdev);
   1615}
   1616
   1617static void __update_firmware_feature(struct rtw_dev *rtwdev,
   1618				      struct rtw_fw_state *fw)
   1619{
   1620	u32 feature;
   1621	const struct rtw_fw_hdr *fw_hdr =
   1622				(const struct rtw_fw_hdr *)fw->firmware->data;
   1623
   1624	feature = le32_to_cpu(fw_hdr->feature);
   1625	fw->feature = feature & FW_FEATURE_SIG ? feature : 0;
   1626}
   1627
   1628static void __update_firmware_info(struct rtw_dev *rtwdev,
   1629				   struct rtw_fw_state *fw)
   1630{
   1631	const struct rtw_fw_hdr *fw_hdr =
   1632				(const struct rtw_fw_hdr *)fw->firmware->data;
   1633
   1634	fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver);
   1635	fw->version = le16_to_cpu(fw_hdr->version);
   1636	fw->sub_version = fw_hdr->subversion;
   1637	fw->sub_index = fw_hdr->subindex;
   1638
   1639	__update_firmware_feature(rtwdev, fw);
   1640}
   1641
   1642static void __update_firmware_info_legacy(struct rtw_dev *rtwdev,
   1643					  struct rtw_fw_state *fw)
   1644{
   1645	struct rtw_fw_hdr_legacy *legacy =
   1646				(struct rtw_fw_hdr_legacy *)fw->firmware->data;
   1647
   1648	fw->h2c_version = 0;
   1649	fw->version = le16_to_cpu(legacy->version);
   1650	fw->sub_version = legacy->subversion1;
   1651	fw->sub_index = legacy->subversion2;
   1652}
   1653
   1654static void update_firmware_info(struct rtw_dev *rtwdev,
   1655				 struct rtw_fw_state *fw)
   1656{
   1657	if (rtw_chip_wcpu_11n(rtwdev))
   1658		__update_firmware_info_legacy(rtwdev, fw);
   1659	else
   1660		__update_firmware_info(rtwdev, fw);
   1661}
   1662
   1663static void rtw_load_firmware_cb(const struct firmware *firmware, void *context)
   1664{
   1665	struct rtw_fw_state *fw = context;
   1666	struct rtw_dev *rtwdev = fw->rtwdev;
   1667
   1668	if (!firmware || !firmware->data) {
   1669		rtw_err(rtwdev, "failed to request firmware\n");
   1670		complete_all(&fw->completion);
   1671		return;
   1672	}
   1673
   1674	fw->firmware = firmware;
   1675	update_firmware_info(rtwdev, fw);
   1676	complete_all(&fw->completion);
   1677
   1678	rtw_info(rtwdev, "Firmware version %u.%u.%u, H2C version %u\n",
   1679		 fw->version, fw->sub_version, fw->sub_index, fw->h2c_version);
   1680}
   1681
   1682static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type)
   1683{
   1684	const char *fw_name;
   1685	struct rtw_fw_state *fw;
   1686	int ret;
   1687
   1688	switch (type) {
   1689	case RTW_WOWLAN_FW:
   1690		fw = &rtwdev->wow_fw;
   1691		fw_name = rtwdev->chip->wow_fw_name;
   1692		break;
   1693
   1694	case RTW_NORMAL_FW:
   1695		fw = &rtwdev->fw;
   1696		fw_name = rtwdev->chip->fw_name;
   1697		break;
   1698
   1699	default:
   1700		rtw_warn(rtwdev, "unsupported firmware type\n");
   1701		return -ENOENT;
   1702	}
   1703
   1704	fw->rtwdev = rtwdev;
   1705	init_completion(&fw->completion);
   1706
   1707	ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev,
   1708				      GFP_KERNEL, fw, rtw_load_firmware_cb);
   1709	if (ret) {
   1710		rtw_err(rtwdev, "failed to async firmware request\n");
   1711		return ret;
   1712	}
   1713
   1714	return 0;
   1715}
   1716
   1717static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev)
   1718{
   1719	struct rtw_chip_info *chip = rtwdev->chip;
   1720	struct rtw_hal *hal = &rtwdev->hal;
   1721	struct rtw_efuse *efuse = &rtwdev->efuse;
   1722
   1723	switch (rtw_hci_type(rtwdev)) {
   1724	case RTW_HCI_TYPE_PCIE:
   1725		rtwdev->hci.rpwm_addr = 0x03d9;
   1726		rtwdev->hci.cpwm_addr = 0x03da;
   1727		break;
   1728	default:
   1729		rtw_err(rtwdev, "unsupported hci type\n");
   1730		return -EINVAL;
   1731	}
   1732
   1733	hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1);
   1734	hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version);
   1735	hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1;
   1736	if (hal->chip_version & BIT_RF_TYPE_ID) {
   1737		hal->rf_type = RF_2T2R;
   1738		hal->rf_path_num = 2;
   1739		hal->antenna_tx = BB_PATH_AB;
   1740		hal->antenna_rx = BB_PATH_AB;
   1741	} else {
   1742		hal->rf_type = RF_1T1R;
   1743		hal->rf_path_num = 1;
   1744		hal->antenna_tx = BB_PATH_A;
   1745		hal->antenna_rx = BB_PATH_A;
   1746	}
   1747	hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num :
   1748			  hal->rf_path_num;
   1749
   1750	efuse->physical_size = chip->phy_efuse_size;
   1751	efuse->logical_size = chip->log_efuse_size;
   1752	efuse->protect_size = chip->ptct_efuse_size;
   1753
   1754	/* default use ack */
   1755	rtwdev->hal.rcr |= BIT_VHT_DACK;
   1756
   1757	hal->bfee_sts_cap = 3;
   1758
   1759	return 0;
   1760}
   1761
   1762static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev)
   1763{
   1764	struct rtw_fw_state *fw = &rtwdev->fw;
   1765	int ret;
   1766
   1767	ret = rtw_hci_setup(rtwdev);
   1768	if (ret) {
   1769		rtw_err(rtwdev, "failed to setup hci\n");
   1770		goto err;
   1771	}
   1772
   1773	ret = rtw_mac_power_on(rtwdev);
   1774	if (ret) {
   1775		rtw_err(rtwdev, "failed to power on mac\n");
   1776		goto err;
   1777	}
   1778
   1779	rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP);
   1780
   1781	wait_for_completion(&fw->completion);
   1782	if (!fw->firmware) {
   1783		ret = -EINVAL;
   1784		rtw_err(rtwdev, "failed to load firmware\n");
   1785		goto err;
   1786	}
   1787
   1788	ret = rtw_download_firmware(rtwdev, fw);
   1789	if (ret) {
   1790		rtw_err(rtwdev, "failed to download firmware\n");
   1791		goto err_off;
   1792	}
   1793
   1794	return 0;
   1795
   1796err_off:
   1797	rtw_mac_power_off(rtwdev);
   1798
   1799err:
   1800	return ret;
   1801}
   1802
   1803static int rtw_dump_hw_feature(struct rtw_dev *rtwdev)
   1804{
   1805	struct rtw_efuse *efuse = &rtwdev->efuse;
   1806	u8 hw_feature[HW_FEATURE_LEN];
   1807	u8 id;
   1808	u8 bw;
   1809	int i;
   1810
   1811	id = rtw_read8(rtwdev, REG_C2HEVT);
   1812	if (id != C2H_HW_FEATURE_REPORT) {
   1813		rtw_err(rtwdev, "failed to read hw feature report\n");
   1814		return -EBUSY;
   1815	}
   1816
   1817	for (i = 0; i < HW_FEATURE_LEN; i++)
   1818		hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i);
   1819
   1820	rtw_write8(rtwdev, REG_C2HEVT, 0);
   1821
   1822	bw = GET_EFUSE_HW_CAP_BW(hw_feature);
   1823	efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw);
   1824	efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature);
   1825	efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature);
   1826	efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature);
   1827	efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature);
   1828
   1829	rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num);
   1830
   1831	if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE ||
   1832	    efuse->hw_cap.nss > rtwdev->hal.rf_path_num)
   1833		efuse->hw_cap.nss = rtwdev->hal.rf_path_num;
   1834
   1835	rtw_dbg(rtwdev, RTW_DBG_EFUSE,
   1836		"hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n",
   1837		efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl,
   1838		efuse->hw_cap.ant_num, efuse->hw_cap.nss);
   1839
   1840	return 0;
   1841}
   1842
   1843static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev)
   1844{
   1845	rtw_hci_stop(rtwdev);
   1846	rtw_mac_power_off(rtwdev);
   1847}
   1848
   1849static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev)
   1850{
   1851	struct rtw_efuse *efuse = &rtwdev->efuse;
   1852	int ret;
   1853
   1854	mutex_lock(&rtwdev->mutex);
   1855
   1856	/* power on mac to read efuse */
   1857	ret = rtw_chip_efuse_enable(rtwdev);
   1858	if (ret)
   1859		goto out_unlock;
   1860
   1861	ret = rtw_parse_efuse_map(rtwdev);
   1862	if (ret)
   1863		goto out_disable;
   1864
   1865	ret = rtw_dump_hw_feature(rtwdev);
   1866	if (ret)
   1867		goto out_disable;
   1868
   1869	ret = rtw_check_supported_rfe(rtwdev);
   1870	if (ret)
   1871		goto out_disable;
   1872
   1873	if (efuse->crystal_cap == 0xff)
   1874		efuse->crystal_cap = 0;
   1875	if (efuse->pa_type_2g == 0xff)
   1876		efuse->pa_type_2g = 0;
   1877	if (efuse->pa_type_5g == 0xff)
   1878		efuse->pa_type_5g = 0;
   1879	if (efuse->lna_type_2g == 0xff)
   1880		efuse->lna_type_2g = 0;
   1881	if (efuse->lna_type_5g == 0xff)
   1882		efuse->lna_type_5g = 0;
   1883	if (efuse->channel_plan == 0xff)
   1884		efuse->channel_plan = 0x7f;
   1885	if (efuse->rf_board_option == 0xff)
   1886		efuse->rf_board_option = 0;
   1887	if (efuse->bt_setting & BIT(0))
   1888		efuse->share_ant = true;
   1889	if (efuse->regd == 0xff)
   1890		efuse->regd = 0;
   1891	if (efuse->tx_bb_swing_setting_2g == 0xff)
   1892		efuse->tx_bb_swing_setting_2g = 0;
   1893	if (efuse->tx_bb_swing_setting_5g == 0xff)
   1894		efuse->tx_bb_swing_setting_5g = 0;
   1895
   1896	efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20;
   1897	efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0;
   1898	efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0;
   1899	efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0;
   1900	efuse->ext_lna_2g = efuse->lna_type_5g & BIT(3) ? 1 : 0;
   1901
   1902out_disable:
   1903	rtw_chip_efuse_disable(rtwdev);
   1904
   1905out_unlock:
   1906	mutex_unlock(&rtwdev->mutex);
   1907	return ret;
   1908}
   1909
   1910static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev)
   1911{
   1912	struct rtw_hal *hal = &rtwdev->hal;
   1913	const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev);
   1914
   1915	if (!rfe_def)
   1916		return -ENODEV;
   1917
   1918	rtw_phy_setup_phy_cond(rtwdev, 0);
   1919
   1920	rtw_phy_init_tx_power(rtwdev);
   1921	if (rfe_def->agc_btg_tbl)
   1922		rtw_load_table(rtwdev, rfe_def->agc_btg_tbl);
   1923	rtw_load_table(rtwdev, rfe_def->phy_pg_tbl);
   1924	rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl);
   1925	rtw_phy_tx_power_by_rate_config(hal);
   1926	rtw_phy_tx_power_limit_config(hal);
   1927
   1928	return 0;
   1929}
   1930
   1931int rtw_chip_info_setup(struct rtw_dev *rtwdev)
   1932{
   1933	int ret;
   1934
   1935	ret = rtw_chip_parameter_setup(rtwdev);
   1936	if (ret) {
   1937		rtw_err(rtwdev, "failed to setup chip parameters\n");
   1938		goto err_out;
   1939	}
   1940
   1941	ret = rtw_chip_efuse_info_setup(rtwdev);
   1942	if (ret) {
   1943		rtw_err(rtwdev, "failed to setup chip efuse info\n");
   1944		goto err_out;
   1945	}
   1946
   1947	ret = rtw_chip_board_info_setup(rtwdev);
   1948	if (ret) {
   1949		rtw_err(rtwdev, "failed to setup chip board info\n");
   1950		goto err_out;
   1951	}
   1952
   1953	return 0;
   1954
   1955err_out:
   1956	return ret;
   1957}
   1958EXPORT_SYMBOL(rtw_chip_info_setup);
   1959
   1960static void rtw_stats_init(struct rtw_dev *rtwdev)
   1961{
   1962	struct rtw_traffic_stats *stats = &rtwdev->stats;
   1963	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
   1964	int i;
   1965
   1966	ewma_tp_init(&stats->tx_ewma_tp);
   1967	ewma_tp_init(&stats->rx_ewma_tp);
   1968
   1969	for (i = 0; i < RTW_EVM_NUM; i++)
   1970		ewma_evm_init(&dm_info->ewma_evm[i]);
   1971	for (i = 0; i < RTW_SNR_NUM; i++)
   1972		ewma_snr_init(&dm_info->ewma_snr[i]);
   1973}
   1974
   1975int rtw_core_init(struct rtw_dev *rtwdev)
   1976{
   1977	struct rtw_chip_info *chip = rtwdev->chip;
   1978	struct rtw_coex *coex = &rtwdev->coex;
   1979	int ret;
   1980
   1981	INIT_LIST_HEAD(&rtwdev->rsvd_page_list);
   1982	INIT_LIST_HEAD(&rtwdev->txqs);
   1983
   1984	timer_setup(&rtwdev->tx_report.purge_timer,
   1985		    rtw_tx_report_purge_timer, 0);
   1986	rtwdev->tx_wq = alloc_workqueue("rtw_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0);
   1987
   1988	INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work);
   1989	INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work);
   1990	INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work);
   1991	INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work);
   1992	INIT_DELAYED_WORK(&coex->wl_remain_work, rtw_coex_wl_remain_work);
   1993	INIT_DELAYED_WORK(&coex->bt_remain_work, rtw_coex_bt_remain_work);
   1994	INIT_DELAYED_WORK(&coex->wl_connecting_work, rtw_coex_wl_connecting_work);
   1995	INIT_DELAYED_WORK(&coex->bt_multi_link_remain_work,
   1996			  rtw_coex_bt_multi_link_remain_work);
   1997	INIT_DELAYED_WORK(&coex->wl_ccklock_work, rtw_coex_wl_ccklock_work);
   1998	INIT_WORK(&rtwdev->tx_work, rtw_tx_work);
   1999	INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work);
   2000	INIT_WORK(&rtwdev->ips_work, rtw_ips_work);
   2001	INIT_WORK(&rtwdev->fw_recovery_work, rtw_fw_recovery_work);
   2002	INIT_WORK(&rtwdev->update_beacon_work, rtw_fw_update_beacon_work);
   2003	INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work);
   2004	skb_queue_head_init(&rtwdev->c2h_queue);
   2005	skb_queue_head_init(&rtwdev->coex.queue);
   2006	skb_queue_head_init(&rtwdev->tx_report.queue);
   2007
   2008	spin_lock_init(&rtwdev->rf_lock);
   2009	spin_lock_init(&rtwdev->h2c.lock);
   2010	spin_lock_init(&rtwdev->txq_lock);
   2011	spin_lock_init(&rtwdev->tx_report.q_lock);
   2012
   2013	mutex_init(&rtwdev->mutex);
   2014	mutex_init(&rtwdev->coex.mutex);
   2015	mutex_init(&rtwdev->hal.tx_power_mutex);
   2016
   2017	init_waitqueue_head(&rtwdev->coex.wait);
   2018	init_completion(&rtwdev->lps_leave_check);
   2019	init_completion(&rtwdev->fw_scan_density);
   2020
   2021	rtwdev->sec.total_cam_num = 32;
   2022	rtwdev->hal.current_channel = 1;
   2023	rtwdev->dm_info.fix_rate = U8_MAX;
   2024	set_bit(RTW_BC_MC_MACID, rtwdev->mac_id_map);
   2025
   2026	rtw_stats_init(rtwdev);
   2027
   2028	/* default rx filter setting */
   2029	rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV |
   2030			  BIT_PKTCTL_DLEN | BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS |
   2031			  BIT_AB | BIT_AM | BIT_APM;
   2032
   2033	ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW);
   2034	if (ret) {
   2035		rtw_warn(rtwdev, "no firmware loaded\n");
   2036		return ret;
   2037	}
   2038
   2039	if (chip->wow_fw_name) {
   2040		ret = rtw_load_firmware(rtwdev, RTW_WOWLAN_FW);
   2041		if (ret) {
   2042			rtw_warn(rtwdev, "no wow firmware loaded\n");
   2043			wait_for_completion(&rtwdev->fw.completion);
   2044			if (rtwdev->fw.firmware)
   2045				release_firmware(rtwdev->fw.firmware);
   2046			return ret;
   2047		}
   2048	}
   2049
   2050	return 0;
   2051}
   2052EXPORT_SYMBOL(rtw_core_init);
   2053
   2054void rtw_core_deinit(struct rtw_dev *rtwdev)
   2055{
   2056	struct rtw_fw_state *fw = &rtwdev->fw;
   2057	struct rtw_fw_state *wow_fw = &rtwdev->wow_fw;
   2058	struct rtw_rsvd_page *rsvd_pkt, *tmp;
   2059	unsigned long flags;
   2060
   2061	rtw_wait_firmware_completion(rtwdev);
   2062
   2063	if (fw->firmware)
   2064		release_firmware(fw->firmware);
   2065
   2066	if (wow_fw->firmware)
   2067		release_firmware(wow_fw->firmware);
   2068
   2069	destroy_workqueue(rtwdev->tx_wq);
   2070	spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags);
   2071	skb_queue_purge(&rtwdev->tx_report.queue);
   2072	skb_queue_purge(&rtwdev->coex.queue);
   2073	spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags);
   2074
   2075	list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list,
   2076				 build_list) {
   2077		list_del(&rsvd_pkt->build_list);
   2078		kfree(rsvd_pkt);
   2079	}
   2080
   2081	mutex_destroy(&rtwdev->mutex);
   2082	mutex_destroy(&rtwdev->coex.mutex);
   2083	mutex_destroy(&rtwdev->hal.tx_power_mutex);
   2084}
   2085EXPORT_SYMBOL(rtw_core_deinit);
   2086
   2087int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw)
   2088{
   2089	struct rtw_hal *hal = &rtwdev->hal;
   2090	int max_tx_headroom = 0;
   2091	int ret;
   2092
   2093	/* TODO: USB & SDIO may need extra room? */
   2094	max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz;
   2095
   2096	hw->extra_tx_headroom = max_tx_headroom;
   2097	hw->queues = IEEE80211_NUM_ACS;
   2098	hw->txq_data_size = sizeof(struct rtw_txq);
   2099	hw->sta_data_size = sizeof(struct rtw_sta_info);
   2100	hw->vif_data_size = sizeof(struct rtw_vif);
   2101
   2102	ieee80211_hw_set(hw, SIGNAL_DBM);
   2103	ieee80211_hw_set(hw, RX_INCLUDES_FCS);
   2104	ieee80211_hw_set(hw, AMPDU_AGGREGATION);
   2105	ieee80211_hw_set(hw, MFP_CAPABLE);
   2106	ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
   2107	ieee80211_hw_set(hw, SUPPORTS_PS);
   2108	ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
   2109	ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
   2110	ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU);
   2111	ieee80211_hw_set(hw, HAS_RATE_CONTROL);
   2112	ieee80211_hw_set(hw, TX_AMSDU);
   2113	ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS);
   2114
   2115	hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
   2116				     BIT(NL80211_IFTYPE_AP) |
   2117				     BIT(NL80211_IFTYPE_ADHOC) |
   2118				     BIT(NL80211_IFTYPE_MESH_POINT);
   2119	hw->wiphy->available_antennas_tx = hal->antenna_tx;
   2120	hw->wiphy->available_antennas_rx = hal->antenna_rx;
   2121
   2122	hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS |
   2123			    WIPHY_FLAG_TDLS_EXTERNAL_SETUP;
   2124
   2125	hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR;
   2126	hw->wiphy->max_scan_ssids = RTW_SCAN_MAX_SSIDS;
   2127	hw->wiphy->max_scan_ie_len = RTW_SCAN_MAX_IE_LEN;
   2128
   2129	wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
   2130	wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN);
   2131	wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL);
   2132
   2133#ifdef CONFIG_PM
   2134	hw->wiphy->wowlan = rtwdev->chip->wowlan_stub;
   2135	hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids;
   2136#endif
   2137	rtw_set_supported_band(hw, rtwdev->chip);
   2138	SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr);
   2139
   2140	hw->wiphy->sar_capa = &rtw_sar_capa;
   2141
   2142	ret = rtw_regd_init(rtwdev);
   2143	if (ret) {
   2144		rtw_err(rtwdev, "failed to init regd\n");
   2145		return ret;
   2146	}
   2147
   2148	ret = ieee80211_register_hw(hw);
   2149	if (ret) {
   2150		rtw_err(rtwdev, "failed to register hw\n");
   2151		return ret;
   2152	}
   2153
   2154	ret = rtw_regd_hint(rtwdev);
   2155	if (ret) {
   2156		rtw_err(rtwdev, "failed to hint regd\n");
   2157		return ret;
   2158	}
   2159
   2160	rtw_debugfs_init(rtwdev);
   2161
   2162	rtwdev->bf_info.bfer_mu_cnt = 0;
   2163	rtwdev->bf_info.bfer_su_cnt = 0;
   2164
   2165	return 0;
   2166}
   2167EXPORT_SYMBOL(rtw_register_hw);
   2168
   2169void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw)
   2170{
   2171	struct rtw_chip_info *chip = rtwdev->chip;
   2172
   2173	ieee80211_unregister_hw(hw);
   2174	rtw_unset_supported_band(hw, chip);
   2175}
   2176EXPORT_SYMBOL(rtw_unregister_hw);
   2177
   2178MODULE_AUTHOR("Realtek Corporation");
   2179MODULE_DESCRIPTION("Realtek 802.11ac wireless core module");
   2180MODULE_LICENSE("Dual BSD/GPL");