cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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util.c (2372B)

      1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
      2/* Copyright(c) 2018-2019  Realtek Corporation
      3 */
      4
      5#include "main.h"
      6#include "util.h"
      7#include "reg.h"
      8
      9bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target)
     10{
     11	u32 cnt;
     12
     13	for (cnt = 0; cnt < 1000; cnt++) {
     14		if (rtw_read32_mask(rtwdev, addr, mask) == target)
     15			return true;
     16
     17		udelay(10);
     18	}
     19
     20	return false;
     21}
     22EXPORT_SYMBOL(check_hw_ready);
     23
     24bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val)
     25{
     26	struct rtw_chip_info *chip = rtwdev->chip;
     27	const struct rtw_ltecoex_addr *ltecoex = chip->ltecoex_addr;
     28
     29	if (!check_hw_ready(rtwdev, ltecoex->ctrl, LTECOEX_READY, 1))
     30		return false;
     31
     32	rtw_write32(rtwdev, ltecoex->ctrl, 0x800F0000 | offset);
     33	*val = rtw_read32(rtwdev, ltecoex->rdata);
     34
     35	return true;
     36}
     37
     38bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value)
     39{
     40	struct rtw_chip_info *chip = rtwdev->chip;
     41	const struct rtw_ltecoex_addr *ltecoex = chip->ltecoex_addr;
     42
     43	if (!check_hw_ready(rtwdev, ltecoex->ctrl, LTECOEX_READY, 1))
     44		return false;
     45
     46	rtw_write32(rtwdev, ltecoex->wdata, value);
     47	rtw_write32(rtwdev, ltecoex->ctrl, 0xC00F0000 | offset);
     48
     49	return true;
     50}
     51
     52void rtw_restore_reg(struct rtw_dev *rtwdev,
     53		     struct rtw_backup_info *bckp, u32 num)
     54{
     55	u8 len;
     56	u32 reg;
     57	u32 val;
     58	int i;
     59
     60	for (i = 0; i < num; i++, bckp++) {
     61		len = bckp->len;
     62		reg = bckp->reg;
     63		val = bckp->val;
     64
     65		switch (len) {
     66		case 1:
     67			rtw_write8(rtwdev, reg, (u8)val);
     68			break;
     69		case 2:
     70			rtw_write16(rtwdev, reg, (u16)val);
     71			break;
     72		case 4:
     73			rtw_write32(rtwdev, reg, (u32)val);
     74			break;
     75		default:
     76			break;
     77		}
     78	}
     79}
     80EXPORT_SYMBOL(rtw_restore_reg);
     81
     82void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss)
     83{
     84	if (rate <= DESC_RATE54M)
     85		return;
     86
     87	if (rate >= DESC_RATEVHT1SS_MCS0 &&
     88	    rate <= DESC_RATEVHT1SS_MCS9) {
     89		*nss = 1;
     90		*mcs = rate - DESC_RATEVHT1SS_MCS0;
     91	} else if (rate >= DESC_RATEVHT2SS_MCS0 &&
     92		   rate <= DESC_RATEVHT2SS_MCS9) {
     93		*nss = 2;
     94		*mcs = rate - DESC_RATEVHT2SS_MCS0;
     95	} else if (rate >= DESC_RATEVHT3SS_MCS0 &&
     96		   rate <= DESC_RATEVHT3SS_MCS9) {
     97		*nss = 3;
     98		*mcs = rate - DESC_RATEVHT3SS_MCS0;
     99	} else if (rate >= DESC_RATEVHT4SS_MCS0 &&
    100		   rate <= DESC_RATEVHT4SS_MCS9) {
    101		*nss = 4;
    102		*mcs = rate - DESC_RATEVHT4SS_MCS0;
    103	} else if (rate >= DESC_RATEMCS0 &&
    104		   rate <= DESC_RATEMCS15) {
    105		*mcs = rate - DESC_RATEMCS0;
    106	}
    107}