cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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reg.h (153452B)


      1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
      2/* Copyright(c) 2019-2020  Realtek Corporation
      3 */
      4
      5#ifndef __RTW89_REG_H__
      6#define __RTW89_REG_H__
      7
      8#define R_AX_SYS_WL_EFUSE_CTRL 0x000A
      9#define B_AX_AUTOLOAD_SUS BIT(5)
     10
     11#define R_AX_SYS_ISO_CTRL 0x0000
     12#define B_AX_PWC_EV2EF_MASK GENMASK(15, 14)
     13#define B_AX_PWC_EV2EF_B15 BIT(15)
     14#define B_AX_PWC_EV2EF_B14 BIT(14)
     15#define B_AX_ISO_EB2CORE BIT(8)
     16
     17#define R_AX_SYS_FUNC_EN 0x0002
     18#define B_AX_FEN_BB_GLB_RSTN BIT(1)
     19#define B_AX_FEN_BBRSTB BIT(0)
     20
     21#define R_AX_SYS_PW_CTRL 0x0004
     22#define B_AX_XTAL_OFF_A_DIE BIT(22)
     23#define B_AX_DIS_WLBT_PDNSUSEN_SOPC BIT(18)
     24#define B_AX_RDY_SYSPWR BIT(17)
     25#define B_AX_EN_WLON BIT(16)
     26#define B_AX_APDM_HPDN BIT(15)
     27#define B_AX_PSUS_OFF_CAPC_EN BIT(14)
     28#define B_AX_AFSM_PCIE_SUS_EN BIT(12)
     29#define B_AX_AFSM_WLSUS_EN BIT(11)
     30#define B_AX_APFM_SWLPS BIT(10)
     31#define B_AX_APFM_OFFMAC BIT(9)
     32#define B_AX_APFN_ONMAC BIT(8)
     33
     34#define R_AX_SYS_CLK_CTRL 0x0008
     35#define B_AX_CPU_CLK_EN BIT(14)
     36
     37#define R_AX_SYS_ADIE_PAD_PWR_CTRL 0x0018
     38#define B_AX_SYM_PADPDN_WL_PTA_1P3 BIT(6)
     39#define B_AX_SYM_PADPDN_WL_RFC_1P3 BIT(5)
     40
     41#define R_AX_RSV_CTRL 0x001C
     42#define B_AX_R_DIS_PRST BIT(6)
     43#define B_AX_WLOCK_1C_BIT6 BIT(5)
     44
     45#define R_AX_EFUSE_CTRL_1 0x0038
     46#define B_AX_EF_PGPD_MASK GENMASK(30, 28)
     47#define B_AX_EF_RDT BIT(27)
     48#define B_AX_EF_VDDQST_MASK GENMASK(26, 24)
     49#define B_AX_EF_PGTS_MASK GENMASK(23, 20)
     50#define B_AX_EF_PD_DIS BIT(11)
     51#define B_AX_EF_POR BIT(10)
     52#define B_AX_EF_CELL_SEL_MASK GENMASK(9, 8)
     53
     54#define R_AX_SPSLDO_ON_CTRL0 0x0200
     55#define B_AX_OCP_L1_MASK GENMASK(15, 13)
     56
     57#define R_AX_EFUSE_CTRL 0x0030
     58#define B_AX_EF_MODE_SEL_MASK GENMASK(31, 30)
     59#define B_AX_EF_RDY BIT(29)
     60#define B_AX_EF_COMP_RESULT BIT(28)
     61#define B_AX_EF_ADDR_MASK GENMASK(26, 16)
     62#define B_AX_EF_DATA_MASK GENMASK(15, 0)
     63
     64#define R_AX_EFUSE_CTRL_1_V1 0x0038
     65#define B_AX_EF_ENT BIT(31)
     66#define B_AX_EF_BURST BIT(19)
     67#define B_AX_EF_TEST_SEL_MASK GENMASK(18, 16)
     68#define B_AX_EF_TROW_EN BIT(15)
     69#define B_AX_EF_ERR_FLAG BIT(14)
     70#define B_AX_EF_DSB_EN BIT(11)
     71#define B_AX_PCIE_CALIB_EN_V1 BIT(12)
     72#define B_AX_WDT_WAKE_PCIE_EN BIT(10)
     73#define B_AX_WDT_WAKE_USB_EN BIT(9)
     74
     75#define R_AX_GPIO_MUXCFG 0x0040
     76#define B_AX_BOOT_MODE BIT(19)
     77#define B_AX_WL_EECS_EXT_32K_SEL BIT(18)
     78#define B_AX_WL_SEC_BONDING_OPT_STS BIT(17)
     79#define B_AX_SECSIC_SEL BIT(16)
     80#define B_AX_ENHTP BIT(14)
     81#define B_AX_BT_AOD_GPIO3 BIT(13)
     82#define B_AX_ENSIC BIT(12)
     83#define B_AX_SIC_SWRST BIT(11)
     84#define B_AX_PO_WIFI_PTA_PINS BIT(10)
     85#define B_AX_PO_BT_PTA_PINS BIT(9)
     86#define B_AX_ENUARTTX BIT(8)
     87#define B_AX_BTMODE_MASK GENMASK(7, 6)
     88#define MAC_AX_BT_MODE_0_3 0
     89#define MAC_AX_BT_MODE_2 2
     90#define MAC_AX_RTK_MODE 0
     91#define MAC_AX_CSR_MODE 1
     92#define B_AX_ENBT BIT(5)
     93#define B_AX_EROM_EN BIT(4)
     94#define B_AX_ENUARTRX BIT(2)
     95#define B_AX_GPIOSEL_MASK GENMASK(1, 0)
     96
     97#define R_AX_DBG_CTRL 0x0058
     98#define B_AX_DBG_SEL1_4BIT GENMASK(31, 30)
     99#define B_AX_DBG_SEL1_16BIT BIT(27)
    100#define B_AX_DBG_SEL1 GENMASK(23, 16)
    101#define B_AX_DBG_SEL0_4BIT GENMASK(15, 14)
    102#define B_AX_DBG_SEL0_16BIT BIT(11)
    103#define B_AX_DBG_SEL0 GENMASK(7, 0)
    104
    105#define R_AX_SYS_SDIO_CTRL 0x0070
    106#define B_AX_PCIE_DIS_L2_CTRL_LDO_HCI BIT(15)
    107#define B_AX_PCIE_DIS_WLSUS_AFT_PDN BIT(14)
    108#define B_AX_PCIE_FORCE_PWR_NGAT BIT(13)
    109#define B_AX_PCIE_CALIB_EN_V1 BIT(12)
    110#define B_AX_PCIE_AUXCLK_GATE BIT(11)
    111#define B_AX_LTE_MUX_CTRL_PATH BIT(26)
    112
    113#define R_AX_HCI_OPT_CTRL 0x0074
    114#define BIT_WAKE_CTRL BIT(5)
    115
    116#define R_AX_HCI_BG_CTRL 0x0078
    117#define B_AX_IBX_EN_VALUE BIT(15)
    118#define B_AX_IB_EN_VALUE BIT(14)
    119#define B_AX_FORCED_IB_EN BIT(4)
    120#define B_AX_EN_REGBG BIT(3)
    121#define B_AX_R_AX_BG_LPF BIT(2)
    122#define B_AX_R_AX_BG GENMASK(1, 0)
    123
    124#define R_AX_PLATFORM_ENABLE 0x0088
    125#define B_AX_AXIDMA_EN BIT(3)
    126#define B_AX_WCPU_EN BIT(1)
    127#define B_AX_PLATFORM_EN BIT(0)
    128
    129#define R_AX_WLLPS_CTRL 0x0090
    130#define B_AX_DIS_WLBT_LPSEN_LOPC BIT(1)
    131
    132#define R_AX_SCOREBOARD  0x00AC
    133#define B_AX_TOGGLE BIT(31)
    134#define B_MAC_AX_SB_FW_MASK GENMASK(30, 24)
    135#define B_MAC_AX_SB_DRV_MASK GENMASK(23, 0)
    136#define B_MAC_AX_BTGS1_NOTIFY BIT(0)
    137#define MAC_AX_NOTIFY_TP_MAJOR 0x81
    138#define MAC_AX_NOTIFY_PWR_MAJOR 0x80
    139
    140#define R_AX_DBG_PORT_SEL 0x00C0
    141#define B_AX_DEBUG_ST_MASK GENMASK(31, 0)
    142
    143#define R_AX_PMC_DBG_CTRL2 0x00CC
    144#define B_AX_SYSON_DIS_PMCR_AX_WRMSK BIT(2)
    145
    146#define R_AX_SYS_CFG1 0x00F0
    147#define B_AX_CHIP_VER_MASK GENMASK(15, 12)
    148
    149#define R_AX_SYS_STATUS1 0x00F4
    150#define B_AX_SEL_0XC0_MASK GENMASK(17, 16)
    151#define B_AX_PAD_HCI_SEL_V2_MASK GENMASK(5, 3)
    152#define MAC_AX_HCI_SEL_SDIO_UART 0
    153#define MAC_AX_HCI_SEL_MULTI_USB 1
    154#define MAC_AX_HCI_SEL_PCIE_UART 2
    155#define MAC_AX_HCI_SEL_PCIE_USB 3
    156#define MAC_AX_HCI_SEL_MULTI_SDIO 4
    157
    158#define R_AX_HALT_H2C_CTRL 0x0160
    159#define R_AX_HALT_H2C 0x0168
    160#define B_AX_HALT_H2C_TRIGGER BIT(0)
    161#define R_AX_HALT_C2H_CTRL 0x0164
    162#define R_AX_HALT_C2H 0x016C
    163
    164#define R_AX_WCPU_FW_CTRL 0x01E0
    165#define B_AX_WCPU_FWDL_STS_MASK GENMASK(7, 5)
    166#define B_AX_FWDL_PATH_RDY BIT(2)
    167#define B_AX_H2C_PATH_RDY BIT(1)
    168#define B_AX_WCPU_FWDL_EN BIT(0)
    169
    170#define R_AX_RPWM 0x01E4
    171#define R_AX_PCIE_HRPWM 0x10C0
    172#define PS_RPWM_TOGGLE BIT(15)
    173#define PS_RPWM_ACK BIT(14)
    174#define PS_RPWM_SEQ_NUM GENMASK(13, 12)
    175#define PS_RPWM_NOTIFY_WAKE BIT(8)
    176#define PS_RPWM_STATE 0x7
    177#define RPWM_SEQ_NUM_MAX 3
    178#define PS_CPWM_SEQ_NUM GENMASK(13, 12)
    179#define PS_CPWM_RSP_SEQ_NUM GENMASK(9, 8)
    180#define PS_CPWM_STATE GENMASK(2, 0)
    181#define CPWM_SEQ_NUM_MAX 3
    182
    183#define R_AX_BOOT_REASON 0x01E6
    184#define B_AX_BOOT_REASON_MASK GENMASK(2, 0)
    185
    186#define R_AX_LDM 0x01E8
    187#define B_AX_EN_32K BIT(31)
    188
    189#define R_AX_UDM0 0x01F0
    190#define R_AX_UDM1 0x01F4
    191#define R_AX_UDM2 0x01F8
    192#define R_AX_UDM3 0x01FC
    193
    194#define R_AX_LDO_AON_CTRL0 0x0218
    195#define B_AX_PD_REGU_L BIT(16)
    196
    197#define R_AX_WLAN_XTAL_SI_CTRL 0x0270
    198#define B_AX_WL_XTAL_SI_CMD_POLL BIT(31)
    199#define B_AX_BT_XTAL_SI_ERR_FLAG BIT(30)
    200#define B_AX_WL_XTAL_GNT BIT(29)
    201#define B_AX_BT_XTAL_GNT BIT(28)
    202#define B_AX_WL_XTAL_SI_MODE_MASK GENMASK(25, 24)
    203#define XTAL_SI_NORMAL_WRITE 0x00
    204#define XTAL_SI_NORMAL_READ 0x01
    205#define B_AX_WL_XTAL_SI_BITMASK_MASK GENMASK(23, 16)
    206#define B_AX_WL_XTAL_SI_DATA_MASK GENMASK(15, 8)
    207#define B_AX_WL_XTAL_SI_ADDR_MASK GENMASK(7, 0)
    208
    209#define R_AX_XTAL_ON_CTRL0 0x0280
    210#define B_AX_XTAL_SC_LPS BIT(31)
    211#define B_AX_XTAL_SC_XO_MASK GENMASK(23, 17)
    212#define B_AX_XTAL_SC_XI_MASK GENMASK(16, 10)
    213#define B_AX_XTAL_SC_MASK GENMASK(6, 0)
    214
    215#define R_AX_GPIO0_7_FUNC_SEL 0x02D0
    216
    217#define R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN 0x02E4
    218#define B_AX_LED1_PULL_LOW_EN BIT(18)
    219#define B_AX_EESK_PULL_LOW_EN BIT(17)
    220#define B_AX_EECS_PULL_LOW_EN BIT(16)
    221
    222#define R_AX_WLRF_CTRL 0x02F0
    223#define B_AX_AFC_AFEDIG BIT(17)
    224#define B_AX_WLRF1_CTRL_7 BIT(15)
    225#define B_AX_WLRF1_CTRL_1 BIT(9)
    226#define B_AX_WLRF_CTRL_7 BIT(7)
    227#define B_AX_WLRF_CTRL_1 BIT(1)
    228
    229#define R_AX_IC_PWR_STATE 0x03F0
    230#define B_AX_WHOLE_SYS_PWR_STE_MASK GENMASK(25, 16)
    231#define B_AX_WLMAC_PWR_STE_MASK GENMASK(9, 8)
    232#define B_AX_UART_HCISYS_PWR_STE_MASK GENMASK(7, 6)
    233#define B_AX_SDIO_HCISYS_PWR_STE_MASK GENMASK(5, 4)
    234#define B_AX_USB_HCISYS_PWR_STE_MASK GENMASK(3, 2)
    235#define B_AX_PCIE_HCISYS_PWR_STE_MASK GENMASK(1, 0)
    236
    237#define R_AX_AFE_OFF_CTRL1 0x0444
    238#define B_AX_S1_LDO_VSEL_F_MASK GENMASK(25, 24)
    239#define B_AX_S1_LDO2PWRCUT_F BIT(23)
    240#define B_AX_S0_LDO_VSEL_F_MASK GENMASK(22, 21)
    241
    242#define R_AX_FILTER_MODEL_ADDR 0x0C04
    243
    244#define R_AX_HAXI_INIT_CFG1 0x1000
    245#define B_AX_WD_ITVL_IDLE_V1_MASK GENMASK(31, 28)
    246#define B_AX_WD_ITVL_ACT_V1_MASK GENMASK(27, 24)
    247#define B_AX_DMA_MODE_MASK GENMASK(19, 18)
    248#define DMA_MOD_PCIE_1B 0x0
    249#define DMA_MOD_PCIE_4B 0x1
    250#define DMA_MOD_USB 0x2
    251#define DMA_MOD_SDIO 0x3
    252#define B_AX_STOP_AXI_MST BIT(17)
    253#define B_AX_HAXI_RST_KEEP_REG BIT(16)
    254#define B_AX_RXHCI_EN_V1 BIT(15)
    255#define B_AX_RXBD_MODE_V1 BIT(14)
    256#define B_AX_HAXI_MAX_RXDMA_MASK GENMASK(9, 8)
    257#define B_AX_TXHCI_EN_V1 BIT(7)
    258#define B_AX_FLUSH_AXI_MST BIT(4)
    259#define B_AX_RST_BDRAM BIT(3)
    260#define B_AX_HAXI_MAX_TXDMA_MASK GENMASK(1, 0)
    261
    262#define R_AX_HAXI_DMA_STOP1 0x1010
    263#define B_AX_STOP_WPDMA BIT(19)
    264#define B_AX_STOP_CH12 BIT(18)
    265#define B_AX_STOP_CH9 BIT(17)
    266#define B_AX_STOP_CH8 BIT(16)
    267#define B_AX_STOP_ACH7 BIT(15)
    268#define B_AX_STOP_ACH6 BIT(14)
    269#define B_AX_STOP_ACH5 BIT(13)
    270#define B_AX_STOP_ACH4 BIT(12)
    271#define B_AX_STOP_ACH3 BIT(11)
    272#define B_AX_STOP_ACH2 BIT(10)
    273#define B_AX_STOP_ACH1 BIT(9)
    274#define B_AX_STOP_ACH0 BIT(8)
    275
    276#define R_AX_HAXI_DMA_BUSY1 0x101C
    277#define B_AX_HAXIIO_BUSY BIT(20)
    278#define B_AX_WPDMA_BUSY BIT(19)
    279#define B_AX_CH12_BUSY BIT(18)
    280#define B_AX_CH9_BUSY BIT(17)
    281#define B_AX_CH8_BUSY BIT(16)
    282#define B_AX_ACH7_BUSY BIT(15)
    283#define B_AX_ACH6_BUSY BIT(14)
    284#define B_AX_ACH5_BUSY BIT(13)
    285#define B_AX_ACH4_BUSY BIT(12)
    286#define B_AX_ACH3_BUSY BIT(11)
    287#define B_AX_ACH2_BUSY BIT(10)
    288#define B_AX_ACH1_BUSY BIT(9)
    289#define B_AX_ACH0_BUSY BIT(8)
    290
    291#define R_AX_PCIE_DBG_CTRL 0x11C0
    292#define B_AX_DBG_DUMMY_MASK GENMASK(23, 16)
    293#define B_AX_DBG_SEL_MASK GENMASK(15, 13)
    294#define B_AX_PCIE_DBG_SEL BIT(12)
    295#define B_AX_MRD_TIMEOUT_EN BIT(10)
    296#define B_AX_ASFF_FULL_NO_STK BIT(1)
    297#define B_AX_EN_STUCK_DBG BIT(0)
    298
    299#define R_AX_HAXI_DMA_STOP2 0x11C0
    300#define B_AX_STOP_CH11 BIT(1)
    301#define B_AX_STOP_CH10 BIT(0)
    302
    303#define R_AX_HAXI_DMA_BUSY2 0x11C8
    304#define B_AX_CH11_BUSY BIT(1)
    305#define B_AX_CH10_BUSY BIT(0)
    306
    307#define R_AX_HAXI_DMA_BUSY3 0x1208
    308#define B_AX_RPQ_BUSY BIT(1)
    309#define B_AX_RXQ_BUSY BIT(0)
    310
    311#define R_AX_LTR_DEC_CTRL 0x1600
    312#define B_AX_LTR_IDX_DRV_VLD BIT(16)
    313#define B_AX_LTR_CURR_IDX_DRV_MASK GENMASK(15, 14)
    314#define B_AX_LTR_IDX_FW_VLD BIT(13)
    315#define B_AX_LTR_CURR_IDX_FW_MASK GENMASK(12, 11)
    316#define B_AX_LTR_IDX_HW_VLD BIT(10)
    317#define B_AX_LTR_CURR_IDX_HW_MASK GENMASK(9, 8)
    318#define B_AX_LTR_REQ_DRV BIT(7)
    319#define B_AX_LTR_IDX_DRV_MASK GENMASK(6, 5)
    320#define PCIE_LTR_IDX_IDLE 3
    321#define B_AX_LTR_DRV_DEC_EN BIT(4)
    322#define B_AX_LTR_FW_DEC_EN BIT(3)
    323#define B_AX_LTR_HW_DEC_EN BIT(2)
    324#define B_AX_LTR_SPACE_IDX_V1_MASK GENMASK(1, 0)
    325#define LTR_EN_BITS (B_AX_LTR_HW_DEC_EN | B_AX_LTR_FW_DEC_EN | B_AX_LTR_DRV_DEC_EN)
    326
    327#define R_AX_LTR_LATENCY_IDX0 0x1604
    328#define R_AX_LTR_LATENCY_IDX1 0x1608
    329#define R_AX_LTR_LATENCY_IDX2 0x160C
    330#define R_AX_LTR_LATENCY_IDX3 0x1610
    331
    332#define R_AX_HCI_FC_CTRL_V1 0x1700
    333#define R_AX_CH_PAGE_CTRL_V1 0x1704
    334
    335#define R_AX_ACH0_PAGE_CTRL_V1 0x1710
    336#define R_AX_ACH1_PAGE_CTRL_V1 0x1714
    337#define R_AX_ACH2_PAGE_CTRL_V1 0x1718
    338#define R_AX_ACH3_PAGE_CTRL_V1 0x171C
    339#define R_AX_ACH4_PAGE_CTRL_V1 0x1720
    340#define R_AX_ACH5_PAGE_CTRL_V1 0x1724
    341#define R_AX_ACH6_PAGE_CTRL_V1 0x1728
    342#define R_AX_ACH7_PAGE_CTRL_V1 0x172C
    343#define R_AX_CH8_PAGE_CTRL_V1 0x1730
    344#define R_AX_CH9_PAGE_CTRL_V1 0x1734
    345#define R_AX_CH10_PAGE_CTRL_V1 0x1738
    346#define R_AX_CH11_PAGE_CTRL_V1 0x173C
    347
    348#define R_AX_ACH0_PAGE_INFO_V1 0x1750
    349#define R_AX_ACH1_PAGE_INFO_V1 0x1754
    350#define R_AX_ACH2_PAGE_INFO_V1 0x1758
    351#define R_AX_ACH3_PAGE_INFO_V1 0x175C
    352#define R_AX_ACH4_PAGE_INFO_V1 0x1760
    353#define R_AX_ACH5_PAGE_INFO_V1 0x1764
    354#define R_AX_ACH6_PAGE_INFO_V1 0x1768
    355#define R_AX_ACH7_PAGE_INFO_V1 0x176C
    356#define R_AX_CH8_PAGE_INFO_V1 0x1770
    357#define R_AX_CH9_PAGE_INFO_V1 0x1774
    358#define R_AX_CH10_PAGE_INFO_V1 0x1778
    359#define R_AX_CH11_PAGE_INFO_V1 0x177C
    360#define R_AX_CH12_PAGE_INFO_V1 0x1780
    361
    362#define R_AX_PUB_PAGE_INFO3_V1 0x178C
    363#define R_AX_PUB_PAGE_CTRL1_V1 0x1790
    364#define R_AX_PUB_PAGE_CTRL2_V1 0x1794
    365#define R_AX_PUB_PAGE_INFO1_V1 0x1798
    366#define R_AX_PUB_PAGE_INFO2_V1 0x179C
    367#define R_AX_WP_PAGE_CTRL1_V1 0x17A0
    368#define R_AX_WP_PAGE_CTRL2_V1 0x17A4
    369#define R_AX_WP_PAGE_INFO1_V1 0x17A8
    370
    371#define R_AX_H2CREG_DATA0_V1 0x7140
    372#define R_AX_H2CREG_DATA1_V1 0x7144
    373#define R_AX_H2CREG_DATA2_V1 0x7148
    374#define R_AX_H2CREG_DATA3_V1 0x714C
    375#define R_AX_C2HREG_DATA0_V1 0x7150
    376#define R_AX_C2HREG_DATA1_V1 0x7154
    377#define R_AX_C2HREG_DATA2_V1 0x7158
    378#define R_AX_C2HREG_DATA3_V1 0x715C
    379#define R_AX_H2CREG_CTRL_V1 0x7160
    380#define R_AX_C2HREG_CTRL_V1 0x7164
    381
    382#define R_AX_HCI_FUNC_EN_V1 0x7880
    383
    384#define R_AX_PHYREG_SET 0x8040
    385#define PHYREG_SET_ALL_CYCLE 0x8
    386
    387#define R_AX_HD0IMR 0x8110
    388#define B_AX_WDT_PTFM_INT_EN BIT(5)
    389#define B_AX_CPWM_INT_EN BIT(2)
    390#define B_AX_GT3_INT_EN BIT(1)
    391#define B_AX_C2H_INT_EN BIT(0)
    392#define R_AX_HD0ISR 0x8114
    393#define B_AX_C2H_INT BIT(0)
    394
    395#define R_AX_H2CREG_DATA0 0x8140
    396#define R_AX_H2CREG_DATA1 0x8144
    397#define R_AX_H2CREG_DATA2 0x8148
    398#define R_AX_H2CREG_DATA3 0x814C
    399#define R_AX_C2HREG_DATA0 0x8150
    400#define R_AX_C2HREG_DATA1 0x8154
    401#define R_AX_C2HREG_DATA2 0x8158
    402#define R_AX_C2HREG_DATA3 0x815C
    403#define R_AX_H2CREG_CTRL 0x8160
    404#define B_AX_H2CREG_TRIGGER BIT(0)
    405#define R_AX_C2HREG_CTRL 0x8164
    406#define B_AX_C2HREG_TRIGGER BIT(0)
    407#define R_AX_CPWM 0x8170
    408
    409#define R_AX_HCI_FUNC_EN 0x8380
    410#define B_AX_HCI_RXDMA_EN BIT(1)
    411#define B_AX_HCI_TXDMA_EN BIT(0)
    412
    413#define R_AX_BOOT_DBG 0x83F0
    414
    415#define R_AX_DMAC_FUNC_EN 0x8400
    416#define B_AX_DMAC_CRPRT BIT(31)
    417#define B_AX_MAC_FUNC_EN BIT(30)
    418#define B_AX_DMAC_FUNC_EN BIT(29)
    419#define B_AX_MPDU_PROC_EN BIT(28)
    420#define B_AX_WD_RLS_EN BIT(27)
    421#define B_AX_DLE_WDE_EN BIT(26)
    422#define B_AX_TXPKT_CTRL_EN BIT(25)
    423#define B_AX_STA_SCH_EN BIT(24)
    424#define B_AX_DLE_PLE_EN BIT(23)
    425#define B_AX_PKT_BUF_EN BIT(22)
    426#define B_AX_DMAC_TBL_EN BIT(21)
    427#define B_AX_PKT_IN_EN BIT(20)
    428#define B_AX_DLE_CPUIO_EN BIT(19)
    429#define B_AX_DISPATCHER_EN BIT(18)
    430#define B_AX_BBRPT_EN BIT(17)
    431#define B_AX_MAC_SEC_EN BIT(16)
    432#define B_AX_MAC_UN_EN BIT(15)
    433#define B_AX_H_AXIDMA_EN BIT(14)
    434
    435#define R_AX_DMAC_CLK_EN 0x8404
    436#define B_AX_WD_RLS_CLK_EN BIT(27)
    437#define B_AX_DLE_WDE_CLK_EN BIT(26)
    438#define B_AX_TXPKT_CTRL_CLK_EN BIT(25)
    439#define B_AX_STA_SCH_CLK_EN BIT(24)
    440#define B_AX_DLE_PLE_CLK_EN BIT(23)
    441#define B_AX_PKT_IN_CLK_EN BIT(20)
    442#define B_AX_DLE_CPUIO_CLK_EN BIT(19)
    443#define B_AX_DISPATCHER_CLK_EN BIT(18)
    444#define B_AX_BBRPT_CLK_EN BIT(17)
    445#define B_AX_MAC_SEC_CLK_EN BIT(16)
    446
    447#define PCI_LTR_IDLE_TIMER_1US 0
    448#define PCI_LTR_IDLE_TIMER_10US 1
    449#define PCI_LTR_IDLE_TIMER_100US 2
    450#define PCI_LTR_IDLE_TIMER_200US 3
    451#define PCI_LTR_IDLE_TIMER_400US 4
    452#define PCI_LTR_IDLE_TIMER_800US 5
    453#define PCI_LTR_IDLE_TIMER_1_6MS 6
    454#define PCI_LTR_IDLE_TIMER_3_2MS 7
    455#define PCI_LTR_IDLE_TIMER_R_ERR 0xFD
    456#define PCI_LTR_IDLE_TIMER_DEF 0xFE
    457#define PCI_LTR_IDLE_TIMER_IGNORE 0xFF
    458
    459#define PCI_LTR_SPC_10US 0
    460#define PCI_LTR_SPC_100US 1
    461#define PCI_LTR_SPC_500US 2
    462#define PCI_LTR_SPC_1MS 3
    463#define PCI_LTR_SPC_R_ERR 0xFD
    464#define PCI_LTR_SPC_DEF 0xFE
    465#define PCI_LTR_SPC_IGNORE 0xFF
    466
    467#define R_AX_LTR_CTRL_0 0x8410
    468#define B_AX_LTR_SPACE_IDX_MASK GENMASK(13, 12)
    469#define B_AX_LTR_IDLE_TIMER_IDX_MASK GENMASK(10, 8)
    470#define B_AX_APP_LTR_ACT BIT(5)
    471#define B_AX_APP_LTR_IDLE BIT(4)
    472#define B_AX_LTR_EN BIT(1)
    473#define B_AX_LTR_WD_NOEMP_CHK_V1 BIT(1)
    474#define B_AX_LTR_HW_EN BIT(0)
    475
    476#define R_AX_LTR_CTRL_1 0x8414
    477#define B_AX_LTR_RX1_TH_MASK GENMASK(27, 16)
    478#define B_AX_LTR_RX0_TH_MASK GENMASK(11, 0)
    479
    480#define R_AX_LTR_IDLE_LATENCY 0x8418
    481
    482#define R_AX_LTR_ACTIVE_LATENCY 0x841C
    483
    484#define R_AX_SER_DBG_INFO 0x8424
    485#define B_AX_L0_TO_L1_EVENT_MASK GENMASK(31, 28)
    486
    487#define R_AX_DLE_EMPTY0 0x8430
    488#define B_AX_PLE_EMPTY_QTA_DMAC_CPUIO BIT(26)
    489#define B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX BIT(25)
    490#define B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU BIT(24)
    491#define B_AX_PLE_EMPTY_QTA_DMAC_H2C BIT(23)
    492#define B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL BIT(22)
    493#define B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL BIT(21)
    494#define B_AX_WDE_EMPTY_QTA_DMAC_CPUIO BIT(20)
    495#define B_AX_WDE_EMPTY_QTA_DMAC_PKTIN BIT(19)
    496#define B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU BIT(18)
    497#define B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU BIT(17)
    498#define B_AX_WDE_EMPTY_QTA_DMAC_HIF BIT(16)
    499#define B_AX_WDE_EMPTY_QUE_DMAC_PKTIN BIT(10)
    500#define B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX BIT(9)
    501#define B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX BIT(8)
    502#define B_AX_WDE_EMPTY_QUE_OTHERS BIT(7)
    503#define B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 BIT(4)
    504#define B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 BIT(3)
    505#define B_AX_WDE_EMPTY_QUE_CMAC1_MBH BIT(2)
    506#define B_AX_WDE_EMPTY_QUE_CMAC0_MBH BIT(1)
    507#define B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC BIT(0)
    508
    509#define R_AX_DMAC_ERR_IMR 0x8520
    510#define B_AX_DLE_CPUIO_ERR_INT_EN BIT(10)
    511#define B_AX_APB_BRIDGE_ERR_INT_EN BIT(9)
    512#define B_AX_DISPATCH_ERR_INT_EN BIT(8)
    513#define B_AX_PKTIN_ERR_INT_EN BIT(7)
    514#define B_AX_PLE_DLE_ERR_INT_EN BIT(6)
    515#define B_AX_TXPKTCTRL_ERR_INT_EN BIT(5)
    516#define B_AX_WDE_DLE_ERR_INT_EN BIT(4)
    517#define B_AX_STA_SCHEDULER_ERR_INT_EN BIT(3)
    518#define B_AX_MPDU_ERR_INT_EN BIT(2)
    519#define B_AX_WSEC_ERR_INT_EN BIT(1)
    520#define B_AX_WDRLS_ERR_INT_EN BIT(0)
    521#define DMAC_ERR_IMR_EN GENMASK(31, 0)
    522#define DMAC_ERR_IMR_DIS 0
    523
    524#define R_AX_DMAC_ERR_ISR 0x8524
    525#define B_AX_DLE_CPUIO_ERR_FLAG BIT(10)
    526#define B_AX_APB_BRIDGE_ERR_FLAG BIT(9)
    527#define B_AX_DISPATCH_ERR_FLAG BIT(8)
    528#define B_AX_PKTIN_ERR_FLAG BIT(7)
    529#define B_AX_PLE_DLE_ERR_FLAG BIT(6)
    530#define B_AX_TXPKTCTRL_ERR_FLAG BIT(5)
    531#define B_AX_WDE_DLE_ERR_FLAG BIT(4)
    532#define B_AX_STA_SCHEDULER_ERR_FLAG BIT(3)
    533#define B_AX_MPDU_ERR_FLAG BIT(2)
    534#define B_AX_WSEC_ERR_FLAG BIT(1)
    535#define B_AX_WDRLS_ERR_FLAG BIT(0)
    536
    537#define R_AX_DISPATCHER_GLOBAL_SETTING_0 0x8800
    538#define B_AX_PL_PAGE_128B_SEL BIT(9)
    539#define B_AX_WD_PAGE_64B_SEL BIT(8)
    540#define R_AX_OTHER_DISPATCHER_ERR_ISR 0x8804
    541#define R_AX_HOST_DISPATCHER_ERR_ISR 0x8808
    542#define R_AX_CPU_DISPATCHER_ERR_ISR 0x880C
    543#define R_AX_TX_ADDRESS_INFO_MODE_SETTING 0x8810
    544#define B_AX_HOST_ADDR_INFO_8B_SEL BIT(0)
    545
    546#define R_AX_HOST_DISPATCHER_ERR_IMR 0x8850
    547#define B_AX_HDT_RX_WRITE_UNDERFLOW_INT_EN BIT(31)
    548#define B_AX_HDT_RX_WRITE_OVERFLOW_INT_EN BIT(30)
    549#define B_AX_HDT_CHKSUM_FSM_ERR_INT_EN BIT(29)
    550#define B_AX_HDT_SHIFT_DMA_CFG_ERR_INT_EN BIT(28)
    551#define B_AX_HDT_DMA_PROCESS_ERR_INT_EN BIT(27)
    552#define B_AX_HDT_TOTAL_LEN_ERR_INT_EN BIT(26)
    553#define B_AX_HDT_SHIFT_EN_ERR_INT_EN BIT(25)
    554#define B_AX_HDT_RXAGG_CFG_ERR_INT_EN BIT(24)
    555#define B_AX_HDT_OUTPUT_ERR_INT_EN BIT(21)
    556#define B_AX_HDT_RES_ERR_INT_EN BIT(20)
    557#define B_AX_HDT_BURST_NUM_ERR_INT_EN BIT(19)
    558#define B_AX_HDT_NULLPKT_ERR_INT_EN BIT(18)
    559#define B_AX_HDT_FLOW_CTRL_ERR_INT_EN BIT(17)
    560#define B_AX_HDT_PLD_CMD_UNDERFLOW_INT_EN BIT(16)
    561#define B_AX_HDT_PLD_CMD_OVERLOW_INT_EN BIT(15)
    562#define B_AX_HDT_TX_WRITE_UNDERFLOW_INT_EN BIT(14)
    563#define B_AX_HDT_TX_WRITE_OVERFLOW_INT_EN BIT(13)
    564#define B_AX_HDT_TCP_CHK_ERR_INT_EN BIT(12)
    565#define B_AX_HDT_TXPKTSIZE_ERR_INT_EN BIT(11)
    566#define B_AX_HDT_PRE_COST_ERR_INT_EN BIT(10)
    567#define B_AX_HDT_WD_CHK_ERR_INT_EN BIT(9)
    568#define B_AX_HDT_CHANNEL_DMA_ERR_INT_EN BIT(8)
    569#define B_AX_HDT_OFFSET_UNMATCH_INT_EN BIT(7)
    570#define B_AX_HDT_PAYLOAD_UNDERFLOW_INT_EN BIT(6)
    571#define B_AX_HDT_PAYLOAD_OVERFLOW_INT_EN BIT(5)
    572#define B_AX_HDT_PERMU_UNDERFLOW_INT_EN BIT(4)
    573#define B_AX_HDT_PERMU_OVERFLOW_INT_EN BIT(3)
    574#define B_AX_HDT_PKT_FAIL_DBG_INT_EN BIT(2)
    575#define B_AX_HDT_CHANNEL_ID_ERR_INT_EN BIT(1)
    576#define B_AX_HDT_CHANNEL_DIFF_ERR_INT_EN BIT(0)
    577#define B_AX_HOST_DISP_IMR_CLR (B_AX_HDT_CHANNEL_DIFF_ERR_INT_EN | \
    578				B_AX_HDT_CHANNEL_ID_ERR_INT_EN | \
    579				B_AX_HDT_PKT_FAIL_DBG_INT_EN | \
    580				B_AX_HDT_PERMU_OVERFLOW_INT_EN | \
    581				B_AX_HDT_PERMU_UNDERFLOW_INT_EN | \
    582				B_AX_HDT_PAYLOAD_OVERFLOW_INT_EN | \
    583				B_AX_HDT_PAYLOAD_UNDERFLOW_INT_EN | \
    584				B_AX_HDT_OFFSET_UNMATCH_INT_EN | \
    585				B_AX_HDT_CHANNEL_DMA_ERR_INT_EN | \
    586				B_AX_HDT_WD_CHK_ERR_INT_EN | \
    587				B_AX_HDT_PRE_COST_ERR_INT_EN | \
    588				B_AX_HDT_TXPKTSIZE_ERR_INT_EN | \
    589				B_AX_HDT_TCP_CHK_ERR_INT_EN | \
    590				B_AX_HDT_TX_WRITE_OVERFLOW_INT_EN | \
    591				B_AX_HDT_TX_WRITE_UNDERFLOW_INT_EN | \
    592				B_AX_HDT_PLD_CMD_OVERLOW_INT_EN | \
    593				B_AX_HDT_PLD_CMD_UNDERFLOW_INT_EN | \
    594				B_AX_HDT_FLOW_CTRL_ERR_INT_EN | \
    595				B_AX_HDT_NULLPKT_ERR_INT_EN | \
    596				B_AX_HDT_BURST_NUM_ERR_INT_EN | \
    597				B_AX_HDT_RXAGG_CFG_ERR_INT_EN | \
    598				B_AX_HDT_SHIFT_EN_ERR_INT_EN | \
    599				B_AX_HDT_TOTAL_LEN_ERR_INT_EN | \
    600				B_AX_HDT_DMA_PROCESS_ERR_INT_EN | \
    601				B_AX_HDT_SHIFT_DMA_CFG_ERR_INT_EN | \
    602				B_AX_HDT_CHKSUM_FSM_ERR_INT_EN | \
    603				B_AX_HDT_RX_WRITE_OVERFLOW_INT_EN | \
    604				B_AX_HDT_RX_WRITE_UNDERFLOW_INT_EN)
    605#define B_AX_HOST_DISP_IMR_SET (B_AX_HDT_CHANNEL_DIFF_ERR_INT_EN | \
    606				B_AX_HDT_PAYLOAD_OVERFLOW_INT_EN | \
    607				B_AX_HDT_PAYLOAD_UNDERFLOW_INT_EN | \
    608				B_AX_HDT_CHANNEL_DMA_ERR_INT_EN | \
    609				B_AX_HDT_TOTAL_LEN_ERR_INT_EN | \
    610				B_AX_HDT_DMA_PROCESS_ERR_INT_EN)
    611
    612#define B_AX_HR_WRFF_UNDERFLOW_ERR_INT_EN BIT(31)
    613#define B_AX_HR_WRFF_OVERFLOW_ERR_INT_EN BIT(30)
    614#define B_AX_HR_CHKSUM_FSM_ERR_INT_EN BIT(29)
    615#define B_AX_HR_SHIFT_DMA_CFG_ERR_INT_EN BIT(28)
    616#define B_AX_HR_DMA_PROCESS_ERR_INT_EN BIT(27)
    617#define B_AX_HR_TOTAL_LEN_UNDER_ERR_INT_EN BIT(26)
    618#define B_AX_HR_SHIFT_EN_ERR_INT_EN BIT(25)
    619#define B_AX_HR_AGG_CFG_ERR_INT_EN BIT(24)
    620#define B_AX_HR_DMA_RD_CNT_DEQ_ERR_INT_EN BIT(23)
    621#define B_AX_HR_PLD_LEN_ZERO_ERR_INT_EN BIT(22)
    622#define B_AX_HT_ILL_CH_ERR_INT_EN BIT(20)
    623#define B_AX_HT_ADDR_INFO_LEN_ERR_INT_EN BIT(18)
    624#define B_AX_HT_WD_LEN_OVER_ERR_INT_EN BIT(17)
    625#define B_AX_HT_PLD_CMD_UNDERFLOW_ERR_INT_EN BIT(16)
    626#define B_AX_HT_PLD_CMD_OVERFLOW_ERR_INT_EN BIT(15)
    627#define B_AX_HT_WRFF_UNDERFLOW_ERR_INT_EN BIT(14)
    628#define B_AX_HT_WRFF_OVERFLOW_ERR_INT_EN BIT(13)
    629#define B_AX_HT_CHKSUM_FSM_ERR_INT_EN BIT(12)
    630#define B_AX_HT_TXPKTSIZE_ERR_INT_EN BIT(11)
    631#define B_AX_HT_PRE_SUB_ERR_INT_EN BIT(10)
    632#define B_AX_HT_WD_CHKSUM_ERR_INT_EN BIT(9)
    633#define B_AX_HT_CHANNEL_DMA_ERR_INT_EN BIT(8)
    634#define B_AX_HT_OFFSET_UNMATCH_ERR_INT_EN BIT(7)
    635#define B_AX_HT_PAYLOAD_UNDER_ERR_INT_EN BIT(6)
    636#define B_AX_HT_PAYLOAD_OVER_ERR_INT_EN BIT(5)
    637#define B_AX_HT_PERMU_FF_UNDERFLOW_ERR_INT_EN BIT(4)
    638#define B_AX_HT_PERMU_FF_OVERFLOW_ERR_INT_EN BIT(3)
    639#define B_AX_HT_PKT_FAIL_ERR_INT_EN BIT(2)
    640#define B_AX_HT_CH_ID_ERR_INT_EN BIT(1)
    641#define B_AX_HT_EP_CH_DIFF_ERR_INT_EN BIT(0)
    642#define B_AX_HOST_DISP_IMR_CLR_V1 (B_AX_HT_EP_CH_DIFF_ERR_INT_EN | \
    643				   B_AX_HT_CH_ID_ERR_INT_EN | \
    644				   B_AX_HT_PKT_FAIL_ERR_INT_EN | \
    645				   B_AX_HT_PERMU_FF_OVERFLOW_ERR_INT_EN | \
    646				   B_AX_HT_PERMU_FF_UNDERFLOW_ERR_INT_EN | \
    647				   B_AX_HT_PAYLOAD_OVER_ERR_INT_EN | \
    648				   B_AX_HT_PAYLOAD_UNDER_ERR_INT_EN | \
    649				   B_AX_HT_OFFSET_UNMATCH_ERR_INT_EN | \
    650				   B_AX_HT_CHANNEL_DMA_ERR_INT_EN | \
    651				   B_AX_HT_WD_CHKSUM_ERR_INT_EN | \
    652				   B_AX_HT_PRE_SUB_ERR_INT_EN | \
    653				   B_AX_HT_TXPKTSIZE_ERR_INT_EN | \
    654				   B_AX_HT_CHKSUM_FSM_ERR_INT_EN | \
    655				   B_AX_HT_WRFF_OVERFLOW_ERR_INT_EN | \
    656				   B_AX_HT_WRFF_UNDERFLOW_ERR_INT_EN | \
    657				   B_AX_HT_PLD_CMD_OVERFLOW_ERR_INT_EN | \
    658				   B_AX_HT_PLD_CMD_UNDERFLOW_ERR_INT_EN | \
    659				   B_AX_HT_WD_LEN_OVER_ERR_INT_EN | \
    660				   B_AX_HT_ADDR_INFO_LEN_ERR_INT_EN | \
    661				   B_AX_HT_ILL_CH_ERR_INT_EN | \
    662				   B_AX_HR_PLD_LEN_ZERO_ERR_INT_EN | \
    663				   B_AX_HR_DMA_RD_CNT_DEQ_ERR_INT_EN | \
    664				   B_AX_HR_AGG_CFG_ERR_INT_EN | \
    665				   B_AX_HR_SHIFT_EN_ERR_INT_EN | \
    666				   B_AX_HR_TOTAL_LEN_UNDER_ERR_INT_EN | \
    667				   B_AX_HR_DMA_PROCESS_ERR_INT_EN | \
    668				   B_AX_HR_SHIFT_DMA_CFG_ERR_INT_EN | \
    669				   B_AX_HR_CHKSUM_FSM_ERR_INT_EN | \
    670				   B_AX_HR_WRFF_OVERFLOW_ERR_INT_EN | \
    671				   B_AX_HR_WRFF_UNDERFLOW_ERR_INT_EN)
    672#define B_AX_HOST_DISP_IMR_SET_V1 (B_AX_HT_PAYLOAD_OVER_ERR_INT_EN | \
    673				   B_AX_HT_PAYLOAD_UNDER_ERR_INT_EN | \
    674				   B_AX_HT_ILL_CH_ERR_INT_EN | \
    675				   B_AX_HR_TOTAL_LEN_UNDER_ERR_INT_EN | \
    676				   B_AX_HR_DMA_PROCESS_ERR_INT_EN)
    677
    678#define R_AX_CPU_DISPATCHER_ERR_IMR 0x8854
    679#define B_AX_CPU_RX_WRITE_UNDERFLOW_INT_EN BIT(31)
    680#define B_AX_CPU_RX_WRITE_OVERFLOW_INT_EN BIT(30)
    681#define B_AX_CPU_CHKSUM_FSM_ERR_INT_EN BIT(29)
    682#define B_AX_CPU_SHIFT_DMA_CFG_ERR_INT_EN BIT(28)
    683#define B_AX_CPU_DMA_PROCESS_ERR_INT_EN BIT(27)
    684#define B_AX_CPU_TOTAL_LEN_ERR_INT_EN BIT(26)
    685#define B_AX_CPU_SHIFT_EN_ERR_INT_EN BIT(25)
    686#define B_AX_CPU_RXAGG_CFG_ERR_INT_EN BIT(24)
    687#define B_AX_CPU_OUTPUT_ERR_INT_EN BIT(20)
    688#define B_AX_CPU_RESP_ERR_INT_EN BIT(19)
    689#define B_AX_CPU_BURST_NUM_ERR_INT_EN BIT(18)
    690#define B_AX_CPU_NULLPKT_ERR_INT_EN BIT(17)
    691#define B_AX_CPU_FLOW_CTRL_ERR_INT_EN BIT(16)
    692#define B_AX_CPU_F2P_SEQ_ERR_INT_EN BIT(15)
    693#define B_AX_CPU_F2P_QSEL_ERR_INT_EN BIT(14)
    694#define B_AX_CPU_PLD_CMD_UNDERFLOW_INT_EN BIT(13)
    695#define B_AX_CPU_PLD_CMD_OVERLOW_INT_EN BIT(12)
    696#define B_AX_CPU_PRE_COST_ERR_INT_EN BIT(11)
    697#define B_AX_CPU_WD_CHK_ERR_INT_EN BIT(10)
    698#define B_AX_CPU_CHANNEL_DMA_ERR_INT_EN BIT(9)
    699#define B_AX_CPU_OFFSET_UNMATCH_INT_EN BIT(8)
    700#define B_AX_CPU_PAYLOAD_CHKSUM_ERR_INT_EN BIT(7)
    701#define B_AX_CPU_PAYLOAD_UNDERFLOW_INT_EN BIT(6)
    702#define B_AX_CPU_PAYLOAD_OVERFLOW_INT_EN BIT(5)
    703#define B_AX_CPU_PERMU_UNDERFLOW_INT_EN BIT(4)
    704#define B_AX_CPU_PERMU_OVERFLOW_INT_EN BIT(3)
    705#define B_AX_CPU_CHANNEL_ID_ERR_INT_EN BIT(2)
    706#define B_AX_CPU_PKT_FAIL_DBG_INT_EN BIT(1)
    707#define B_AX_CPU_CHANNEL_DIFF_ERR_INT_EN BIT(0)
    708#define B_AX_CPU_DISP_IMR_CLR (B_AX_CPU_CHANNEL_DIFF_ERR_INT_EN | \
    709			       B_AX_CPU_PKT_FAIL_DBG_INT_EN | \
    710			       B_AX_CPU_CHANNEL_ID_ERR_INT_EN | \
    711			       B_AX_CPU_PERMU_OVERFLOW_INT_EN | \
    712			       B_AX_CPU_PERMU_UNDERFLOW_INT_EN | \
    713			       B_AX_CPU_PAYLOAD_OVERFLOW_INT_EN | \
    714			       B_AX_CPU_PAYLOAD_UNDERFLOW_INT_EN | \
    715			       B_AX_CPU_PAYLOAD_CHKSUM_ERR_INT_EN | \
    716			       B_AX_CPU_OFFSET_UNMATCH_INT_EN | \
    717			       B_AX_CPU_CHANNEL_DMA_ERR_INT_EN | \
    718			       B_AX_CPU_WD_CHK_ERR_INT_EN | \
    719			       B_AX_CPU_PRE_COST_ERR_INT_EN | \
    720			       B_AX_CPU_PLD_CMD_OVERLOW_INT_EN | \
    721			       B_AX_CPU_PLD_CMD_UNDERFLOW_INT_EN | \
    722			       B_AX_CPU_F2P_QSEL_ERR_INT_EN | \
    723			       B_AX_CPU_F2P_SEQ_ERR_INT_EN | \
    724			       B_AX_CPU_FLOW_CTRL_ERR_INT_EN | \
    725			       B_AX_CPU_NULLPKT_ERR_INT_EN | \
    726			       B_AX_CPU_BURST_NUM_ERR_INT_EN | \
    727			       B_AX_CPU_RXAGG_CFG_ERR_INT_EN | \
    728			       B_AX_CPU_SHIFT_EN_ERR_INT_EN | \
    729			       B_AX_CPU_TOTAL_LEN_ERR_INT_EN | \
    730			       B_AX_CPU_DMA_PROCESS_ERR_INT_EN | \
    731			       B_AX_CPU_SHIFT_DMA_CFG_ERR_INT_EN | \
    732			       B_AX_CPU_CHKSUM_FSM_ERR_INT_EN | \
    733			       B_AX_CPU_RX_WRITE_OVERFLOW_INT_EN | \
    734			       B_AX_CPU_RX_WRITE_UNDERFLOW_INT_EN)
    735#define B_AX_CPU_DISP_IMR_SET (B_AX_CPU_PKT_FAIL_DBG_INT_EN | \
    736			       B_AX_CPU_PAYLOAD_OVERFLOW_INT_EN | \
    737			       B_AX_CPU_PAYLOAD_UNDERFLOW_INT_EN | \
    738			       B_AX_CPU_TOTAL_LEN_ERR_INT_EN)
    739
    740#define B_AX_CR_PLD_LEN_ERR_INT_EN BIT(30)
    741#define B_AX_CR_WRFF_UNDERFLOW_ERR_INT_EN BIT(29)
    742#define B_AX_CR_WRFF_OVERFLOW_ERR_INT_EN BIT(28)
    743#define B_AX_CR_SHIFT_DMA_CFG_ERR_INT_EN BIT(27)
    744#define B_AX_CR_DMA_PROCESS_ERR_INT_EN BIT(26)
    745#define B_AX_CR_TOTAL_LEN_UNDER_ERR_INT_EN BIT(25)
    746#define B_AX_CR_SHIFT_EN_ERR_INT_EN BIT(24)
    747#define B_AX_REUSE_FIFO_B_UNDER_ERR_INT_EN BIT(22)
    748#define B_AX_REUSE_FIFO_B_OVER_ERR_INT_EN BIT(21)
    749#define B_AX_REUSE_FIFO_A_UNDER_ERR_INT_EN BIT(20)
    750#define B_AX_REUSE_FIFO_A_OVER_ERR_INT_EN BIT(19)
    751#define B_AX_CT_ADDR_INFO_LEN_MISS_ERR_INT_EN BIT(17)
    752#define B_AX_CT_WD_LEN_OVER_ERR_INT_EN BIT(16)
    753#define B_AX_CT_F2P_SEQ_ERR_INT_EN BIT(15)
    754#define B_AX_CT_F2P_QSEL_ERR_INT_EN BIT(14)
    755#define B_AX_CT_PLD_CMD_UNDERFLOW_ERR_INT_EN BIT(13)
    756#define B_AX_CT_PLD_CMD_OVERFLOW_ERR_INT_EN BIT(12)
    757#define B_AX_CT_PRE_SUB_ERR_INT_EN BIT(11)
    758#define B_AX_CT_WD_CHKSUM_ERR_INT_EN BIT(10)
    759#define B_AX_CT_CHANNEL_DMA_ERR_INT_EN BIT(9)
    760#define B_AX_CT_OFFSET_UNMATCH_ERR_INT_EN BIT(8)
    761#define B_AX_CT_PAYLOAD_CHKSUM_ERR_INT_EN BIT(7)
    762#define B_AX_CT_PAYLOAD_UNDER_ERR_INT_EN BIT(6)
    763#define B_AX_CT_PAYLOAD_OVER_ERR_INT_EN BIT(5)
    764#define B_AX_CT_PERMU_FF_UNDERFLOW_ERR_INT_EN BIT(4)
    765#define B_AX_CT_PERMU_FF_OVERFLOW_ERR_INT_EN BIT(3)
    766#define B_AX_CT_CH_ID_ERR_INT_EN BIT(2)
    767#define B_AX_CT_EP_CH_DIFF_ERR_INT_EN BIT(0)
    768#define B_AX_CPU_DISP_IMR_CLR_V1 (B_AX_CT_EP_CH_DIFF_ERR_INT_EN | \
    769				  B_AX_CT_CH_ID_ERR_INT_EN | \
    770				  B_AX_CT_PERMU_FF_OVERFLOW_ERR_INT_EN | \
    771				  B_AX_CT_PERMU_FF_UNDERFLOW_ERR_INT_EN | \
    772				  B_AX_CT_PAYLOAD_OVER_ERR_INT_EN | \
    773				  B_AX_CT_PAYLOAD_UNDER_ERR_INT_EN | \
    774				  B_AX_CT_PAYLOAD_CHKSUM_ERR_INT_EN | \
    775				  B_AX_CT_OFFSET_UNMATCH_ERR_INT_EN | \
    776				  B_AX_CT_CHANNEL_DMA_ERR_INT_EN | \
    777				  B_AX_CT_WD_CHKSUM_ERR_INT_EN | \
    778				  B_AX_CT_PRE_SUB_ERR_INT_EN | \
    779				  B_AX_CT_PLD_CMD_OVERFLOW_ERR_INT_EN | \
    780				  B_AX_CT_PLD_CMD_UNDERFLOW_ERR_INT_EN | \
    781				  B_AX_CT_F2P_QSEL_ERR_INT_EN | \
    782				  B_AX_CT_F2P_SEQ_ERR_INT_EN | \
    783				  B_AX_CT_WD_LEN_OVER_ERR_INT_EN | \
    784				  B_AX_CT_ADDR_INFO_LEN_MISS_ERR_INT_EN | \
    785				  B_AX_REUSE_FIFO_A_OVER_ERR_INT_EN | \
    786				  B_AX_REUSE_FIFO_A_UNDER_ERR_INT_EN | \
    787				  B_AX_REUSE_FIFO_B_OVER_ERR_INT_EN | \
    788				  B_AX_REUSE_FIFO_B_UNDER_ERR_INT_EN | \
    789				  B_AX_CR_SHIFT_EN_ERR_INT_EN | \
    790				  B_AX_CR_TOTAL_LEN_UNDER_ERR_INT_EN | \
    791				  B_AX_CR_DMA_PROCESS_ERR_INT_EN | \
    792				  B_AX_CR_SHIFT_DMA_CFG_ERR_INT_EN | \
    793				  B_AX_CR_WRFF_OVERFLOW_ERR_INT_EN | \
    794				  B_AX_CR_WRFF_UNDERFLOW_ERR_INT_EN | \
    795				  B_AX_CR_PLD_LEN_ERR_INT_EN)
    796#define B_AX_CPU_DISP_IMR_SET_V1 (B_AX_CT_PAYLOAD_OVER_ERR_INT_EN | \
    797				  B_AX_CT_PAYLOAD_UNDER_ERR_INT_EN | \
    798				  B_AX_CR_TOTAL_LEN_UNDER_ERR_INT_EN | \
    799				  B_AX_CR_DMA_PROCESS_ERR_INT_EN | \
    800				  B_AX_CR_WRFF_OVERFLOW_ERR_INT_EN | \
    801				  B_AX_CR_WRFF_UNDERFLOW_ERR_INT_EN)
    802
    803#define R_AX_OTHER_DISPATCHER_ERR_IMR 0x8858
    804#define B_AX_OTHER_STF_WROQT_UNDERFLOW_INT_EN BIT(29)
    805#define B_AX_OTHER_STF_WROQT_OVERFLOW_INT_EN BIT(28)
    806#define B_AX_OTHER_STF_WRFF_UNDERFLOW_INT_EN BIT(27)
    807#define B_AX_OTHER_STF_WRFF_OVERFLOW_INT_EN BIT(26)
    808#define B_AX_OTHER_STF_CMD_UNDERFLOW_INT_EN BIT(25)
    809#define B_AX_OTHER_STF_CMD_OVERFLOW_INT_EN BIT(24)
    810#define B_AX_HOST_ADDR_INFO_LEN_ZERO_ERR_INT_EN BIT(17)
    811#define B_AX_CPU_ADDR_INFO_LEN_ZERO_ERR_INT_EN BIT(16)
    812#define B_AX_PLE_OUTPUT_ERR_INT_EN BIT(12)
    813#define B_AX_PLE_RESP_ERR_INT_EN BIT(11)
    814#define B_AX_PLE_BURST_NUM_ERR_INT_EN BIT(10)
    815#define B_AX_PLE_NULL_PKT_ERR_INT_EN BIT(9)
    816#define B_AX_PLE_FLOW_CTRL_ERR_INT_EN BIT(8)
    817#define B_AX_WDE_OUTPUT_ERR_INT_EN BIT(4)
    818#define B_AX_WDE_RESP_ERR_INT_EN BIT(3)
    819#define B_AX_WDE_BURST_NUM_ERR_INT_EN BIT(2)
    820#define B_AX_WDE_NULL_PKT_ERR_INT_EN BIT(1)
    821#define B_AX_WDE_FLOW_CTRL_ERR_INT_EN BIT(0)
    822#define B_AX_OTHER_DISP_IMR_CLR (B_AX_OTHER_STF_WROQT_UNDERFLOW_INT_EN | \
    823				 B_AX_OTHER_STF_WROQT_OVERFLOW_INT_EN | \
    824				 B_AX_OTHER_STF_WRFF_UNDERFLOW_INT_EN | \
    825				 B_AX_OTHER_STF_WRFF_OVERFLOW_INT_EN | \
    826				 B_AX_OTHER_STF_CMD_UNDERFLOW_INT_EN | \
    827				 B_AX_OTHER_STF_CMD_OVERFLOW_INT_EN | \
    828				 B_AX_HOST_ADDR_INFO_LEN_ZERO_ERR_INT_EN | \
    829				 B_AX_CPU_ADDR_INFO_LEN_ZERO_ERR_INT_EN | \
    830				 B_AX_PLE_OUTPUT_ERR_INT_EN | \
    831				 B_AX_PLE_RESP_ERR_INT_EN | \
    832				 B_AX_PLE_BURST_NUM_ERR_INT_EN | \
    833				 B_AX_PLE_NULL_PKT_ERR_INT_EN | \
    834				 B_AX_PLE_FLOW_CTRL_ERR_INT_EN | \
    835				 B_AX_WDE_OUTPUT_ERR_INT_EN | \
    836				 B_AX_WDE_RESP_ERR_INT_EN | \
    837				 B_AX_WDE_BURST_NUM_ERR_INT_EN | \
    838				 B_AX_WDE_NULL_PKT_ERR_INT_EN | \
    839				 B_AX_WDE_FLOW_CTRL_ERR_INT_EN)
    840
    841#define B_AX_REUSE_SIZE_ERR_INT_EN BIT(31)
    842#define B_AX_REUSE_EN_ERR_INT_EN BIT(30)
    843#define B_AX_STF_OQT_UNDERFLOW_ERR_INT_EN BIT(29)
    844#define B_AX_STF_OQT_OVERFLOW_ERR_INT_EN BIT(28)
    845#define B_AX_STF_WRFF_UNDERFLOW_ERR_INT_EN BIT(27)
    846#define B_AX_STF_WRFF_OVERFLOW_ERR_INT_EN BIT(26)
    847#define B_AX_STF_CMD_UNDERFLOW_ERR_INT_EN BIT(25)
    848#define B_AX_STF_CMD_OVERFLOW_ERR_INT_EN BIT(24)
    849#define B_AX_REUSE_SIZE_ZERO_ERR_INT_EN BIT(23)
    850#define B_AX_REUSE_PKT_CNT_ERR_INT_EN BIT(22)
    851#define B_AX_CDT_PTR_TIMEOUT_ERR_INT_EN BIT(21)
    852#define B_AX_CDT_HCI_TIMEOUT_ERR_INT_EN BIT(20)
    853#define B_AX_HDT_PTR_TIMEOUT_ERR_INT_EN BIT(19)
    854#define B_AX_HDT_HCI_TIMEOUT_ERR_INT_EN BIT(18)
    855#define B_AX_CDT_ADDR_INFO_LEN_ERR_INT_EN BIT(17)
    856#define B_AX_HDT_ADDR_INFO_LEN_ERR_INT_EN BIT(16)
    857#define B_AX_CDR_DMA_TIMEOUT_ERR_INT_EN BIT(15)
    858#define B_AX_CDR_RX_TIMEOUT_ERR_INT_EN BIT(14)
    859#define B_AX_PLE_RESPOSE_ERR_INT_EN BIT(11)
    860#define B_AX_HDR_DMA_TIMEOUT_ERR_INT_EN BIT(7)
    861#define B_AX_HDR_RX_TIMEOUT_ERR_INT_EN BIT(6)
    862#define B_AX_WDE_RESPONSE_ERR_INT_EN BIT(3)
    863#define B_AX_OTHER_DISP_IMR_CLR_V1 (B_AX_CT_EP_CH_DIFF_ERR_INT_EN | \
    864				    B_AX_WDE_FLOW_CTRL_ERR_INT_EN | \
    865				    B_AX_WDE_NULL_PKT_ERR_INT_EN | \
    866				    B_AX_WDE_BURST_NUM_ERR_INT_EN | \
    867				    B_AX_WDE_RESPONSE_ERR_INT_EN | \
    868				    B_AX_WDE_OUTPUT_ERR_INT_EN | \
    869				    B_AX_HDR_RX_TIMEOUT_ERR_INT_EN | \
    870				    B_AX_HDR_DMA_TIMEOUT_ERR_INT_EN | \
    871				    B_AX_PLE_FLOW_CTRL_ERR_INT_EN | \
    872				    B_AX_PLE_NULL_PKT_ERR_INT_EN | \
    873				    B_AX_PLE_BURST_NUM_ERR_INT_EN | \
    874				    B_AX_PLE_RESPOSE_ERR_INT_EN | \
    875				    B_AX_PLE_OUTPUT_ERR_INT_EN | \
    876				    B_AX_CDR_RX_TIMEOUT_ERR_INT_EN | \
    877				    B_AX_CDR_DMA_TIMEOUT_ERR_INT_EN | \
    878				    B_AX_HDT_ADDR_INFO_LEN_ERR_INT_EN | \
    879				    B_AX_CDT_ADDR_INFO_LEN_ERR_INT_EN | \
    880				    B_AX_HDT_HCI_TIMEOUT_ERR_INT_EN | \
    881				    B_AX_HDT_PTR_TIMEOUT_ERR_INT_EN | \
    882				    B_AX_CDT_HCI_TIMEOUT_ERR_INT_EN | \
    883				    B_AX_CDT_PTR_TIMEOUT_ERR_INT_EN | \
    884				    B_AX_REUSE_PKT_CNT_ERR_INT_EN | \
    885				    B_AX_REUSE_SIZE_ZERO_ERR_INT_EN | \
    886				    B_AX_STF_CMD_OVERFLOW_ERR_INT_EN | \
    887				    B_AX_STF_CMD_UNDERFLOW_ERR_INT_EN | \
    888				    B_AX_STF_WRFF_OVERFLOW_ERR_INT_EN | \
    889				    B_AX_STF_WRFF_UNDERFLOW_ERR_INT_EN | \
    890				    B_AX_STF_OQT_OVERFLOW_ERR_INT_EN | \
    891				    B_AX_STF_OQT_UNDERFLOW_ERR_INT_EN | \
    892				    B_AX_REUSE_EN_ERR_INT_EN | \
    893				    B_AX_REUSE_SIZE_ERR_INT_EN)
    894#define B_AX_OTHER_DISP_IMR_SET_V1 (B_AX_CDR_RX_TIMEOUT_ERR_INT_EN | \
    895				    B_AX_CDR_DMA_TIMEOUT_ERR_INT_EN | \
    896				    B_AX_HDT_HCI_TIMEOUT_ERR_INT_EN | \
    897				    B_AX_HDT_PTR_TIMEOUT_ERR_INT_EN | \
    898				    B_AX_CDT_HCI_TIMEOUT_ERR_INT_EN | \
    899				    B_AX_CDT_PTR_TIMEOUT_ERR_INT_EN | \
    900				    B_AX_STF_OQT_OVERFLOW_ERR_INT_EN | \
    901				    B_AX_STF_OQT_UNDERFLOW_ERR_INT_EN)
    902
    903#define R_AX_HCI_FC_CTRL 0x8A00
    904#define B_AX_HCI_FC_CH12_FULL_COND_MASK GENMASK(11, 10)
    905#define B_AX_HCI_FC_WP_CH811_FULL_COND_MASK GENMASK(9, 8)
    906#define B_AX_HCI_FC_WP_CH07_FULL_COND_MASK GENMASK(7, 6)
    907#define B_AX_HCI_FC_WD_FULL_COND_MASK GENMASK(5, 4)
    908#define B_AX_HCI_FC_CH12_EN BIT(3)
    909#define B_AX_HCI_FC_MODE_MASK GENMASK(2, 1)
    910#define B_AX_HCI_FC_EN BIT(0)
    911
    912#define R_AX_CH_PAGE_CTRL 0x8A04
    913#define B_AX_PREC_PAGE_CH12_MASK GENMASK(24, 16)
    914#define B_AX_PREC_PAGE_CH011_MASK GENMASK(8, 0)
    915
    916#define B_AX_MAX_PG_MASK GENMASK(28, 16)
    917#define B_AX_MIN_PG_MASK GENMASK(12, 0)
    918#define B_AX_GRP BIT(31)
    919#define R_AX_ACH0_PAGE_CTRL 0x8A10
    920#define R_AX_ACH1_PAGE_CTRL 0x8A14
    921#define R_AX_ACH2_PAGE_CTRL 0x8A18
    922#define R_AX_ACH3_PAGE_CTRL 0x8A1C
    923#define R_AX_ACH4_PAGE_CTRL 0x8A20
    924#define R_AX_ACH5_PAGE_CTRL 0x8A24
    925#define R_AX_ACH6_PAGE_CTRL 0x8A28
    926#define R_AX_ACH7_PAGE_CTRL 0x8A2C
    927#define R_AX_CH8_PAGE_CTRL 0x8A30
    928#define R_AX_CH9_PAGE_CTRL 0x8A34
    929#define R_AX_CH10_PAGE_CTRL 0x8A38
    930#define R_AX_CH11_PAGE_CTRL 0x8A3C
    931
    932#define B_AX_AVAL_PG_MASK GENMASK(27, 16)
    933#define B_AX_USE_PG_MASK GENMASK(12, 0)
    934#define R_AX_ACH0_PAGE_INFO 0x8A50
    935#define R_AX_ACH1_PAGE_INFO 0x8A54
    936#define R_AX_ACH2_PAGE_INFO 0x8A58
    937#define R_AX_ACH3_PAGE_INFO 0x8A5C
    938#define R_AX_ACH4_PAGE_INFO 0x8A60
    939#define R_AX_ACH5_PAGE_INFO 0x8A64
    940#define R_AX_ACH6_PAGE_INFO 0x8A68
    941#define R_AX_ACH7_PAGE_INFO 0x8A6C
    942#define R_AX_CH8_PAGE_INFO 0x8A70
    943#define R_AX_CH9_PAGE_INFO 0x8A74
    944#define R_AX_CH10_PAGE_INFO 0x8A78
    945#define R_AX_CH11_PAGE_INFO 0x8A7C
    946#define R_AX_CH12_PAGE_INFO 0x8A80
    947
    948#define R_AX_PUB_PAGE_INFO3 0x8A8C
    949#define B_AX_G1_AVAL_PG_MASK GENMASK(28, 16)
    950#define B_AX_G0_AVAL_PG_MASK GENMASK(12, 0)
    951
    952#define R_AX_PUB_PAGE_CTRL1 0x8A90
    953#define B_AX_PUBPG_G1_MASK GENMASK(28, 16)
    954#define B_AX_PUBPG_G0_MASK GENMASK(12, 0)
    955
    956#define R_AX_PUB_PAGE_CTRL2 0x8A94
    957#define B_AX_PUBPG_ALL_MASK GENMASK(12, 0)
    958
    959#define R_AX_PUB_PAGE_INFO1 0x8A98
    960#define B_AX_G1_USE_PG_MASK GENMASK(28, 16)
    961#define B_AX_G0_USE_PG_MASK GENMASK(12, 0)
    962
    963#define R_AX_PUB_PAGE_INFO2 0x8A9C
    964#define B_AX_PUB_AVAL_PG_MASK GENMASK(12, 0)
    965
    966#define R_AX_WP_PAGE_CTRL1 0x8AA0
    967#define B_AX_PREC_PAGE_WP_CH811_MASK GENMASK(24, 16)
    968#define B_AX_PREC_PAGE_WP_CH07_MASK GENMASK(8, 0)
    969
    970#define R_AX_WP_PAGE_CTRL2 0x8AA4
    971#define B_AX_WP_THRD_MASK GENMASK(12, 0)
    972
    973#define R_AX_WP_PAGE_INFO1 0x8AA8
    974#define B_AX_WP_AVAL_PG_MASK GENMASK(28, 16)
    975
    976#define R_AX_WDE_PKTBUF_CFG 0x8C08
    977#define B_AX_WDE_START_BOUND_MASK GENMASK(13, 8)
    978#define B_AX_WDE_PAGE_SEL_MASK GENMASK(1, 0)
    979#define B_AX_WDE_FREE_PAGE_NUM_MASK GENMASK(28, 16)
    980
    981#define R_AX_WDE_ERRFLAG_MSG 0x8C30
    982#define B_AX_WDE_ERR_FLAG_MSG_MASK GENMASK(31, 0)
    983
    984#define R_AX_WDE_ERR_FLAG_CFG 0x8C34
    985
    986#define R_AX_WDE_ERR_IMR 0x8C38
    987#define B_AX_WDE_DATCHN_RRDY_ERR_INT_EN BIT(27)
    988#define B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN BIT(26)
    989#define B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN BIT(25)
    990#define B_AX_WDE_DATCHN_ARBT_ERR_INT_EN BIT(24)
    991#define B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN BIT(19)
    992#define B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN BIT(18)
    993#define B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN BIT(17)
    994#define B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(16)
    995#define B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(15)
    996#define B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN BIT(14)
    997#define B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN BIT(13)
    998#define B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN BIT(12)
    999#define B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN BIT(7)
   1000#define B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN BIT(6)
   1001#define B_AX_WDE_GETNPG_STRPG_ERR_INT_EN BIT(5)
   1002#define B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN BIT(4)
   1003#define B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN BIT(3)
   1004#define B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN BIT(2)
   1005#define B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN BIT(1)
   1006#define B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN BIT(0)
   1007#define B_AX_WDE_IMR_CLR (B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN | \
   1008			  B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN | \
   1009			  B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \
   1010			  B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN | \
   1011			  B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \
   1012			  B_AX_WDE_GETNPG_STRPG_ERR_INT_EN | \
   1013			  B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN | \
   1014			  B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN | \
   1015			  B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN | \
   1016			  B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN | \
   1017			  B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN | \
   1018			  B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
   1019			  B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
   1020			  B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN | \
   1021			  B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN | \
   1022			  B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN | \
   1023			  B_AX_WDE_DATCHN_ARBT_ERR_INT_EN | \
   1024			  B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN | \
   1025			  B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN)
   1026#define B_AX_WDE_IMR_SET (B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN | \
   1027			  B_AX_WDE_BUFREQ_SIZE0_INT_EN | \
   1028			  B_AX_WDE_BUFREQ_SIZELMT_INT_EN | \
   1029			  B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN_V1 | \
   1030			  B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 | \
   1031			  B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN_V1 | \
   1032			  B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 | \
   1033			  B_AX_WDE_GETNPG_STRPG_ERR_INT_EN_V1 | \
   1034			  B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN_V1 | \
   1035			  B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN_V1 | \
   1036			  B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN | \
   1037			  B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN | \
   1038			  B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN | \
   1039			  B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
   1040			  B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
   1041			  B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN | \
   1042			  B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN | \
   1043			  B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN | \
   1044			  B_AX_WDE_DATCHN_ARBT_ERR_INT_EN | \
   1045			  B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN | \
   1046			  B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN | \
   1047			  B_AX_WDE_DATCHN_RRDY_ERR_INT_EN | \
   1048			  B_AX_WDE_DATCHN_ADRERR_ERR_INT_EN | \
   1049			  B_AX_WDE_DATCHN_CAMREQ_ERR_INT_EN)
   1050
   1051#define B_AX_WDE_DATCHN_CAMREQ_ERR_INT_EN BIT(29)
   1052#define B_AX_WDE_DATCHN_ADRERR_ERR_INT_EN BIT(28)
   1053#define B_AX_WDE_DATCHN_RRDY_ERR_INT_EN BIT(27)
   1054#define B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN BIT(26)
   1055#define B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN BIT(25)
   1056#define B_AX_WDE_DATCHN_ARBT_ERR_INT_EN BIT(24)
   1057#define B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN BIT(19)
   1058#define B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN BIT(18)
   1059#define B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN BIT(17)
   1060#define B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(16)
   1061#define B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(15)
   1062#define B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN BIT(14)
   1063#define B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN_V1 BIT(9)
   1064#define B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN_V1 BIT(8)
   1065#define B_AX_WDE_GETNPG_STRPG_ERR_INT_EN_V1 BIT(7)
   1066#define B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 BIT(6)
   1067#define B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN_V1 BIT(5)
   1068#define B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 BIT(4)
   1069#define B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN_V1 BIT(3)
   1070#define B_AX_WDE_BUFREQ_SIZELMT_INT_EN BIT(2)
   1071#define B_AX_WDE_BUFREQ_SIZE0_INT_EN BIT(1)
   1072#define B_AX_WDE_IMR_CLR_V1 (B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN | \
   1073			     B_AX_WDE_BUFREQ_SIZE0_INT_EN | \
   1074			     B_AX_WDE_BUFREQ_SIZELMT_INT_EN | \
   1075			     B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN_V1 | \
   1076			     B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 | \
   1077			     B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN_V1 | \
   1078			     B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 | \
   1079			     B_AX_WDE_GETNPG_STRPG_ERR_INT_EN_V1 | \
   1080			     B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN_V1 | \
   1081			     B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN_V1 | \
   1082			     B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN | \
   1083			     B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN | \
   1084			     B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN | \
   1085			     B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
   1086			     B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
   1087			     B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN | \
   1088			     B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN | \
   1089			     B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN | \
   1090			     B_AX_WDE_DATCHN_ARBT_ERR_INT_EN | \
   1091			     B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN | \
   1092			     B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN | \
   1093			     B_AX_WDE_DATCHN_RRDY_ERR_INT_EN | \
   1094			     B_AX_WDE_DATCHN_ADRERR_ERR_INT_EN | \
   1095			     B_AX_WDE_DATCHN_CAMREQ_ERR_INT_EN)
   1096#define B_AX_WDE_IMR_SET_V1 (B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN | \
   1097			     B_AX_WDE_BUFREQ_SIZE0_INT_EN | \
   1098			     B_AX_WDE_BUFREQ_SIZELMT_INT_EN | \
   1099			     B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN_V1 | \
   1100			     B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 | \
   1101			     B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN_V1 | \
   1102			     B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 | \
   1103			     B_AX_WDE_GETNPG_STRPG_ERR_INT_EN_V1 | \
   1104			     B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN_V1 | \
   1105			     B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN_V1 | \
   1106			     B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN | \
   1107			     B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN | \
   1108			     B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN | \
   1109			     B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
   1110			     B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
   1111			     B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN | \
   1112			     B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN | \
   1113			     B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN | \
   1114			     B_AX_WDE_DATCHN_ARBT_ERR_INT_EN | \
   1115			     B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN | \
   1116			     B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN | \
   1117			     B_AX_WDE_DATCHN_RRDY_ERR_INT_EN | \
   1118			     B_AX_WDE_DATCHN_ADRERR_ERR_INT_EN | \
   1119			     B_AX_WDE_DATCHN_CAMREQ_ERR_INT_EN)
   1120
   1121#define R_AX_WDE_ERR_ISR 0x8C3C
   1122#define B_AX_WDE_DATCHN_RRDY_ERR BIT(27)
   1123#define B_AX_WDE_DATCHN_FRZTO_ERR BIT(26)
   1124#define B_AX_WDE_DATCHN_NULLPG_ERR BIT(25)
   1125#define B_AX_WDE_DATCHN_ARBT_ERR BIT(24)
   1126#define B_AX_WDE_QUEMGN_FRZTO_ERR BIT(19)
   1127#define B_AX_WDE_NXTPKTLL_AD_ERR BIT(18)
   1128#define B_AX_WDE_PREPKTLLT_AD_ERR BIT(17)
   1129#define B_AX_WDE_ENQ_PKTCNT_NVAL_ERR BIT(16)
   1130#define B_AX_WDE_ENQ_PKTCNT_OVRF_ERR BIT(15)
   1131#define B_AX_WDE_QUE_SRCQUEID_ERR BIT(14)
   1132#define B_AX_WDE_QUE_DSTQUEID_ERR BIT(13)
   1133#define B_AX_WDE_QUE_CMDTYPE_ERR BIT(12)
   1134#define B_AX_WDE_BUFMGN_FRZTO_ERR BIT(7)
   1135#define B_AX_WDE_GETNPG_PGOFST_ERR BIT(6)
   1136#define B_AX_WDE_GETNPG_STRPG_ERR BIT(5)
   1137#define B_AX_WDE_BUFREQ_SRCHTAILPG_ERR BIT(4)
   1138#define B_AX_WDE_BUFRTN_SIZE_ERR BIT(3)
   1139#define B_AX_WDE_BUFRTN_INVLD_PKTID_ERR BIT(2)
   1140#define B_AX_WDE_BUFREQ_UNAVAL_ERR BIT(1)
   1141#define B_AX_WDE_BUFREQ_QTAID_ERR BIT(0)
   1142
   1143#define B_AX_WDE_MAX_SIZE_MASK GENMASK(27, 16)
   1144#define B_AX_WDE_MIN_SIZE_MASK GENMASK(11, 0)
   1145#define R_AX_WDE_QTA0_CFG 0x8C40
   1146#define R_AX_WDE_QTA1_CFG 0x8C44
   1147#define R_AX_WDE_QTA2_CFG 0x8C48
   1148#define R_AX_WDE_QTA3_CFG 0x8C4C
   1149#define R_AX_WDE_QTA4_CFG 0x8C50
   1150
   1151#define B_AX_DLE_PUB_PGNUM GENMASK(12, 0)
   1152#define B_AX_DLE_FREE_HEADPG GENMASK(11, 0)
   1153#define B_AX_DLE_FREE_TAILPG GENMASK(27, 16)
   1154#define B_AX_DLE_USE_PGNUM GENMASK(27, 16)
   1155#define B_AX_DLE_RSV_PGNUM GENMASK(11, 0)
   1156#define B_AX_DLE_QEMPTY_GRP GENMASK(31, 0)
   1157
   1158#define R_AX_WDE_INI_STATUS 0x8D00
   1159#define B_AX_WDE_Q_MGN_INI_RDY BIT(1)
   1160#define B_AX_WDE_BUF_MGN_INI_RDY BIT(0)
   1161#define WDE_MGN_INI_RDY (B_AX_WDE_Q_MGN_INI_RDY | B_AX_WDE_BUF_MGN_INI_RDY)
   1162#define R_AX_WDE_DBG_FUN_INTF_CTL 0x8D10
   1163#define B_AX_WDE_DFI_ACTIVE BIT(31)
   1164#define B_AX_WDE_DFI_TRGSEL_MASK GENMASK(19, 16)
   1165#define B_AX_WDE_DFI_ADDR_MASK GENMASK(15, 0)
   1166#define R_AX_WDE_DBG_FUN_INTF_DATA 0x8D14
   1167#define B_AX_WDE_DFI_DATA_MASK GENMASK(31, 0)
   1168
   1169#define R_AX_PLE_PKTBUF_CFG 0x9008
   1170#define B_AX_PLE_START_BOUND_MASK GENMASK(13, 8)
   1171#define B_AX_PLE_PAGE_SEL_MASK GENMASK(1, 0)
   1172#define B_AX_PLE_FREE_PAGE_NUM_MASK GENMASK(28, 16)
   1173#define R_AX_PLE_ERR_FLAG_CFG 0x9034
   1174
   1175#define R_AX_PLE_ERR_IMR 0x9038
   1176#define B_AX_PLE_DATCHN_RRDY_ERR_INT_EN BIT(27)
   1177#define B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN BIT(26)
   1178#define B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN BIT(25)
   1179#define B_AX_PLE_DATCHN_ARBT_ERR_INT_EN BIT(24)
   1180#define B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN BIT(19)
   1181#define B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN BIT(18)
   1182#define B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN BIT(17)
   1183#define B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(16)
   1184#define B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(15)
   1185#define B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN BIT(14)
   1186#define B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN BIT(13)
   1187#define B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN BIT(12)
   1188#define B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN BIT(7)
   1189#define B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN BIT(6)
   1190#define B_AX_PLE_GETNPG_STRPG_ERR_INT_EN BIT(5)
   1191#define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN BIT(4)
   1192#define B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN BIT(3)
   1193#define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN BIT(2)
   1194#define B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN BIT(1)
   1195#define B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN BIT(0)
   1196#define B_AX_PLE_IMR_CLR (B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN | \
   1197			  B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN | \
   1198			  B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \
   1199			  B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN | \
   1200			  B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \
   1201			  B_AX_PLE_GETNPG_STRPG_ERR_INT_EN | \
   1202			  B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN | \
   1203			  B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN | \
   1204			  B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN | \
   1205			  B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN | \
   1206			  B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN | \
   1207			  B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
   1208			  B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
   1209			  B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN | \
   1210			  B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN | \
   1211			  B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN | \
   1212			  B_AX_PLE_DATCHN_ARBT_ERR_INT_EN | \
   1213			  B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN | \
   1214			  B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN)
   1215#define B_AX_PLE_IMR_SET (B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN | \
   1216			  B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN | \
   1217			  B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \
   1218			  B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN | \
   1219			  B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \
   1220			  B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN | \
   1221			  B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN | \
   1222			  B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN | \
   1223			  B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN | \
   1224			  B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN | \
   1225			  B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
   1226			  B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
   1227			  B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN | \
   1228			  B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN | \
   1229			  B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN | \
   1230			  B_AX_PLE_DATCHN_ARBT_ERR_INT_EN | \
   1231			  B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN | \
   1232			  B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN)
   1233
   1234#define B_AX_PLE_DATCHN_CAMREQ_ERR_INT_EN BIT(29)
   1235#define B_AX_PLE_DATCHN_ADRERR_ERR_INT_EN BIT(28)
   1236#define B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN_V1 BIT(9)
   1237#define B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN_V1 BIT(8)
   1238#define B_AX_PLE_GETNPG_STRPG_ERR_INT_EN_V1 BIT(7)
   1239#define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 BIT(6)
   1240#define B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN_V1 BIT(5)
   1241#define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 BIT(4)
   1242#define B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN_V1 BIT(3)
   1243#define B_AX_PLE_BUFREQ_SIZELMT_INT_EN BIT(2)
   1244#define B_AX_PLE_BUFREQ_SIZE0_INT_EN BIT(1)
   1245#define B_AX_PLE_IMR_CLR_V1 (B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN | \
   1246			     B_AX_PLE_BUFREQ_SIZE0_INT_EN | \
   1247			     B_AX_PLE_BUFREQ_SIZELMT_INT_EN | \
   1248			     B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN_V1 | \
   1249			     B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 | \
   1250			     B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN_V1 | \
   1251			     B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 | \
   1252			     B_AX_PLE_GETNPG_STRPG_ERR_INT_EN_V1 | \
   1253			     B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN_V1 | \
   1254			     B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN_V1 | \
   1255			     B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN | \
   1256			     B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN | \
   1257			     B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN | \
   1258			     B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
   1259			     B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
   1260			     B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN | \
   1261			     B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN | \
   1262			     B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN | \
   1263			     B_AX_PLE_DATCHN_ARBT_ERR_INT_EN | \
   1264			     B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN | \
   1265			     B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN | \
   1266			     B_AX_PLE_DATCHN_RRDY_ERR_INT_EN | \
   1267			     B_AX_PLE_DATCHN_ADRERR_ERR_INT_EN | \
   1268			     B_AX_PLE_DATCHN_CAMREQ_ERR_INT_EN)
   1269#define B_AX_PLE_IMR_SET_V1 (B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN | \
   1270			     B_AX_PLE_BUFREQ_SIZE0_INT_EN | \
   1271			     B_AX_PLE_BUFREQ_SIZELMT_INT_EN | \
   1272			     B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN_V1 | \
   1273			     B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 | \
   1274			     B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN_V1 | \
   1275			     B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 | \
   1276			     B_AX_PLE_GETNPG_STRPG_ERR_INT_EN_V1 | \
   1277			     B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN_V1 | \
   1278			     B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN_V1 | \
   1279			     B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN | \
   1280			     B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN | \
   1281			     B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN | \
   1282			     B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \
   1283			     B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \
   1284			     B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN | \
   1285			     B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN | \
   1286			     B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN | \
   1287			     B_AX_PLE_DATCHN_ARBT_ERR_INT_EN | \
   1288			     B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN | \
   1289			     B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN | \
   1290			     B_AX_PLE_DATCHN_RRDY_ERR_INT_EN | \
   1291			     B_AX_PLE_DATCHN_ADRERR_ERR_INT_EN | \
   1292			     B_AX_PLE_DATCHN_CAMREQ_ERR_INT_EN)
   1293
   1294#define R_AX_PLE_ERR_FLAG_ISR 0x903C
   1295#define B_AX_PLE_MAX_SIZE_MASK GENMASK(27, 16)
   1296#define B_AX_PLE_MIN_SIZE_MASK GENMASK(11, 0)
   1297#define R_AX_PLE_QTA0_CFG 0x9040
   1298#define R_AX_PLE_QTA1_CFG 0x9044
   1299#define R_AX_PLE_QTA2_CFG 0x9048
   1300#define R_AX_PLE_QTA3_CFG 0x904C
   1301#define R_AX_PLE_QTA4_CFG 0x9050
   1302#define R_AX_PLE_QTA5_CFG 0x9054
   1303#define R_AX_PLE_QTA6_CFG 0x9058
   1304#define B_AX_PLE_Q6_MAX_SIZE_MASK GENMASK(27, 16)
   1305#define B_AX_PLE_Q6_MIN_SIZE_MASK GENMASK(11, 0)
   1306#define R_AX_PLE_QTA7_CFG 0x905C
   1307#define R_AX_PLE_QTA8_CFG 0x9060
   1308#define R_AX_PLE_QTA9_CFG 0x9064
   1309#define R_AX_PLE_QTA10_CFG 0x9068
   1310#define R_AX_PLE_QTA11_CFG 0x906C
   1311
   1312#define R_AX_PLE_INI_STATUS 0x9100
   1313#define B_AX_PLE_Q_MGN_INI_RDY BIT(1)
   1314#define B_AX_PLE_BUF_MGN_INI_RDY BIT(0)
   1315#define PLE_MGN_INI_RDY (B_AX_PLE_Q_MGN_INI_RDY | B_AX_PLE_BUF_MGN_INI_RDY)
   1316#define R_AX_PLE_DBG_FUN_INTF_CTL 0x9110
   1317#define B_AX_PLE_DFI_ACTIVE BIT(31)
   1318#define B_AX_PLE_DFI_TRGSEL_MASK GENMASK(19, 16)
   1319#define B_AX_PLE_DFI_ADDR_MASK GENMASK(15, 0)
   1320#define R_AX_PLE_DBG_FUN_INTF_DATA 0x9114
   1321#define B_AX_PLE_DFI_DATA_MASK GENMASK(31, 0)
   1322
   1323#define R_AX_WDRLS_CFG 0x9408
   1324#define B_AX_RLSRPT_BUFREQ_TO_MASK GENMASK(15, 8)
   1325#define B_AX_WDRLS_MODE_MASK GENMASK(1, 0)
   1326
   1327#define R_AX_RLSRPT0_CFG0 0x9410
   1328#define B_AX_RLSRPT0_FLTR_MAP_MASK GENMASK(27, 24)
   1329#define B_AX_RLSRPT0_PKTTYPE_MASK GENMASK(19, 16)
   1330#define B_AX_RLSRPT0_PID_MASK GENMASK(10, 8)
   1331#define B_AX_RLSRPT0_QID_MASK GENMASK(5, 0)
   1332
   1333#define R_AX_RLSRPT0_CFG1 0x9414
   1334#define B_AX_RLSRPT0_TO_MASK GENMASK(23, 16)
   1335#define B_AX_RLSRPT0_AGGNUM_MASK GENMASK(7, 0)
   1336
   1337#define R_AX_WDRLS_ERR_IMR 0x9430
   1338#define B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN BIT(13)
   1339#define B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN BIT(12)
   1340#define B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN BIT(9)
   1341#define B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN BIT(8)
   1342#define B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN BIT(5)
   1343#define B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN BIT(4)
   1344#define B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN BIT(2)
   1345#define B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN BIT(1)
   1346#define B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN BIT(0)
   1347#define B_AX_WDRLS_IMR_EN_CLR (B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN | \
   1348			       B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN | \
   1349			       B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN | \
   1350			       B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN | \
   1351			       B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN | \
   1352			       B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN | \
   1353			       B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN | \
   1354			       B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN | \
   1355			       B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN)
   1356#define B_AX_WDRLS_IMR_SET (B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN | \
   1357			    B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN | \
   1358			    B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN | \
   1359			    B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN | \
   1360			    B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN | \
   1361			    B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN | \
   1362			    B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN | \
   1363			    B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN)
   1364#define B_AX_WDRLS_IMR_SET_V1 (B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN | \
   1365			      B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN | \
   1366			      B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN | \
   1367			      B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN | \
   1368			      B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN | \
   1369			      B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN | \
   1370			      B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN | \
   1371			      B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN | \
   1372			      B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN)
   1373
   1374#define R_AX_WDRLS_ERR_ISR 0x9434
   1375
   1376#define R_AX_BBRPT_COM_ERR_IMR 0x9608
   1377#define B_AX_BBRPT_COM_HANG_EN BIT(1)
   1378#define B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN BIT(0)
   1379
   1380#define R_AX_BBRPT_COM_ERR_IMR_ISR 0x960C
   1381#define B_AX_BBRPT_COM_NULL_PLPKTID_ERR BIT(16)
   1382#define B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN BIT(0)
   1383
   1384#define R_AX_BBRPT_CHINFO_ERR_IMR 0x9628
   1385#define B_AX_BBPRT_CHIF_TO_ERR_INT_EN BIT(7)
   1386#define B_AX_BBPRT_CHIF_NULL_ERR_INT_EN BIT(6)
   1387#define B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN BIT(5)
   1388#define B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN BIT(4)
   1389#define B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN BIT(3)
   1390#define B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN BIT(2)
   1391#define B_AX_BBPRT_CHIF_OVF_ERR_INT_EN BIT(1)
   1392#define B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN BIT(0)
   1393#define R_AX_BBRPT_CHINFO_IMR_SET_V1 (B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN | \
   1394				      B_AX_BBPRT_CHIF_OVF_ERR_INT_EN | \
   1395				      B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN | \
   1396				      B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN | \
   1397				      B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN | \
   1398				      B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN | \
   1399				      B_AX_BBPRT_CHIF_NULL_ERR_INT_EN | \
   1400				      B_AX_BBPRT_CHIF_TO_ERR_INT_EN)
   1401
   1402#define R_AX_BBRPT_CHINFO_ERR_IMR_ISR 0x962C
   1403#define B_AX_BBPRT_CHIF_TO_ERR BIT(23)
   1404#define B_AX_BBPRT_CHIF_NULL_ERR BIT(22)
   1405#define B_AX_BBPRT_CHIF_LEFT2_ERR BIT(21)
   1406#define B_AX_BBPRT_CHIF_LEFT1_ERR BIT(20)
   1407#define B_AX_BBPRT_CHIF_HDRL_ERR BIT(19)
   1408#define B_AX_BBPRT_CHIF_BOVF_ERR BIT(18)
   1409#define B_AX_BBPRT_CHIF_OVF_ERR BIT(17)
   1410#define B_AX_BBPRT_CHIF_BB_TO_ERR BIT(16)
   1411#define B_AX_BBPRT_CHIF_TO_ERR_INT_EN BIT(7)
   1412#define B_AX_BBPRT_CHIF_NULL_ERR_INT_EN BIT(6)
   1413#define B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN BIT(5)
   1414#define B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN BIT(4)
   1415#define B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN BIT(3)
   1416#define B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN BIT(2)
   1417#define B_AX_BBPRT_CHIF_OVF_ERR_INT_EN BIT(1)
   1418#define B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN BIT(0)
   1419#define B_AX_BBRPT_CHINFO_IMR_CLR (B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN | \
   1420				   B_AX_BBPRT_CHIF_OVF_ERR_INT_EN | \
   1421				   B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN | \
   1422				   B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN | \
   1423				   B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN | \
   1424				   B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN | \
   1425				   B_AX_BBPRT_CHIF_NULL_ERR_INT_EN | \
   1426				   B_AX_BBPRT_CHIF_TO_ERR_INT_EN)
   1427
   1428#define R_AX_BBRPT_DFS_ERR_IMR 0x9638
   1429#define B_AX_BBRPT_DFS_TO_ERR_INT_EN BIT(0)
   1430
   1431#define R_AX_BBRPT_DFS_ERR_IMR_ISR 0x963C
   1432#define B_AX_BBRPT_DFS_TO_ERR BIT(16)
   1433#define B_AX_BBRPT_DFS_TO_ERR_INT_EN BIT(0)
   1434
   1435#define R_AX_LA_ERRFLAG 0x966C
   1436#define B_AX_LA_ISR_DATA_LOSS_ERR BIT(16)
   1437#define B_AX_LA_IMR_DATA_LOSS_ERR BIT(0)
   1438
   1439#define R_AX_WD_BUF_REQ 0x9800
   1440#define R_AX_PL_BUF_REQ 0x9820
   1441#define B_AX_WD_BUF_REQ_EXEC BIT(31)
   1442#define B_AX_WD_BUF_REQ_QUOTA_ID_MASK GENMASK(23, 16)
   1443#define B_AX_WD_BUF_REQ_LEN_MASK GENMASK(15, 0)
   1444
   1445#define R_AX_WD_BUF_STATUS 0x9804
   1446#define R_AX_PL_BUF_STATUS 0x9824
   1447#define B_AX_WD_BUF_STAT_DONE BIT(31)
   1448#define B_AX_WD_BUF_STAT_PKTID_MASK GENMASK(11, 0)
   1449
   1450#define R_AX_WD_CPUQ_OP_0 0x9810
   1451#define R_AX_PL_CPUQ_OP_0 0x9830
   1452#define B_AX_WD_CPUQ_OP_EXEC BIT(31)
   1453#define B_AX_CPUQ_OP_CMD_TYPE_MASK GENMASK(27, 24)
   1454#define B_AX_CPUQ_OP_MACID_MASK GENMASK(23, 16)
   1455#define B_AX_CPUQ_OP_PKTNUM_MASK GENMASK(7, 0)
   1456
   1457#define R_AX_WD_CPUQ_OP_1 0x9814
   1458#define R_AX_PL_CPUQ_OP_1 0x9834
   1459#define B_AX_CPUQ_OP_SRC_PID_MASK GENMASK(24, 22)
   1460#define B_AX_CPUQ_OP_SRC_QID_MASK GENMASK(21, 16)
   1461#define B_AX_CPUQ_OP_DST_PID_MASK GENMASK(8, 6)
   1462#define B_AX_CPUQ_OP_DST_QID_MASK GENMASK(5, 0)
   1463
   1464#define R_AX_WD_CPUQ_OP_2 0x9818
   1465#define R_AX_PL_CPUQ_OP_2 0x9838
   1466#define B_AX_WD_CPUQ_OP_STRT_PKTID_MASK GENMASK(27, 16)
   1467#define B_AX_WD_CPUQ_OP_END_PKTID_MASK GENMASK(11, 0)
   1468
   1469#define R_AX_WD_CPUQ_OP_STATUS 0x981C
   1470#define R_AX_PL_CPUQ_OP_STATUS 0x983C
   1471#define B_AX_WD_CPUQ_OP_STAT_DONE BIT(31)
   1472#define B_AX_WD_CPUQ_OP_PKTID_MASK GENMASK(11, 0)
   1473
   1474#define R_AX_CPUIO_ERR_IMR 0x9840
   1475#define B_AX_PLEQUE_OP_ERR_INT_EN BIT(12)
   1476#define B_AX_PLEBUF_OP_ERR_INT_EN BIT(8)
   1477#define B_AX_WDEQUE_OP_ERR_INT_EN BIT(4)
   1478#define B_AX_WDEBUF_OP_ERR_INT_EN BIT(0)
   1479#define B_AX_CPUIO_IMR_CLR (B_AX_WDEBUF_OP_ERR_INT_EN | \
   1480			    B_AX_WDEQUE_OP_ERR_INT_EN | \
   1481			    B_AX_PLEBUF_OP_ERR_INT_EN | \
   1482			    B_AX_PLEQUE_OP_ERR_INT_EN)
   1483#define B_AX_CPUIO_IMR_SET (B_AX_WDEBUF_OP_ERR_INT_EN | \
   1484			    B_AX_WDEQUE_OP_ERR_INT_EN | \
   1485			    B_AX_PLEBUF_OP_ERR_INT_EN | \
   1486			    B_AX_PLEQUE_OP_ERR_INT_EN)
   1487
   1488#define R_AX_CPUIO_ERR_ISR 0x9844
   1489
   1490#define R_AX_SEC_ERR_IMR_ISR 0x991C
   1491
   1492#define R_AX_PKTIN_SETTING 0x9A00
   1493#define B_AX_WD_ADDR_INFO_LENGTH BIT(1)
   1494
   1495#define R_AX_PKTIN_ERR_IMR 0x9A20
   1496#define B_AX_PKTIN_GETPKTID_ERR_INT_EN BIT(0)
   1497
   1498#define R_AX_PKTIN_ERR_ISR 0x9A24
   1499
   1500#define R_AX_MPDU_TX_ERR_ISR 0x9BF0
   1501#define R_AX_MPDU_TX_ERR_IMR 0x9BF4
   1502#define B_AX_TX_KSRCH_ERR_EN BIT(9)
   1503#define B_AX_TX_NW_TYPE_ERR_EN BIT(8)
   1504#define B_AX_TX_LLC_PRE_ERR_EN BIT(7)
   1505#define B_AX_TX_ETH_TYPE_ERR_EN BIT(6)
   1506#define B_AX_TX_HDR3_SIZE_ERR_INT_EN BIT(5)
   1507#define B_AX_TX_OFFSET_ERR_INT_EN BIT(4)
   1508#define B_AX_TX_MPDU_SIZE_ZERO_INT_EN BIT(3)
   1509#define B_AX_TX_NXT_ERRPKTID_INT_EN BIT(2)
   1510#define B_AX_TX_GET_ERRPKTID_INT_EN BIT(1)
   1511#define B_AX_MPDU_TX_IMR_SET_V1 (B_AX_TX_GET_ERRPKTID_INT_EN | \
   1512				 B_AX_TX_NXT_ERRPKTID_INT_EN | \
   1513				 B_AX_TX_MPDU_SIZE_ZERO_INT_EN | \
   1514				 B_AX_TX_HDR3_SIZE_ERR_INT_EN | \
   1515				 B_AX_TX_ETH_TYPE_ERR_EN | \
   1516				 B_AX_TX_NW_TYPE_ERR_EN | \
   1517				 B_AX_TX_KSRCH_ERR_EN)
   1518
   1519#define R_AX_MPDU_PROC 0x9C00
   1520#define B_AX_A_ICV_ERR BIT(1)
   1521#define B_AX_APPEND_FCS BIT(0)
   1522
   1523#define R_AX_ACTION_FWD0 0x9C04
   1524#define TRXCFG_MPDU_PROC_ACT_FRWD 0x02A95A95
   1525
   1526#define R_AX_TF_FWD 0x9C14
   1527#define TRXCFG_MPDU_PROC_TF_FRWD 0x0000AA55
   1528
   1529#define R_AX_HW_RPT_FWD 0x9C18
   1530#define B_AX_FWD_PPDU_STAT_MASK GENMASK(1, 0)
   1531#define RTW89_PRPT_DEST_HOST 1
   1532#define RTW89_PRPT_DEST_WLCPU 2
   1533
   1534#define R_AX_CUT_AMSDU_CTRL 0x9C40
   1535#define TRXCFG_MPDU_PROC_CUT_CTRL	0x010E05F0
   1536
   1537#define R_AX_MPDU_RX_ERR_ISR 0x9CF0
   1538#define R_AX_MPDU_RX_ERR_IMR 0x9CF4
   1539#define B_AX_RPT_ERR_INT_EN BIT(3)
   1540#define B_AX_MHDRLEN_ERR_INT_EN BIT(1)
   1541#define B_AX_GETPKTID_ERR_INT_EN BIT(0)
   1542#define B_AX_MPDU_RX_IMR_SET_V1 B_AX_RPT_ERR_INT_EN
   1543
   1544#define R_AX_SEC_ENG_CTRL 0x9D00
   1545#define B_AX_TX_PARTIAL_MODE BIT(11)
   1546#define B_AX_CLK_EN_CGCMP BIT(10)
   1547#define B_AX_CLK_EN_WAPI BIT(9)
   1548#define B_AX_CLK_EN_WEP_TKIP BIT(8)
   1549#define B_AX_BMC_MGNT_DEC BIT(5)
   1550#define B_AX_UC_MGNT_DEC BIT(4)
   1551#define B_AX_MC_DEC BIT(3)
   1552#define B_AX_BC_DEC BIT(2)
   1553#define B_AX_SEC_RX_DEC BIT(1)
   1554#define B_AX_SEC_TX_ENC BIT(0)
   1555
   1556#define R_AX_SEC_MPDU_PROC 0x9D04
   1557#define B_AX_APPEND_ICV BIT(1)
   1558#define B_AX_APPEND_MIC BIT(0)
   1559
   1560#define R_AX_SEC_CAM_ACCESS 0x9D10
   1561#define R_AX_SEC_CAM_RDATA 0x9D14
   1562#define R_AX_SEC_CAM_WDATA 0x9D18
   1563
   1564#define R_AX_SEC_DEBUG 0x9D1C
   1565#define B_AX_IMR_ERROR BIT(3)
   1566
   1567#define R_AX_SEC_DEBUG1 0x9D1C
   1568#define B_AX_TX_TIMEOUT_SEL_MASK GENMASK(31, 30)
   1569#define AX_TX_TO_VAL  0x2
   1570
   1571#define R_AX_SEC_TX_DEBUG 0x9D20
   1572#define R_AX_SEC_RX_DEBUG 0x9D24
   1573#define R_AX_SEC_TRX_PKT_CNT 0x9D28
   1574#define R_AX_SEC_TRX_BLK_CNT 0x9D2C
   1575
   1576#define R_AX_SEC_ERROR_FLAG_IMR 0x9D2C
   1577#define B_AX_RX_HANG_IMR BIT(1)
   1578#define B_AX_TX_HANG_IMR BIT(0)
   1579
   1580#define R_AX_SS_CTRL 0x9E10
   1581#define B_AX_SS_INIT_DONE_1 BIT(31)
   1582#define B_AX_SS_WARM_INIT_FLG BIT(29)
   1583#define B_AX_SS_NONEMPTY_SS2FINFO_EN BIT(28)
   1584#define B_AX_SS_EN BIT(0)
   1585
   1586#define R_AX_SS2FINFO_PATH 0x9E50
   1587#define B_AX_SS_UL_REL BIT(31)
   1588#define B_AX_SS_REL_QUEUE_MASK GENMASK(29, 24)
   1589#define B_AX_SS_REL_PORT_MASK GENMASK(18, 16)
   1590#define B_AX_SS_DEST_QUEUE_MASK GENMASK(13, 8)
   1591#define SS2F_PATH_WLCPU 0x0A
   1592#define B_AX_SS_DEST_PORT_MASK GENMASK(2, 0)
   1593
   1594#define R_AX_SS_MACID_PAUSE_0 0x9EB0
   1595#define B_AX_SS_MACID31_0_PAUSE_SH 0
   1596#define B_AX_SS_MACID31_0_PAUSE_MASK GENMASK(31, 0)
   1597
   1598#define R_AX_SS_MACID_PAUSE_1 0x9EB4
   1599#define B_AX_SS_MACID63_32_PAUSE_SH 0
   1600#define B_AX_SS_MACID63_32_PAUSE_MASK GENMASK(31, 0)
   1601
   1602#define R_AX_SS_MACID_PAUSE_2 0x9EB8
   1603#define B_AX_SS_MACID95_64_PAUSE_SH 0
   1604#define B_AX_SS_MACID95_64_PAUSE_MASK GENMASK(31, 0)
   1605
   1606#define R_AX_SS_MACID_PAUSE_3 0x9EBC
   1607#define B_AX_SS_MACID127_96_PAUSE_SH 0
   1608#define B_AX_SS_MACID127_96_PAUSE_MASK GENMASK(31, 0)
   1609
   1610#define R_AX_STA_SCHEDULER_ERR_IMR 0x9EF0
   1611#define B_AX_PLE_B_PKTID_ERR_INT_EN BIT(2)
   1612#define B_AX_RPT_HANG_TIMEOUT_INT_EN BIT(1)
   1613#define B_AX_SEARCH_HANG_TIMEOUT_INT_EN BIT(0)
   1614#define B_AX_STA_SCHEDULER_IMR_SET (B_AX_SEARCH_HANG_TIMEOUT_INT_EN | \
   1615				    B_AX_RPT_HANG_TIMEOUT_INT_EN | \
   1616				    B_AX_PLE_B_PKTID_ERR_INT_EN)
   1617
   1618#define R_AX_STA_SCHEDULER_ERR_ISR 0x9EF4
   1619
   1620#define R_AX_TXPKTCTL_ERR_IMR_ISR 0x9F1C
   1621#define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR BIT(25)
   1622#define B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR BIT(24)
   1623#define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR BIT(19)
   1624#define B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR BIT(18)
   1625#define B_AX_TXPKTCTL_USRCTL_NOINIT_ERR BIT(17)
   1626#define B_AX_TXPKTCTL_USRCTL_REINIT_ERR BIT(16)
   1627#define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN BIT(9)
   1628#define B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN BIT(8)
   1629#define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN BIT(3)
   1630#define B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN BIT(2)
   1631#define B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN BIT(1)
   1632#define B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN BIT(0)
   1633#define B_AX_TXPKTCTL_IMR_B0_CLR (B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN | \
   1634				  B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN | \
   1635				  B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN | \
   1636				  B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN | \
   1637				  B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN | \
   1638				  B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN)
   1639#define B_AX_TXPKTCTL_IMR_B1_CLR (B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN | \
   1640				  B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN | \
   1641				  B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN | \
   1642				  B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN | \
   1643				  B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN | \
   1644				  B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN)
   1645#define B_AX_TXPKTCTL_IMR_B0_SET (B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN | \
   1646				  B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN)
   1647#define B_AX_TXPKTCTL_IMR_B1_SET (B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN | \
   1648				  B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN | \
   1649				  B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN | \
   1650				  B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN)
   1651
   1652#define R_AX_TXPKTCTL_ERR_IMR_ISR_B1 0x9F2C
   1653#define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN BIT(9)
   1654#define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN BIT(3)
   1655#define B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN BIT(2)
   1656#define B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN BIT(1)
   1657
   1658#define R_AX_DBG_FUN_INTF_CTL 0x9F30
   1659#define B_AX_DFI_ACTIVE BIT(31)
   1660#define B_AX_DFI_TRGSEL_MASK GENMASK(19, 16)
   1661#define B_AX_DFI_ADDR_MASK GENMASK(15, 0)
   1662#define R_AX_DBG_FUN_INTF_DATA 0x9F34
   1663#define B_AX_DFI_DATA_MASK GENMASK(31, 0)
   1664
   1665#define R_AX_TXPKTCTL_B0_PRELD_CFG0 0x9F48
   1666#define B_AX_B0_PRELD_FEN BIT(31)
   1667#define B_AX_B0_PRELD_USEMAXSZ_MASK GENMASK(25, 16)
   1668#define PRELD_B0_ENT_NUM 10
   1669#define PRELD_AMSDU_SIZE 52
   1670#define B_AX_B0_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8)
   1671#define B_AX_B0_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
   1672
   1673#define R_AX_TXPKTCTL_B0_PRELD_CFG1 0x9F4C
   1674#define B_AX_B0_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8)
   1675#define PRELD_NEXT_WND 1
   1676#define B_AX_B0_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)
   1677
   1678#define R_AX_TXPKTCTL_B0_ERRFLAG_IMR 0x9F78
   1679#define B_AX_B0_IMR_ERR_PRELD_ENTNUMCFG BIT(21)
   1680#define B_AX_B0_IMR_ERR_PRELD_RLSPKTSZERR BIT(20)
   1681#define B_AX_B0_IMR_ERR_MPDUIF_DATAERR BIT(18)
   1682#define B_AX_B0_IMR_ERR_MPDUINFO_RECFG BIT(16)
   1683#define B_AX_B0_IMR_ERR_CMDPSR_TBLSZ BIT(11)
   1684#define B_AX_B0_IMR_ERR_CMDPSR_FRZTO BIT(10)
   1685#define B_AX_B0_IMR_ERR_CMDPSR_CMDTYPE BIT(9)
   1686#define B_AX_B0_IMR_ERR_CMDPSR_1STCMDERR BIT(8)
   1687#define B_AX_B0_IMR_ERR_USRCTL_RLSBMPLEN BIT(3)
   1688#define B_AX_B0_IMR_ERR_USRCTL_RDNRLSCMD BIT(2)
   1689#define B_AX_B0_IMR_ERR_USRCTL_NOINIT BIT(1)
   1690#define B_AX_B0_IMR_ERR_USRCTL_REINIT BIT(0)
   1691#define B_AX_TXPKTCTL_IMR_B0_CLR_V1 (B_AX_B0_IMR_ERR_USRCTL_REINIT | \
   1692				     B_AX_B0_IMR_ERR_USRCTL_NOINIT | \
   1693				     B_AX_B0_IMR_ERR_USRCTL_RDNRLSCMD | \
   1694				     B_AX_B0_IMR_ERR_USRCTL_RLSBMPLEN | \
   1695				     B_AX_B0_IMR_ERR_CMDPSR_1STCMDERR | \
   1696				     B_AX_B0_IMR_ERR_CMDPSR_CMDTYPE | \
   1697				     B_AX_B0_IMR_ERR_CMDPSR_FRZTO | \
   1698				     B_AX_B0_IMR_ERR_CMDPSR_TBLSZ | \
   1699				     B_AX_B0_IMR_ERR_MPDUINFO_RECFG | \
   1700				     B_AX_B0_IMR_ERR_MPDUIF_DATAERR | \
   1701				     B_AX_B0_IMR_ERR_PRELD_RLSPKTSZERR | \
   1702				     B_AX_B0_IMR_ERR_PRELD_ENTNUMCFG)
   1703#define B_AX_TXPKTCTL_IMR_B0_SET_V1 (B_AX_B0_IMR_ERR_USRCTL_REINIT | \
   1704				     B_AX_B0_IMR_ERR_USRCTL_NOINIT | \
   1705				     B_AX_B0_IMR_ERR_CMDPSR_1STCMDERR | \
   1706				     B_AX_B0_IMR_ERR_CMDPSR_CMDTYPE | \
   1707				     B_AX_B0_IMR_ERR_CMDPSR_FRZTO | \
   1708				     B_AX_B0_IMR_ERR_CMDPSR_TBLSZ | \
   1709				     B_AX_B0_IMR_ERR_MPDUINFO_RECFG | \
   1710				     B_AX_B0_IMR_ERR_MPDUIF_DATAERR | \
   1711				     B_AX_B0_IMR_ERR_PRELD_RLSPKTSZERR | \
   1712				     B_AX_B0_IMR_ERR_PRELD_ENTNUMCFG)
   1713
   1714#define R_AX_TXPKTCTL_B1_PRELD_CFG0 0x9F88
   1715#define B_AX_B1_PRELD_FEN BIT(31)
   1716#define B_AX_B1_PRELD_USEMAXSZ_MASK GENMASK(25, 16)
   1717#define PRELD_B1_ENT_NUM 4
   1718#define B_AX_B1_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8)
   1719#define B_AX_B1_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
   1720
   1721#define R_AX_TXPKTCTL_B1_PRELD_CFG1 0x9F8C
   1722#define B_AX_B1_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8)
   1723#define B_AX_B1_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0)
   1724
   1725#define R_AX_TXPKTCTL_B1_ERRFLAG_IMR 0x9FB8
   1726#define B_AX_B1_IMR_ERR_PRELD_ENTNUMCFG BIT(21)
   1727#define B_AX_B1_IMR_ERR_PRELD_RLSPKTSZERR BIT(20)
   1728#define B_AX_B1_IMR_ERR_MPDUIF_DATAERR BIT(18)
   1729#define B_AX_B1_IMR_ERR_MPDUINFO_RECFG BIT(16)
   1730#define B_AX_B1_IMR_ERR_CMDPSR_TBLSZ BIT(11)
   1731#define B_AX_B1_IMR_ERR_CMDPSR_FRZTO BIT(10)
   1732#define B_AX_B1_IMR_ERR_CMDPSR_CMDTYPE BIT(9)
   1733#define B_AX_B1_IMR_ERR_CMDPSR_1STCMDERR BIT(8)
   1734#define B_AX_B1_IMR_ERR_USRCTL_RLSBMPLEN BIT(3)
   1735#define B_AX_B1_IMR_ERR_USRCTL_RDNRLSCMD BIT(2)
   1736#define B_AX_B1_IMR_ERR_USRCTL_NOINIT BIT(1)
   1737#define B_AX_B1_IMR_ERR_USRCTL_REINIT BIT(0)
   1738#define B_AX_TXPKTCTL_IMR_B1_CLR_V1 (B_AX_B1_IMR_ERR_USRCTL_REINIT | \
   1739				     B_AX_B1_IMR_ERR_USRCTL_NOINIT | \
   1740				     B_AX_B1_IMR_ERR_USRCTL_RDNRLSCMD | \
   1741				     B_AX_B1_IMR_ERR_USRCTL_RLSBMPLEN | \
   1742				     B_AX_B1_IMR_ERR_CMDPSR_1STCMDERR | \
   1743				     B_AX_B1_IMR_ERR_CMDPSR_CMDTYPE | \
   1744				     B_AX_B1_IMR_ERR_CMDPSR_FRZTO | \
   1745				     B_AX_B1_IMR_ERR_CMDPSR_TBLSZ | \
   1746				     B_AX_B1_IMR_ERR_MPDUINFO_RECFG | \
   1747				     B_AX_B1_IMR_ERR_MPDUIF_DATAERR | \
   1748				     B_AX_B1_IMR_ERR_PRELD_RLSPKTSZERR | \
   1749				     B_AX_B1_IMR_ERR_PRELD_ENTNUMCFG)
   1750#define B_AX_TXPKTCTL_IMR_B1_SET_V1 (B_AX_B1_IMR_ERR_USRCTL_REINIT | \
   1751				     B_AX_B1_IMR_ERR_USRCTL_NOINIT | \
   1752				     B_AX_B1_IMR_ERR_CMDPSR_1STCMDERR | \
   1753				     B_AX_B1_IMR_ERR_CMDPSR_CMDTYPE | \
   1754				     B_AX_B1_IMR_ERR_CMDPSR_FRZTO | \
   1755				     B_AX_B1_IMR_ERR_CMDPSR_TBLSZ | \
   1756				     B_AX_B1_IMR_ERR_MPDUINFO_RECFG | \
   1757				     B_AX_B1_IMR_ERR_MPDUIF_DATAERR | \
   1758				     B_AX_B1_IMR_ERR_PRELD_RLSPKTSZERR | \
   1759				     B_AX_B1_IMR_ERR_PRELD_ENTNUMCFG)
   1760
   1761#define R_AX_AFE_CTRL1 0x0024
   1762
   1763#define B_AX_R_SYM_WLCMAC1_P4_PC_EN BIT(4)
   1764#define B_AX_R_SYM_WLCMAC1_P3_PC_EN BIT(3)
   1765#define B_AX_R_SYM_WLCMAC1_P2_PC_EN BIT(2)
   1766#define B_AX_R_SYM_WLCMAC1_P1_PC_EN BIT(1)
   1767#define B_AX_R_SYM_WLCMAC1_PC_EN BIT(0)
   1768
   1769#define R_AX_SYS_ISO_CTRL_EXTEND 0x0080
   1770#define B_AX_CMAC1_FEN BIT(30)
   1771#define B_AX_R_SYM_FEN_WLBBGLB_1 BIT(17)
   1772#define B_AX_R_SYM_FEN_WLBBFUN_1 BIT(16)
   1773#define B_AX_R_SYM_ISO_CMAC12PP BIT(5)
   1774
   1775#define R_AX_CMAC_REG_START 0xC000
   1776
   1777#define R_AX_CMAC_FUNC_EN 0xC000
   1778#define R_AX_CMAC_FUNC_EN_C1 0xE000
   1779#define B_AX_CMAC_CRPRT BIT(31)
   1780#define B_AX_CMAC_EN BIT(30)
   1781#define B_AX_CMAC_TXEN BIT(29)
   1782#define B_AX_CMAC_RXEN BIT(28)
   1783#define B_AX_FORCE_CMACREG_GCKEN BIT(15)
   1784#define B_AX_PHYINTF_EN BIT(5)
   1785#define B_AX_CMAC_DMA_EN BIT(4)
   1786#define B_AX_PTCLTOP_EN BIT(3)
   1787#define B_AX_SCHEDULER_EN BIT(2)
   1788#define B_AX_TMAC_EN BIT(1)
   1789#define B_AX_RMAC_EN BIT(0)
   1790
   1791#define R_AX_CK_EN 0xC004
   1792#define R_AX_CK_EN_C1 0xE004
   1793#define B_AX_CMAC_ALLCKEN GENMASK(31, 0)
   1794#define B_AX_CMAC_CKEN BIT(30)
   1795#define B_AX_PHYINTF_CKEN BIT(5)
   1796#define B_AX_CMAC_DMA_CKEN BIT(4)
   1797#define B_AX_PTCLTOP_CKEN BIT(3)
   1798#define B_AX_SCHEDULER_CKEN BIT(2)
   1799#define B_AX_TMAC_CKEN BIT(1)
   1800#define B_AX_RMAC_CKEN BIT(0)
   1801
   1802#define R_AX_WMAC_RFMOD 0xC010
   1803#define R_AX_WMAC_RFMOD_C1 0xE010
   1804#define B_AX_WMAC_RFMOD_MASK GENMASK(1, 0)
   1805#define AX_WMAC_RFMOD_20M 0
   1806#define AX_WMAC_RFMOD_40M 1
   1807#define AX_WMAC_RFMOD_80M 2
   1808#define AX_WMAC_RFMOD_160M 3
   1809
   1810#define R_AX_GID_POSITION0 0xC070
   1811#define R_AX_GID_POSITION0_C1 0xE070
   1812#define R_AX_GID_POSITION1 0xC074
   1813#define R_AX_GID_POSITION1_C1 0xE074
   1814#define R_AX_GID_POSITION2 0xC078
   1815#define R_AX_GID_POSITION2_C1 0xE078
   1816#define R_AX_GID_POSITION3 0xC07C
   1817#define R_AX_GID_POSITION3_C1 0xE07C
   1818#define R_AX_GID_POSITION_EN0 0xC080
   1819#define R_AX_GID_POSITION_EN0_C1 0xE080
   1820#define R_AX_GID_POSITION_EN1 0xC084
   1821#define R_AX_GID_POSITION_EN1_C1 0xE084
   1822
   1823#define R_AX_TX_SUB_CARRIER_VALUE 0xC088
   1824#define R_AX_TX_SUB_CARRIER_VALUE_C1 0xE088
   1825#define B_AX_TXSC_80M_MASK GENMASK(11, 8)
   1826#define B_AX_TXSC_40M_MASK GENMASK(7, 4)
   1827#define B_AX_TXSC_20M_MASK GENMASK(3, 0)
   1828
   1829#define R_AX_CMAC_ERR_IMR 0xC160
   1830#define R_AX_CMAC_ERR_IMR_C1 0xE160
   1831#define B_AX_WMAC_TX_ERR_IND_EN BIT(7)
   1832#define B_AX_WMAC_RX_ERR_IND_EN BIT(6)
   1833#define B_AX_TXPWR_CTRL_ERR_IND_EN BIT(5)
   1834#define B_AX_PHYINTF_ERR_IND_EN BIT(4)
   1835#define B_AX_DMA_TOP_ERR_IND_EN BIT(3)
   1836#define B_AX_PTCL_TOP_ERR_IND_EN BIT(1)
   1837#define B_AX_SCHEDULE_TOP_ERR_IND_EN BIT(0)
   1838#define CMAC0_ERR_IMR_EN GENMASK(31, 0)
   1839#define CMAC1_ERR_IMR_EN GENMASK(31, 0)
   1840#define CMAC0_ERR_IMR_DIS 0
   1841#define CMAC1_ERR_IMR_DIS 0
   1842
   1843#define R_AX_CMAC_ERR_ISR 0xC164
   1844#define R_AX_CMAC_ERR_ISR_C1 0xE164
   1845#define B_AX_WMAC_TX_ERR_IND BIT(7)
   1846#define B_AX_WMAC_RX_ERR_IND BIT(6)
   1847#define B_AX_TXPWR_CTRL_ERR_IND BIT(5)
   1848#define B_AX_PHYINTF_ERR_IND BIT(4)
   1849#define B_AX_DMA_TOP_ERR_IND BIT(3)
   1850#define B_AX_PTCL_TOP_ERR_IND BIT(1)
   1851#define B_AX_SCHEDULE_TOP_ERR_IND BIT(0)
   1852
   1853#define R_AX_MACID_SLEEP_0 0xC2C0
   1854#define R_AX_MACID_SLEEP_0_C1 0xE2C0
   1855#define B_AX_MACID31_0_SLEEP_SH 0
   1856#define B_AX_MACID31_0_SLEEP_MASK GENMASK(31, 0)
   1857
   1858#define R_AX_MACID_SLEEP_1 0xC2C4
   1859#define R_AX_MACID_SLEEP_1_C1 0xE2C4
   1860#define B_AX_MACID63_32_SLEEP_SH 0
   1861#define B_AX_MACID63_32_SLEEP_MASK GENMASK(31, 0)
   1862
   1863#define R_AX_MACID_SLEEP_2 0xC2C8
   1864#define R_AX_MACID_SLEEP_2_C1 0xE2C8
   1865#define B_AX_MACID95_64_SLEEP_SH 0
   1866#define B_AX_MACID95_64_SLEEP_MASK GENMASK(31, 0)
   1867
   1868#define R_AX_MACID_SLEEP_3 0xC2CC
   1869#define R_AX_MACID_SLEEP_3_C1 0xE2CC
   1870#define B_AX_MACID127_96_SLEEP_SH 0
   1871#define B_AX_MACID127_96_SLEEP_MASK GENMASK(31, 0)
   1872
   1873#define SCH_PREBKF_24US 0x18
   1874#define R_AX_PREBKF_CFG_0 0xC338
   1875#define R_AX_PREBKF_CFG_0_C1 0xE338
   1876#define B_AX_PREBKF_TIME_MASK GENMASK(4, 0)
   1877
   1878#define R_AX_PREBKF_CFG_1 0xC33C
   1879#define R_AX_PREBKF_CFG_1_C1 0xE33C
   1880#define B_AX_SIFS_TIMEOUT_TB_AGGR_MASK GENMASK(30, 24)
   1881#define B_AX_SIFS_PREBKF_MASK GENMASK(23, 16)
   1882#define B_AX_SIFS_TIMEOUT_T2_MASK GENMASK(14, 8)
   1883#define B_AX_SIFS_MACTXEN_T1_MASK GENMASK(6, 0)
   1884#define SIFS_MACTXEN_T1 0x47
   1885
   1886#define R_AX_CCA_CFG_0 0xC340
   1887#define R_AX_CCA_CFG_0_C1 0xE340
   1888#define B_AX_BTCCA_BRK_TXOP_EN BIT(9)
   1889#define B_AX_BTCCA_EN BIT(5)
   1890#define B_AX_EDCCA_EN BIT(4)
   1891#define B_AX_SEC80_EN BIT(3)
   1892#define B_AX_SEC40_EN BIT(2)
   1893#define B_AX_SEC20_EN BIT(1)
   1894#define B_AX_CCA_EN BIT(0)
   1895
   1896#define R_AX_CTN_TXEN 0xC348
   1897#define R_AX_CTN_TXEN_C1 0xE348
   1898#define B_AX_CTN_TXEN_TWT_1 BIT(15)
   1899#define B_AX_CTN_TXEN_TWT_0 BIT(14)
   1900#define B_AX_CTN_TXEN_ULQ BIT(13)
   1901#define B_AX_CTN_TXEN_BCNQ BIT(12)
   1902#define B_AX_CTN_TXEN_HGQ BIT(11)
   1903#define B_AX_CTN_TXEN_CPUMGQ BIT(10)
   1904#define B_AX_CTN_TXEN_MGQ1 BIT(9)
   1905#define B_AX_CTN_TXEN_MGQ BIT(8)
   1906#define B_AX_CTN_TXEN_VO_1 BIT(7)
   1907#define B_AX_CTN_TXEN_VI_1 BIT(6)
   1908#define B_AX_CTN_TXEN_BK_1 BIT(5)
   1909#define B_AX_CTN_TXEN_BE_1 BIT(4)
   1910#define B_AX_CTN_TXEN_VO_0 BIT(3)
   1911#define B_AX_CTN_TXEN_VI_0 BIT(2)
   1912#define B_AX_CTN_TXEN_BK_0 BIT(1)
   1913#define B_AX_CTN_TXEN_BE_0 BIT(0)
   1914#define B_AX_CTN_TXEN_ALL_MASK GENMASK(15, 0)
   1915
   1916#define R_AX_MUEDCA_BE_PARAM_0 0xC350
   1917#define R_AX_MUEDCA_BE_PARAM_0_C1 0xE350
   1918#define B_AX_MUEDCA_BE_PARAM_0_TIMER_MASK GENMASK(31, 16)
   1919#define B_AX_MUEDCA_BE_PARAM_0_CW_MASK GENMASK(15, 8)
   1920#define B_AX_MUEDCA_BE_PARAM_0_AIFS_MASK GENMASK(7, 0)
   1921
   1922#define R_AX_MUEDCA_BK_PARAM_0 0xC354
   1923#define R_AX_MUEDCA_BK_PARAM_0_C1 0xE354
   1924#define R_AX_MUEDCA_VI_PARAM_0 0xC358
   1925#define R_AX_MUEDCA_VI_PARAM_0_C1 0xE358
   1926#define R_AX_MUEDCA_VO_PARAM_0 0xC35C
   1927#define R_AX_MUEDCA_VO_PARAM_0_C1 0xE35C
   1928
   1929#define R_AX_MUEDCA_EN 0xC370
   1930#define R_AX_MUEDCA_EN_C1 0xE370
   1931#define B_AX_MUEDCA_WMM_SEL BIT(8)
   1932#define B_AX_SET_MUEDCATIMER_TF_0 BIT(4)
   1933#define B_AX_MUEDCA_EN_0 BIT(0)
   1934
   1935#define R_AX_CCA_CONTROL 0xC390
   1936#define R_AX_CCA_CONTROL_C1 0xE390
   1937#define B_AX_TB_CHK_TX_NAV BIT(31)
   1938#define B_AX_TB_CHK_BASIC_NAV BIT(30)
   1939#define B_AX_TB_CHK_BTCCA BIT(29)
   1940#define B_AX_TB_CHK_EDCCA BIT(28)
   1941#define B_AX_TB_CHK_CCA_S80 BIT(27)
   1942#define B_AX_TB_CHK_CCA_S40 BIT(26)
   1943#define B_AX_TB_CHK_CCA_S20 BIT(25)
   1944#define B_AX_TB_CHK_CCA_P20 BIT(24)
   1945#define B_AX_SIFS_CHK_BTCCA BIT(21)
   1946#define B_AX_SIFS_CHK_EDCCA BIT(20)
   1947#define B_AX_SIFS_CHK_CCA_S80 BIT(19)
   1948#define B_AX_SIFS_CHK_CCA_S40 BIT(18)
   1949#define B_AX_SIFS_CHK_CCA_S20 BIT(17)
   1950#define B_AX_SIFS_CHK_CCA_P20 BIT(16)
   1951#define B_AX_CTN_CHK_TXNAV BIT(8)
   1952#define B_AX_CTN_CHK_INTRA_NAV BIT(7)
   1953#define B_AX_CTN_CHK_BASIC_NAV BIT(6)
   1954#define B_AX_CTN_CHK_BTCCA BIT(5)
   1955#define B_AX_CTN_CHK_EDCCA BIT(4)
   1956#define B_AX_CTN_CHK_CCA_S80 BIT(3)
   1957#define B_AX_CTN_CHK_CCA_S40 BIT(2)
   1958#define B_AX_CTN_CHK_CCA_S20 BIT(1)
   1959#define B_AX_CTN_CHK_CCA_P20 BIT(0)
   1960
   1961#define R_AX_CTN_DRV_TXEN 0xC398
   1962#define R_AX_CTN_DRV_TXEN_C1 0xE398
   1963#define B_AX_CTN_TXEN_TWT_3 BIT(17)
   1964#define B_AX_CTN_TXEN_TWT_2 BIT(16)
   1965#define B_AX_CTN_TXEN_ALL_MASK_V1 GENMASK(17, 0)
   1966
   1967#define R_AX_SCHEDULE_ERR_IMR 0xC3E8
   1968#define R_AX_SCHEDULE_ERR_IMR_C1 0xE3E8
   1969#define B_AX_SORT_NON_IDLE_ERR_INT_EN BIT(1)
   1970
   1971#define R_AX_SCHEDULE_ERR_ISR 0xC3EC
   1972#define R_AX_SCHEDULE_ERR_ISR_C1 0xE3EC
   1973
   1974#define R_AX_SCH_DBG_SEL 0xC3F4
   1975#define R_AX_SCH_DBG_SEL_C1 0xE3F4
   1976#define B_AX_SCH_DBG_EN BIT(16)
   1977#define B_AX_SCH_CFG_CMD_SEL GENMASK(15, 8)
   1978#define B_AX_SCH_DBG_SEL_MASK GENMASK(7, 0)
   1979
   1980#define R_AX_SCH_DBG 0xC3F8
   1981#define R_AX_SCH_DBG_C1 0xE3F8
   1982#define B_AX_SCHEDULER_DBG_MASK GENMASK(31, 0)
   1983
   1984#define R_AX_SCH_EXT_CTRL 0xC3FC
   1985#define R_AX_SCH_EXT_CTRL_C1 0xE3FC
   1986#define B_AX_PORT_RST_TSF_ADV BIT(1)
   1987
   1988#define R_AX_PORT_CFG_P0 0xC400
   1989#define R_AX_PORT_CFG_P1 0xC440
   1990#define R_AX_PORT_CFG_P2 0xC480
   1991#define R_AX_PORT_CFG_P3 0xC4C0
   1992#define R_AX_PORT_CFG_P4 0xC500
   1993#define B_AX_BRK_SETUP BIT(16)
   1994#define B_AX_TBTT_UPD_SHIFT_SEL BIT(15)
   1995#define B_AX_BCN_DROP_ALLOW BIT(14)
   1996#define B_AX_TBTT_PROHIB_EN BIT(13)
   1997#define B_AX_BCNTX_EN BIT(12)
   1998#define B_AX_NET_TYPE_MASK GENMASK(11, 10)
   1999#define B_AX_BCN_FORCETX_EN BIT(9)
   2000#define B_AX_TXBCN_BTCCA_EN BIT(8)
   2001#define B_AX_BCNERR_CNT_EN BIT(7)
   2002#define B_AX_BCN_AGRES BIT(6)
   2003#define B_AX_TSFTR_RST BIT(5)
   2004#define B_AX_RX_BSSID_FIT_EN BIT(4)
   2005#define B_AX_TSF_UDT_EN BIT(3)
   2006#define B_AX_PORT_FUNC_EN BIT(2)
   2007#define B_AX_TXBCN_RPT_EN BIT(1)
   2008#define B_AX_RXBCN_RPT_EN BIT(0)
   2009
   2010#define R_AX_TBTT_PROHIB_P0 0xC404
   2011#define R_AX_TBTT_PROHIB_P1 0xC444
   2012#define R_AX_TBTT_PROHIB_P2 0xC484
   2013#define R_AX_TBTT_PROHIB_P3 0xC4C4
   2014#define R_AX_TBTT_PROHIB_P4 0xC504
   2015#define B_AX_TBTT_HOLD_MASK GENMASK(27, 16)
   2016#define B_AX_TBTT_SETUP_MASK GENMASK(7, 0)
   2017
   2018#define R_AX_BCN_AREA_P0 0xC408
   2019#define R_AX_BCN_AREA_P1 0xC448
   2020#define R_AX_BCN_AREA_P2 0xC488
   2021#define R_AX_BCN_AREA_P3 0xC4C8
   2022#define R_AX_BCN_AREA_P4 0xC508
   2023#define B_AX_BCN_MSK_AREA_MASK GENMASK(27, 16)
   2024#define B_AX_BCN_CTN_AREA_MASK GENMASK(11, 0)
   2025
   2026#define R_AX_BCNERLYINT_CFG_P0 0xC40C
   2027#define R_AX_BCNERLYINT_CFG_P1 0xC44C
   2028#define R_AX_BCNERLYINT_CFG_P2 0xC48C
   2029#define R_AX_BCNERLYINT_CFG_P3 0xC4CC
   2030#define R_AX_BCNERLYINT_CFG_P4 0xC50C
   2031#define B_AX_BCNERLY_MASK GENMASK(11, 0)
   2032
   2033#define R_AX_TBTTERLYINT_CFG_P0 0xC40E
   2034#define R_AX_TBTTERLYINT_CFG_P1 0xC44E
   2035#define R_AX_TBTTERLYINT_CFG_P2 0xC48E
   2036#define R_AX_TBTTERLYINT_CFG_P3 0xC4CE
   2037#define R_AX_TBTTERLYINT_CFG_P4 0xC50E
   2038#define B_AX_TBTTERLY_MASK GENMASK(11, 0)
   2039
   2040#define R_AX_TBTT_AGG_P0 0xC412
   2041#define R_AX_TBTT_AGG_P1 0xC452
   2042#define R_AX_TBTT_AGG_P2 0xC492
   2043#define R_AX_TBTT_AGG_P3 0xC4D2
   2044#define R_AX_TBTT_AGG_P4 0xC512
   2045#define B_AX_TBTT_AGG_NUM_MASK GENMASK(15, 8)
   2046
   2047#define R_AX_BCN_SPACE_CFG_P0 0xC414
   2048#define R_AX_BCN_SPACE_CFG_P1 0xC454
   2049#define R_AX_BCN_SPACE_CFG_P2 0xC494
   2050#define R_AX_BCN_SPACE_CFG_P3 0xC4D4
   2051#define R_AX_BCN_SPACE_CFG_P4 0xC514
   2052#define B_AX_SUB_BCN_SPACE_MASK GENMASK(23, 16)
   2053#define B_AX_BCN_SPACE_MASK GENMASK(15, 0)
   2054
   2055#define R_AX_BCN_FORCETX_P0 0xC418
   2056#define R_AX_BCN_FORCETX_P1 0xC458
   2057#define R_AX_BCN_FORCETX_P2 0xC498
   2058#define R_AX_BCN_FORCETX_P3 0xC4D8
   2059#define R_AX_BCN_FORCETX_P4 0xC518
   2060#define B_AX_FORCE_BCN_CURRCNT_MASK GENMASK(23, 16)
   2061#define B_AX_FORCE_BCN_NUM_MASK GENMASK(15, 0)
   2062#define B_AX_BCN_MAX_ERR_MASK GENMASK(7, 0)
   2063
   2064#define R_AX_BCN_ERR_CNT_P0 0xC420
   2065#define R_AX_BCN_ERR_CNT_P1 0xC460
   2066#define R_AX_BCN_ERR_CNT_P2 0xC4A0
   2067#define R_AX_BCN_ERR_CNT_P3 0xC4E0
   2068#define R_AX_BCN_ERR_CNT_P4 0xC520
   2069#define B_AX_BCN_ERR_CNT_SUM_MASK GENMASK(31, 24)
   2070#define B_AX_BCN_ERR_CNT_NAV_MASK GENMASK(23, 16)
   2071#define B_AX_BCN_ERR_CNT_EDCCA_MASK GENMASK(15, 0)
   2072#define B_AX_BCN_ERR_CNT_CCA_MASK GENMASK(7, 0)
   2073
   2074#define R_AX_BCN_ERR_FLAG_P0 0xC424
   2075#define R_AX_BCN_ERR_FLAG_P1 0xC464
   2076#define R_AX_BCN_ERR_FLAG_P2 0xC4A4
   2077#define R_AX_BCN_ERR_FLAG_P3 0xC4E4
   2078#define R_AX_BCN_ERR_FLAG_P4 0xC524
   2079#define B_AX_BCN_ERR_FLAG_OTHERS BIT(6)
   2080#define B_AX_BCN_ERR_FLAG_MAC BIT(5)
   2081#define B_AX_BCN_ERR_FLAG_TXON BIT(4)
   2082#define B_AX_BCN_ERR_FLAG_SRCHEND BIT(3)
   2083#define B_AX_BCN_ERR_FLAG_INVALID BIT(2)
   2084#define B_AX_BCN_ERR_FLAG_CMP BIT(1)
   2085#define B_AX_BCN_ERR_FLAG_LOCK BIT(0)
   2086
   2087#define R_AX_DTIM_CTRL_P0 0xC426
   2088#define R_AX_DTIM_CTRL_P1 0xC466
   2089#define R_AX_DTIM_CTRL_P2 0xC4A6
   2090#define R_AX_DTIM_CTRL_P3 0xC4E6
   2091#define R_AX_DTIM_CTRL_P4 0xC526
   2092#define B_AX_DTIM_NUM_MASK GENMASK(15, 8)
   2093#define B_AX_DTIM_CURRCNT_MASK GENMASK(7, 0)
   2094
   2095#define R_AX_TBTT_SHIFT_P0 0xC428
   2096#define R_AX_TBTT_SHIFT_P1 0xC468
   2097#define R_AX_TBTT_SHIFT_P2 0xC4A8
   2098#define R_AX_TBTT_SHIFT_P3 0xC4E8
   2099#define R_AX_TBTT_SHIFT_P4 0xC528
   2100#define B_AX_TBTT_SHIFT_OFST_MASK GENMASK(11, 0)
   2101
   2102#define R_AX_BCN_CNT_TMR_P0 0xC434
   2103#define R_AX_BCN_CNT_TMR_P1 0xC474
   2104#define R_AX_BCN_CNT_TMR_P2 0xC4B4
   2105#define R_AX_BCN_CNT_TMR_P3 0xC4F4
   2106#define R_AX_BCN_CNT_TMR_P4 0xC534
   2107#define B_AX_BCN_CNT_TMR_MASK GENMASK(31, 0)
   2108
   2109#define R_AX_TSFTR_LOW_P0 0xC438
   2110#define R_AX_TSFTR_LOW_P1 0xC478
   2111#define R_AX_TSFTR_LOW_P2 0xC4B8
   2112#define R_AX_TSFTR_LOW_P3 0xC4F8
   2113#define R_AX_TSFTR_LOW_P4 0xC538
   2114#define B_AX_TSFTR_LOW_MASK GENMASK(31, 0)
   2115
   2116#define R_AX_TSFTR_HIGH_P0 0xC43C
   2117#define R_AX_TSFTR_HIGH_P1 0xC47C
   2118#define R_AX_TSFTR_HIGH_P2 0xC4BC
   2119#define R_AX_TSFTR_HIGH_P3 0xC4FC
   2120#define R_AX_TSFTR_HIGH_P4 0xC53C
   2121#define B_AX_TSFTR_HIGH_MASK GENMASK(31, 0)
   2122
   2123#define R_AX_MBSSID_CTRL 0xC568
   2124#define R_AX_MBSSID_CTRL_C1 0xE568
   2125#define B_AX_P0MB_ALL_MASK GENMASK(23, 1)
   2126#define B_AX_P0MB_NUM_MASK GENMASK(19, 16)
   2127#define B_AX_P0MB15_EN BIT(15)
   2128#define B_AX_P0MB14_EN BIT(14)
   2129#define B_AX_P0MB13_EN BIT(13)
   2130#define B_AX_P0MB12_EN BIT(12)
   2131#define B_AX_P0MB11_EN BIT(11)
   2132#define B_AX_P0MB10_EN BIT(10)
   2133#define B_AX_P0MB9_EN BIT(9)
   2134#define B_AX_P0MB8_EN BIT(8)
   2135#define B_AX_P0MB7_EN BIT(7)
   2136#define B_AX_P0MB6_EN BIT(6)
   2137#define B_AX_P0MB5_EN BIT(5)
   2138#define B_AX_P0MB4_EN BIT(4)
   2139#define B_AX_P0MB3_EN BIT(3)
   2140#define B_AX_P0MB2_EN BIT(2)
   2141#define B_AX_P0MB1_EN BIT(1)
   2142
   2143#define R_AX_P0MB_HGQ_WINDOW_CFG_0 0xC590
   2144#define R_AX_P0MB_HGQ_WINDOW_CFG_0_C1 0xE590
   2145#define R_AX_PORT_HGQ_WINDOW_CFG 0xC5A0
   2146#define R_AX_PORT_HGQ_WINDOW_CFG_C1 0xE5A0
   2147
   2148#define R_AX_PTCL_COMMON_SETTING_0 0xC600
   2149#define R_AX_PTCL_COMMON_SETTING_0_C1 0xE600
   2150#define B_AX_PCIE_MODE_MASK GENMASK(15, 14)
   2151#define B_AX_CPUMGQ_LIFETIME_EN BIT(8)
   2152#define B_AX_MGQ_LIFETIME_EN BIT(7)
   2153#define B_AX_LIFETIME_EN BIT(6)
   2154#define B_AX_PTCL_TRIGGER_SS_EN_UL BIT(4)
   2155#define B_AX_PTCL_TRIGGER_SS_EN_1 BIT(3)
   2156#define B_AX_PTCL_TRIGGER_SS_EN_0 BIT(2)
   2157#define B_AX_CMAC_TX_MODE_1 BIT(1)
   2158#define B_AX_CMAC_TX_MODE_0 BIT(0)
   2159
   2160#define R_AX_AMPDU_AGG_LIMIT 0xC610
   2161#define B_AX_AMPDU_MAX_TIME_MASK GENMASK(31, 24)
   2162#define B_AX_RA_TRY_RATE_AGG_LMT_MASK GENMASK(23, 16)
   2163#define B_AX_RTS_MAX_AGG_NUM_MASK GENMASK(15, 8)
   2164#define B_AX_MAX_AGG_NUM_MASK GENMASK(7, 0)
   2165
   2166#define R_AX_AGG_LEN_HT_0 0xC614
   2167#define R_AX_AGG_LEN_HT_0_C1 0xE614
   2168#define B_AX_AMPDU_MAX_LEN_HT_MASK GENMASK(31, 16)
   2169#define B_AX_RTS_TXTIME_TH_MASK GENMASK(15, 8)
   2170#define B_AX_RTS_LEN_TH_MASK GENMASK(7, 0)
   2171
   2172#define S_AX_CTS2S_TH_SEC_256B 1
   2173#define R_AX_SIFS_SETTING 0xC624
   2174#define R_AX_SIFS_SETTING_C1 0xE624
   2175#define B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK GENMASK(31, 24)
   2176#define B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK GENMASK(23, 18)
   2177#define B_AX_HW_CTS2SELF_EN BIT(16)
   2178#define B_AX_SPEC_SIFS_OFDM_PTCL_SH 8
   2179#define B_AX_SPEC_SIFS_OFDM_PTCL_MASK GENMASK(15, 8)
   2180#define B_AX_SPEC_SIFS_CCK_PTCL_MASK GENMASK(7, 0)
   2181#define S_AX_CTS2S_TH_1K 4
   2182
   2183#define R_AX_TXRATE_CHK 0xC628
   2184#define R_AX_TXRATE_CHK_C1 0xE628
   2185#define B_AX_DEFT_RATE_MASK GENMASK(15, 7)
   2186#define B_AX_BAND_MODE BIT(4)
   2187#define B_AX_MAX_TXNSS_MASK GENMASK(3, 2)
   2188#define B_AX_RTS_LIMIT_IN_OFDM6 BIT(1)
   2189#define B_AX_CHECK_CCK_EN BIT(0)
   2190
   2191#define R_AX_TXCNT 0xC62C
   2192#define R_AX_TXCNT_C1 0xE62C
   2193#define B_AX_ADD_TXCNT_BY BIT(31)
   2194#define B_AX_S_TXCNT_LMT_MASK GENMASK(29, 24)
   2195#define B_AX_L_TXCNT_LMT_MASK GENMASK(21, 16)
   2196
   2197#define R_AX_MBSSID_DROP_0 0xC63C
   2198#define R_AX_MBSSID_DROP_0_C1 0xE63C
   2199#define B_AX_GI_LTF_FB_SEL BIT(30)
   2200#define B_AX_RATE_SEL_MASK GENMASK(29, 24)
   2201#define B_AX_PORT_DROP_4_0_MASK GENMASK(20, 16)
   2202#define B_AX_MBSSID_DROP_15_0_MASK GENMASK(15, 0)
   2203
   2204#define R_AX_PTCLRPT_FULL_HDL 0xC660
   2205#define R_AX_PTCLRPT_FULL_HDL_C1 0xE660
   2206#define B_AX_RPT_LATCH_PHY_TIME_MASK GENMASK(15, 12)
   2207#define B_AX_F2PCMD_FWWD_RLS_MODE BIT(9)
   2208#define B_AX_F2PCMD_RPT_EN BIT(8)
   2209#define B_AX_BCN_RPT_PATH_MASK GENMASK(7, 6)
   2210#define B_AX_SPE_RPT_PATH_MASK GENMASK(5, 4)
   2211#define FWD_TO_WLCPU 1
   2212#define B_AX_TX_RPT_PATH_MASK GENMASK(3, 2)
   2213#define B_AX_F2PCMDRPT_FULL_DROP BIT(1)
   2214#define B_AX_NON_F2PCMDRPT_FULL_DROP BIT(0)
   2215
   2216#define R_AX_BT_PLT 0xC67C
   2217#define R_AX_BT_PLT_C1 0xE67C
   2218#define B_AX_BT_PLT_PKT_CNT_MASK GENMASK(31, 16)
   2219#define B_AX_BT_PLT_RST BIT(9)
   2220#define B_AX_PLT_EN BIT(8)
   2221#define B_AX_RX_PLT_GNT_LTE_RX BIT(7)
   2222#define B_AX_RX_PLT_GNT_BT_RX BIT(6)
   2223#define B_AX_RX_PLT_GNT_BT_TX BIT(5)
   2224#define B_AX_RX_PLT_GNT_WL BIT(4)
   2225#define B_AX_TX_PLT_GNT_LTE_RX BIT(3)
   2226#define B_AX_TX_PLT_GNT_BT_RX BIT(2)
   2227#define B_AX_TX_PLT_GNT_BT_TX BIT(1)
   2228#define B_AX_TX_PLT_GNT_WL BIT(0)
   2229
   2230#define R_AX_PTCL_BSS_COLOR_0 0xC6A0
   2231#define R_AX_PTCL_BSS_COLOR_0_C1 0xE6A0
   2232#define B_AX_BSS_COLOB_AX_PORT_3_MASK GENMASK(29, 24)
   2233#define B_AX_BSS_COLOB_AX_PORT_2_MASK GENMASK(21, 16)
   2234#define B_AX_BSS_COLOB_AX_PORT_1_MASK GENMASK(13, 8)
   2235#define B_AX_BSS_COLOB_AX_PORT_0_MASK GENMASK(5, 0)
   2236
   2237#define R_AX_PTCL_BSS_COLOR_1 0xC6A4
   2238#define R_AX_PTCL_BSS_COLOR_1_C1 0xE6A4
   2239#define B_AX_BSS_COLOB_AX_PORT_4_MASK GENMASK(5, 0)
   2240
   2241#define R_AX_PTCL_IMR0 0xC6C0
   2242#define R_AX_PTCL_IMR0_C1 0xE6C0
   2243#define B_AX_F2PCMD_PKTID_ERR_INT_EN BIT(31)
   2244#define B_AX_F2PCMD_RD_PKTID_ERR_INT_EN BIT(30)
   2245#define B_AX_F2PCMD_ASSIGN_PKTID_ERR_INT_EN BIT(29)
   2246#define B_AX_F2PCMD_USER_ALLC_ERR_INT_EN BIT(28)
   2247#define B_AX_RX_SPF_U0_PKTID_ERR_INT_EN BIT(27)
   2248#define B_AX_TX_SPF_U1_PKTID_ERR_INT_EN BIT(26)
   2249#define B_AX_TX_SPF_U2_PKTID_ERR_INT_EN BIT(25)
   2250#define B_AX_TX_SPF_U3_PKTID_ERR_INT_EN BIT(24)
   2251#define B_AX_TX_RECORD_PKTID_ERR_INT_EN BIT(23)
   2252#define B_AX_F2PCMD_EMPTY_ERR_INT_EN BIT(15)
   2253#define B_AX_TWTSP_QSEL_ERR_INT_EN BIT(14)
   2254#define B_AX_BCNQ_ORDER_ERR_INT_EN BIT(12)
   2255#define B_AX_Q_PKTID_ERR_INT_EN BIT(11)
   2256#define B_AX_D_PKTID_ERR_INT_EN BIT(10)
   2257#define B_AX_TXPRT_FULL_DROP_ERR_INT_EN BIT(9)
   2258#define B_AX_F2PCMDRPT_FULL_DROP_ERR_INT_EN BIT(8)
   2259#define B_AX_FSM1_TIMEOUT_ERR_INT_EN BIT(1)
   2260#define B_AX_FSM_TIMEOUT_ERR_INT_EN BIT(0)
   2261#define B_AX_PTCL_IMR_CLR (B_AX_FSM_TIMEOUT_ERR_INT_EN | \
   2262			   B_AX_F2PCMDRPT_FULL_DROP_ERR_INT_EN | \
   2263			   B_AX_TXPRT_FULL_DROP_ERR_INT_EN | \
   2264			   B_AX_D_PKTID_ERR_INT_EN | \
   2265			   B_AX_Q_PKTID_ERR_INT_EN | \
   2266			   B_AX_BCNQ_ORDER_ERR_INT_EN | \
   2267			   B_AX_TWTSP_QSEL_ERR_INT_EN | \
   2268			   B_AX_F2PCMD_EMPTY_ERR_INT_EN | \
   2269			   B_AX_TX_RECORD_PKTID_ERR_INT_EN | \
   2270			   B_AX_TX_SPF_U3_PKTID_ERR_INT_EN | \
   2271			   B_AX_TX_SPF_U2_PKTID_ERR_INT_EN | \
   2272			   B_AX_TX_SPF_U1_PKTID_ERR_INT_EN | \
   2273			   B_AX_RX_SPF_U0_PKTID_ERR_INT_EN | \
   2274			   B_AX_F2PCMD_USER_ALLC_ERR_INT_EN | \
   2275			   B_AX_F2PCMD_ASSIGN_PKTID_ERR_INT_EN | \
   2276			   B_AX_F2PCMD_RD_PKTID_ERR_INT_EN | \
   2277			   B_AX_F2PCMD_PKTID_ERR_INT_EN)
   2278#define B_AX_PTCL_IMR_SET (B_AX_FSM_TIMEOUT_ERR_INT_EN | \
   2279			   B_AX_TX_RECORD_PKTID_ERR_INT_EN | \
   2280			   B_AX_F2PCMD_USER_ALLC_ERR_INT_EN)
   2281#define B_AX_PTCL_IMR_CLR_V1 (B_AX_FSM1_TIMEOUT_ERR_INT_EN | \
   2282			      B_AX_FSM_TIMEOUT_ERR_INT_EN)
   2283#define B_AX_PTCL_IMR_SET_V1 (B_AX_FSM1_TIMEOUT_ERR_INT_EN | \
   2284			      B_AX_FSM_TIMEOUT_ERR_INT_EN)
   2285
   2286#define R_AX_PTCL_ISR0 0xC6C4
   2287#define R_AX_PTCL_ISR0_C1 0xE6C4
   2288
   2289#define S_AX_PTCL_TO_2MS 0x3F
   2290#define R_AX_PTCL_FSM_MON 0xC6E8
   2291#define R_AX_PTCL_FSM_MON_C1 0xE6E8
   2292#define B_AX_PTCL_TX_ARB_TO_MODE BIT(6)
   2293#define B_AX_PTCL_TX_ARB_TO_THR_MASK GENMASK(5, 0)
   2294
   2295#define R_AX_PTCL_TX_CTN_SEL 0xC6EC
   2296#define R_AX_PTCL_TX_CTN_SEL_C1 0xE6EC
   2297#define B_AX_PTCL_TX_ON_STAT BIT(7)
   2298
   2299#define R_AX_PTCL_DBG_INFO 0xC6F0
   2300#define R_AX_PTCL_DBG_INFO_C1 0xE6F0
   2301#define B_AX_PTCL_DBG_INFO_MASK GENMASK(31, 0)
   2302#define R_AX_PTCL_DBG 0xC6F4
   2303#define R_AX_PTCL_DBG_C1 0xE6F4
   2304#define B_AX_PTCL_DBG_EN BIT(8)
   2305#define B_AX_PTCL_DBG_SEL_MASK GENMASK(7, 0)
   2306
   2307#define R_AX_DLE_CTRL 0xC800
   2308#define R_AX_DLE_CTRL_C1 0xE800
   2309#define B_AX_NO_RESERVE_PAGE_ERR_IMR BIT(23)
   2310#define B_AX_RXDATA_FSM_HANG_ERROR_IMR BIT(15)
   2311#define B_AX_RXSTS_FSM_HANG_ERROR_IMR BIT(14)
   2312#define B_AX_DLE_IMR_CLR (B_AX_RXSTS_FSM_HANG_ERROR_IMR | \
   2313			  B_AX_RXDATA_FSM_HANG_ERROR_IMR | \
   2314			  B_AX_NO_RESERVE_PAGE_ERR_IMR)
   2315#define B_AX_DLE_IMR_SET (B_AX_RXSTS_FSM_HANG_ERROR_IMR | \
   2316			  B_AX_RXDATA_FSM_HANG_ERROR_IMR)
   2317
   2318#define R_AX_RXDMA_PKT_INFO_0 0xC814
   2319#define R_AX_RXDMA_PKT_INFO_1 0xC818
   2320#define R_AX_RXDMA_PKT_INFO_2 0xC81C
   2321
   2322#define R_AX_RX_ERR_FLAG_IMR 0xC804
   2323#define R_AX_RX_ERR_FLAG_IMR_C1 0xE804
   2324#define B_AX_RX_GET_NULL_PKT_ERR_MSK BIT(30)
   2325#define B_AX_RX_RU0_FSM_HANG_MSK_ERR_MSK BIT(29)
   2326#define B_AX_RX_RU1_FSM_HANG_MSK_ERR_MSK BIT(28)
   2327#define B_AX_RX_RU2_FSM_HANG_MSK_ERR_MSK BIT(27)
   2328#define B_AX_RX_RU3_FSM_HANG_MSK_ERR_MSK BIT(26)
   2329#define B_AX_RX_RU4_FSM_HANG_MSK_ERR_MSK BIT(25)
   2330#define B_AX_RX_RU5_FSM_HANG_MSK_ERR_MSK BIT(24)
   2331#define B_AX_RX_RU6_FSM_HANG_MSK_ERR_MSK BIT(23)
   2332#define B_AX_RX_RU7_FSM_HANG_MSK_ERR_MSK BIT(22)
   2333#define B_AX_RX_RXSTS_FSM_HANG_MSK_ERR_MSK BIT(21)
   2334#define B_AX_RX_CSI_FSM_HANG_MSK_ERR_MSK BIT(20)
   2335#define B_AX_RX_TXRPT_FSM_HANG_MSK_ERR_MSK BIT(19)
   2336#define B_AX_RX_F2PCMD_FSM_HANG_MSK_ERR_MSK BIT(18)
   2337#define B_AX_RX_RU0_ZERO_LEN_ERR_MSK BIT(17)
   2338#define B_AX_RX_RU1_ZERO_LEN_ERR_MSK BIT(16)
   2339#define B_AX_RX_RU2_ZERO_LEN_ERR_MSK BIT(15)
   2340#define B_AX_RX_RU3_ZERO_LEN_ERR_MSK BIT(14)
   2341#define B_AX_RX_RU4_ZERO_LEN_ERR_MSK BIT(13)
   2342#define B_AX_RX_RU5_ZERO_LEN_ERR_MSK BIT(12)
   2343#define B_AX_RX_RU6_ZERO_LEN_ERR_MSK BIT(11)
   2344#define B_AX_RX_RU7_ZERO_LEN_ERR_MSK BIT(10)
   2345#define B_AX_RX_RXSTS_ZERO_LEN_ERR_MSK BIT(9)
   2346#define B_AX_RX_CSI_ZERO_LEN_ERR_MSK BIT(8)
   2347#define B_AX_PLE_DATA_OPT_FSM_HANG_MSK BIT(7)
   2348#define B_AX_PLE_RXDATA_REQ_BUF_FSM_HANG_MSK BIT(6)
   2349#define B_AX_PLE_TXRPT_REQ_BUF_FSM_HANG_MSK BIT(5)
   2350#define B_AX_PLE_WD_OPT_FSM_HANG_MSK BIT(4)
   2351#define B_AX_PLE_ENQ_FSM_HANG_MSK BIT(3)
   2352#define B_AX_RXDATA_ENQUE_ORDER_ERR_MSK BIT(2)
   2353#define B_AX_RXSTS_ENQUE_ORDER_ERR_MSK BIT(1)
   2354#define B_AX_RX_CSI_PKT_NUM_ERR_MSK BIT(0)
   2355#define B_AX_RX_ERR_IMR_CLR_V1 (B_AX_RXSTS_ENQUE_ORDER_ERR_MSK | \
   2356				B_AX_RXDATA_ENQUE_ORDER_ERR_MSK | \
   2357				B_AX_RX_CSI_ZERO_LEN_ERR_MSK | \
   2358				B_AX_RX_RXSTS_ZERO_LEN_ERR_MSK | \
   2359				B_AX_RX_RU7_ZERO_LEN_ERR_MSK | \
   2360				B_AX_RX_RU6_ZERO_LEN_ERR_MSK | \
   2361				B_AX_RX_RU5_ZERO_LEN_ERR_MSK | \
   2362				B_AX_RX_RU4_ZERO_LEN_ERR_MSK | \
   2363				B_AX_RX_RU3_ZERO_LEN_ERR_MSK | \
   2364				B_AX_RX_RU2_ZERO_LEN_ERR_MSK | \
   2365				B_AX_RX_RU1_ZERO_LEN_ERR_MSK | \
   2366				B_AX_RX_RU0_ZERO_LEN_ERR_MSK | \
   2367				B_AX_RX_F2PCMD_FSM_HANG_MSK_ERR_MSK | \
   2368				B_AX_RX_TXRPT_FSM_HANG_MSK_ERR_MSK | \
   2369				B_AX_RX_CSI_FSM_HANG_MSK_ERR_MSK | \
   2370				B_AX_RX_RXSTS_FSM_HANG_MSK_ERR_MSK | \
   2371				B_AX_RX_RU7_FSM_HANG_MSK_ERR_MSK | \
   2372				B_AX_RX_RU6_FSM_HANG_MSK_ERR_MSK | \
   2373				B_AX_RX_RU5_FSM_HANG_MSK_ERR_MSK | \
   2374				B_AX_RX_RU4_FSM_HANG_MSK_ERR_MSK | \
   2375				B_AX_RX_RU3_FSM_HANG_MSK_ERR_MSK | \
   2376				B_AX_RX_RU2_FSM_HANG_MSK_ERR_MSK | \
   2377				B_AX_RX_RU1_FSM_HANG_MSK_ERR_MSK | \
   2378				B_AX_RX_RU0_FSM_HANG_MSK_ERR_MSK | \
   2379				B_AX_RX_GET_NULL_PKT_ERR_MSK)
   2380#define B_AX_RX_ERR_IMR_SET_V1 (B_AX_RXSTS_ENQUE_ORDER_ERR_MSK | \
   2381				B_AX_RXDATA_ENQUE_ORDER_ERR_MSK | \
   2382				B_AX_RX_CSI_ZERO_LEN_ERR_MSK | \
   2383				B_AX_RX_RXSTS_ZERO_LEN_ERR_MSK | \
   2384				B_AX_RX_RU7_ZERO_LEN_ERR_MSK | \
   2385				B_AX_RX_RU6_ZERO_LEN_ERR_MSK | \
   2386				B_AX_RX_RU5_ZERO_LEN_ERR_MSK | \
   2387				B_AX_RX_RU4_ZERO_LEN_ERR_MSK | \
   2388				B_AX_RX_RU3_ZERO_LEN_ERR_MSK | \
   2389				B_AX_RX_RU2_ZERO_LEN_ERR_MSK | \
   2390				B_AX_RX_RU1_ZERO_LEN_ERR_MSK | \
   2391				B_AX_RX_RU0_ZERO_LEN_ERR_MSK | \
   2392				B_AX_RX_F2PCMD_FSM_HANG_MSK_ERR_MSK | \
   2393				B_AX_RX_TXRPT_FSM_HANG_MSK_ERR_MSK | \
   2394				B_AX_RX_CSI_FSM_HANG_MSK_ERR_MSK | \
   2395				B_AX_RX_RXSTS_FSM_HANG_MSK_ERR_MSK | \
   2396				B_AX_RX_RU7_FSM_HANG_MSK_ERR_MSK | \
   2397				B_AX_RX_RU6_FSM_HANG_MSK_ERR_MSK | \
   2398				B_AX_RX_RU5_FSM_HANG_MSK_ERR_MSK | \
   2399				B_AX_RX_RU4_FSM_HANG_MSK_ERR_MSK | \
   2400				B_AX_RX_RU3_FSM_HANG_MSK_ERR_MSK | \
   2401				B_AX_RX_RU2_FSM_HANG_MSK_ERR_MSK | \
   2402				B_AX_RX_RU1_FSM_HANG_MSK_ERR_MSK | \
   2403				B_AX_RX_RU0_FSM_HANG_MSK_ERR_MSK | \
   2404				B_AX_RX_GET_NULL_PKT_ERR_MSK)
   2405
   2406#define R_AX_TX_ERR_FLAG_IMR 0xC870
   2407#define R_AX_TX_ERR_FLAG_IMR_C1 0xE870
   2408#define B_AX_TX_RU0_FSM_HANG_ERR_MSK BIT(31)
   2409#define B_AX_TX_RU1_FSM_HANG_ERR_MSK BIT(30)
   2410#define B_AX_TX_RU2_FSM_HANG_ERR_MSK BIT(29)
   2411#define B_AX_TX_RU3_FSM_HANG_ERR_MSK BIT(28)
   2412#define B_AX_TX_RU4_FSM_HANG_ERR_MSK BIT(27)
   2413#define B_AX_TX_RU5_FSM_HANG_ERR_MSK BIT(26)
   2414#define B_AX_TX_RU6_FSM_HANG_ERR_MSK BIT(25)
   2415#define B_AX_TX_RU7_FSM_HANG_ERR_MSK BIT(24)
   2416#define B_AX_TX_RU8_FSM_HANG_ERR_MSK BIT(23)
   2417#define B_AX_TX_RU9_FSM_HANG_ERR_MSK BIT(22)
   2418#define B_AX_TX_RU10_FSM_HANG_ERR_MSK BIT(21)
   2419#define B_AX_TX_RU11_FSM_HANG_ERR_MSK BIT(20)
   2420#define B_AX_TX_RU12_FSM_HANG_ERR_MSK BIT(19)
   2421#define B_AX_TX_RU13_FSM_HANG_ERR_MSK BIT(18)
   2422#define B_AX_TX_RU14_FSM_HANG_ERR_MSK BIT(17)
   2423#define B_AX_TX_RU15_FSM_HANG_ERR_MSK BIT(16)
   2424#define B_AX_TX_CSI_FSM_HANG_ERR_MSK BIT(15)
   2425#define B_AX_TX_WD_PLD_ID_FSM_HANG_ERR_MSK BIT(14)
   2426#define B_AX_TX_ERR_IMR_CLR_V1 (B_AX_TX_WD_PLD_ID_FSM_HANG_ERR_MSK | \
   2427				B_AX_TX_CSI_FSM_HANG_ERR_MSK | \
   2428				B_AX_TX_RU7_FSM_HANG_ERR_MSK | \
   2429				B_AX_TX_RU6_FSM_HANG_ERR_MSK | \
   2430				B_AX_TX_RU5_FSM_HANG_ERR_MSK | \
   2431				B_AX_TX_RU4_FSM_HANG_ERR_MSK | \
   2432				B_AX_TX_RU3_FSM_HANG_ERR_MSK | \
   2433				B_AX_TX_RU2_FSM_HANG_ERR_MSK | \
   2434				B_AX_TX_RU1_FSM_HANG_ERR_MSK | \
   2435				B_AX_TX_RU0_FSM_HANG_ERR_MSK)
   2436#define B_AX_TX_ERR_IMR_SET_V1 (B_AX_TX_WD_PLD_ID_FSM_HANG_ERR_MSK | \
   2437				B_AX_TX_CSI_FSM_HANG_ERR_MSK | \
   2438				B_AX_TX_RU7_FSM_HANG_ERR_MSK | \
   2439				B_AX_TX_RU6_FSM_HANG_ERR_MSK | \
   2440				B_AX_TX_RU5_FSM_HANG_ERR_MSK | \
   2441				B_AX_TX_RU4_FSM_HANG_ERR_MSK | \
   2442				B_AX_TX_RU3_FSM_HANG_ERR_MSK | \
   2443				B_AX_TX_RU2_FSM_HANG_ERR_MSK | \
   2444				B_AX_TX_RU1_FSM_HANG_ERR_MSK | \
   2445				B_AX_TX_RU0_FSM_HANG_ERR_MSK)
   2446
   2447#define R_AX_TCR0 0xCA00
   2448#define R_AX_TCR0_C1 0xEA00
   2449#define B_AX_TCR_ZLD_NUM_MASK GENMASK(31, 24)
   2450#define B_AX_TCR_UDF_EN BIT(23)
   2451#define B_AX_TCR_UDF_THSD_MASK GENMASK(22, 16)
   2452#define TCR_UDF_THSD 0x6
   2453#define B_AX_TCR_ERRSTEN_MASK GENMASK(15, 10)
   2454#define B_AX_TCR_VHTSIGA1_TXPS BIT(9)
   2455#define B_AX_TCR_PLCP_ERRHDL_EN BIT(8)
   2456#define B_AX_TCR_PADSEL BIT(7)
   2457#define B_AX_TCR_MASK_SIGBCRC BIT(6)
   2458#define B_AX_TCR_SR_VAL15_ALLOW BIT(5)
   2459#define B_AX_TCR_EN_EOF BIT(4)
   2460#define B_AX_TCR_EN_SCRAM_INC BIT(3)
   2461#define B_AX_TCR_EN_20MST BIT(2)
   2462#define B_AX_TCR_CRC BIT(1)
   2463#define B_AX_TCR_DISGCLK BIT(0)
   2464
   2465#define R_AX_TCR1 0xCA04
   2466#define R_AX_TCR1_C1 0xEA04
   2467#define B_AX_TXDFIFO_THRESHOLD GENMASK(31, 28)
   2468#define B_AX_TCR_CCK_LOCK_CLK BIT(27)
   2469#define B_AX_TCR_FORCE_READ_TXDFIFO BIT(26)
   2470#define B_AX_TCR_USTIME GENMASK(23, 16)
   2471#define B_AX_TCR_SMOOTH_VAL BIT(15)
   2472#define B_AX_TCR_SMOOTH_CTRL BIT(14)
   2473#define B_AX_CS_REQ_VAL BIT(13)
   2474#define B_AX_CS_REQ_SEL BIT(12)
   2475#define B_AX_TCR_ZLD_USTIME_AFTERPHYTXON GENMASK(11, 8)
   2476#define B_AX_TCR_TXTIMEOUT GENMASK(7, 0)
   2477
   2478#define R_AX_MD_TSFT_STMP_CTL 0xCA08
   2479#define R_AX_MD_TSFT_STMP_CTL_C1 0xEA08
   2480#define B_AX_TSFT_OFS_MASK GENMASK(31, 16)
   2481#define B_AX_STMP_THSD_MASK GENMASK(15, 8)
   2482#define B_AX_UPD_HGQMD BIT(1)
   2483#define B_AX_UPD_TIMIE BIT(0)
   2484
   2485#define R_AX_PPWRBIT_SETTING 0xCA0C
   2486#define R_AX_PPWRBIT_SETTING_C1 0xEA0C
   2487
   2488#define R_AX_TXD_FIFO_CTRL 0xCA1C
   2489#define R_AX_TXD_FIFO_CTRL_C1 0xEA1C
   2490#define B_AX_NON_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(28, 24)
   2491#define B_AX_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(20, 16)
   2492#define B_AX_TXDFIFO_HIGH_MCS_THRE_MASK GENMASK(15, 12)
   2493#define TXDFIFO_HIGH_MCS_THRE 0x7
   2494#define B_AX_TXDFIFO_LOW_MCS_THRE_MASK GENMASK(11, 8)
   2495#define TXDFIFO_LOW_MCS_THRE  0x7
   2496#define B_AX_HIGH_MCS_PHY_RATE_MASK GENMASK(7, 4)
   2497#define B_AX_BW_PHY_RATE_MASK GENMASK(1, 0)
   2498
   2499#define R_AX_MACTX_DBG_SEL_CNT 0xCA20
   2500#define R_AX_MACTX_DBG_SEL_CNT_C1 0xEA20
   2501#define B_AX_MACTX_MPDU_CNT GENMASK(31, 24)
   2502#define B_AX_MACTX_DMA_CNT GENMASK(23, 16)
   2503#define B_AX_LENGTH_ERR_FLAG_U3 BIT(11)
   2504#define B_AX_LENGTH_ERR_FLAG_U2 BIT(10)
   2505#define B_AX_LENGTH_ERR_FLAG_U1 BIT(9)
   2506#define B_AX_LENGTH_ERR_FLAG_U0 BIT(8)
   2507#define B_AX_DBGSEL_MACTX_MASK GENMASK(5, 0)
   2508
   2509#define R_AX_WMAC_TX_CTRL_DEBUG 0xCAE4
   2510#define R_AX_WMAC_TX_CTRL_DEBUG_C1 0xEAE4
   2511#define B_AX_TX_CTRL_DEBUG_SEL_MASK GENMASK(3, 0)
   2512
   2513#define R_AX_WMAC_TX_INFO0_DEBUG 0xCAE8
   2514#define R_AX_WMAC_TX_INFO0_DEBUG_C1 0xEAE8
   2515#define B_AX_TX_CTRL_INFO_P0_MASK GENMASK(31, 0)
   2516
   2517#define R_AX_WMAC_TX_INFO1_DEBUG 0xCAEC
   2518#define R_AX_WMAC_TX_INFO1_DEBUG_C1 0xEAEC
   2519#define B_AX_TX_CTRL_INFO_P1_MASK GENMASK(31, 0)
   2520
   2521#define R_AX_RSP_CHK_SIG 0xCC00
   2522#define R_AX_RSP_CHK_SIG_C1 0xEC00
   2523#define B_AX_RSP_STATIC_RTS_CHK_SERV_BW_EN BIT(30)
   2524#define B_AX_RSP_TBPPDU_CHK_PWR BIT(29)
   2525#define B_AX_RSP_CHK_BASIC_NAV BIT(21)
   2526#define B_AX_RSP_CHK_INTRA_NAV BIT(20)
   2527#define B_AX_RSP_CHK_TXNAV BIT(19)
   2528#define B_AX_TXDATA_END_PS_OPT BIT(18)
   2529#define B_AX_CHECK_SOUNDING_SEQ BIT(17)
   2530#define B_AX_RXBA_IGNOREA2 BIT(16)
   2531#define B_AX_ACKTO_CCK_MASK GENMASK(15, 8)
   2532#define B_AX_ACKTO_MASK GENMASK(7, 0)
   2533
   2534#define R_AX_TRXPTCL_RESP_0 0xCC04
   2535#define R_AX_TRXPTCL_RESP_0_C1 0xEC04
   2536#define B_AX_WMAC_RESP_STBC_EN BIT(31)
   2537#define B_AX_WMAC_RXFTM_TXACK_SC BIT(30)
   2538#define B_AX_WMAC_RXFTM_TXACKBWEQ BIT(29)
   2539#define B_AX_RSP_CHK_SEC_CCA_80 BIT(28)
   2540#define B_AX_RSP_CHK_SEC_CCA_40 BIT(27)
   2541#define B_AX_RSP_CHK_SEC_CCA_20 BIT(26)
   2542#define B_AX_RSP_CHK_BTCCA BIT(25)
   2543#define B_AX_RSP_CHK_EDCCA BIT(24)
   2544#define B_AX_RSP_CHK_CCA BIT(23)
   2545#define B_AX_WMAC_LDPC_EN BIT(22)
   2546#define B_AX_WMAC_SGIEN BIT(21)
   2547#define B_AX_WMAC_SPLCPEN BIT(20)
   2548#define B_AX_WMAC_BESP_EARLY_TXBA BIT(17)
   2549#define B_AX_WMAC_SPEC_SIFS_OFDM_MASK GENMASK(15, 8)
   2550#define B_AX_WMAC_SPEC_SIFS_CCK_MASK GENMASK(7, 0)
   2551#define WMAC_SPEC_SIFS_OFDM_52A 0x15
   2552#define WMAC_SPEC_SIFS_OFDM_52B 0x11
   2553#define WMAC_SPEC_SIFS_OFDM_52C 0x11
   2554#define WMAC_SPEC_SIFS_CCK	 0xA
   2555
   2556#define R_AX_MAC_LOOPBACK 0xCC20
   2557#define R_AX_MAC_LOOPBACK_C1 0xEC20
   2558#define B_AX_MACLBK_EN BIT(0)
   2559
   2560#define R_AX_WMAC_NAV_CTL 0xCC80
   2561#define R_AX_WMAC_NAV_CTL_C1 0xEC80
   2562#define B_AX_WMAC_NAV_UPPER_EN BIT(26)
   2563#define B_AX_WMAC_0P125US_TIMER_MASK GENMASK(25, 18)
   2564#define B_AX_WMAC_PLCP_UP_NAV_EN BIT(17)
   2565#define B_AX_WMAC_TF_UP_NAV_EN BIT(16)
   2566#define B_AX_WMAC_NAV_UPPER_MASK GENMASK(15, 8)
   2567#define NAV_12MS 0xBC
   2568#define B_AX_WMAC_RTS_RST_DUR_MASK GENMASK(7, 0)
   2569
   2570#define R_AX_RXTRIG_TEST_USER_2 0xCCB0
   2571#define R_AX_RXTRIG_TEST_USER_2_C1 0xECB0
   2572#define B_AX_RXTRIG_MACID_MASK GENMASK(31, 24)
   2573#define B_AX_RXTRIG_RU26_DIS BIT(21)
   2574#define B_AX_RXTRIG_FCSCHK_EN BIT(20)
   2575#define B_AX_RXTRIG_PORT_SEL_MASK GENMASK(19, 17)
   2576#define B_AX_RXTRIG_EN BIT(16)
   2577#define B_AX_RXTRIG_USERINFO_2_MASK GENMASK(15, 0)
   2578
   2579#define R_AX_TRXPTCL_ERROR_INDICA_MASK 0xCCBC
   2580#define R_AX_TRXPTCL_ERROR_INDICA_MASK_C1 0xECBC
   2581#define B_AX_WMAC_MODE BIT(22)
   2582#define B_AX_WMAC_TIMETOUT_THR_MASK GENMASK(21, 16)
   2583#define B_AX_RMAC_FTM BIT(8)
   2584#define B_AX_RMAC_CSI BIT(7)
   2585#define B_AX_TMAC_MIMO_CTRL BIT(6)
   2586#define B_AX_TMAC_RXTB BIT(5)
   2587#define B_AX_TMAC_HWSIGB_GEN BIT(4)
   2588#define B_AX_TMAC_TXPLCP BIT(3)
   2589#define B_AX_TMAC_RESP BIT(2)
   2590#define B_AX_TMAC_TXCTL BIT(1)
   2591#define B_AX_TMAC_MACTX BIT(0)
   2592#define B_AX_TMAC_IMR_CLR_V1 (B_AX_TMAC_MACTX | \
   2593			      B_AX_TMAC_TXCTL | \
   2594			      B_AX_TMAC_RESP | \
   2595			      B_AX_TMAC_TXPLCP | \
   2596			      B_AX_TMAC_HWSIGB_GEN | \
   2597			      B_AX_TMAC_RXTB | \
   2598			      B_AX_TMAC_MIMO_CTRL | \
   2599			      B_AX_RMAC_CSI | \
   2600			      B_AX_RMAC_FTM)
   2601#define B_AX_TMAC_IMR_SET_V1 (B_AX_TMAC_MACTX | \
   2602			      B_AX_TMAC_TXCTL | \
   2603			      B_AX_TMAC_RESP | \
   2604			      B_AX_TMAC_TXPLCP | \
   2605			      B_AX_TMAC_HWSIGB_GEN | \
   2606			      B_AX_TMAC_RXTB | \
   2607			      B_AX_TMAC_MIMO_CTRL | \
   2608			      B_AX_RMAC_FTM)
   2609
   2610#define R_AX_WMAC_TX_TF_INFO_0 0xCCD0
   2611#define R_AX_WMAC_TX_TF_INFO_0_C1 0xECD0
   2612#define B_AX_WMAC_TX_TF_INFO_SEL_MASK GENMASK(2, 0)
   2613
   2614#define R_AX_WMAC_TX_TF_INFO_1 0xCCD4
   2615#define R_AX_WMAC_TX_TF_INFO_1_C1 0xECD4
   2616#define B_AX_WMAC_TX_TF_INFO_P0_MASK GENMASK(31, 0)
   2617
   2618#define R_AX_WMAC_TX_TF_INFO_2 0xCCD8
   2619#define R_AX_WMAC_TX_TF_INFO_2_C1 0xECD8
   2620#define B_AX_WMAC_TX_TF_INFO_P1_MASK GENMASK(31, 0)
   2621
   2622#define R_AX_TMAC_ERR_IMR_ISR 0xCCEC
   2623#define R_AX_TMAC_ERR_IMR_ISR_C1 0xECEC
   2624#define B_AX_TMAC_TXPLCP_ERR_CLR BIT(19)
   2625#define B_AX_TMAC_RESP_ERR_CLR BIT(18)
   2626#define B_AX_TMAC_TXCTL_ERR_CLR BIT(17)
   2627#define B_AX_TMAC_MACTX_ERR_CLR BIT(16)
   2628#define B_AX_TMAC_TXPLCP_ERR BIT(14)
   2629#define B_AX_TMAC_RESP_ERR BIT(13)
   2630#define B_AX_TMAC_TXCTL_ERR BIT(12)
   2631#define B_AX_TMAC_MACTX_ERR BIT(11)
   2632#define B_AX_TMAC_TXPLCP_INT_EN BIT(10)
   2633#define B_AX_TMAC_RESP_INT_EN BIT(9)
   2634#define B_AX_TMAC_TXCTL_INT_EN BIT(8)
   2635#define B_AX_TMAC_MACTX_INT_EN BIT(7)
   2636#define B_AX_WMAC_INT_MODE BIT(6)
   2637#define B_AX_TMAC_TIMETOUT_THR_MASK GENMASK(5, 0)
   2638#define B_AX_TMAC_IMR_CLR (B_AX_TMAC_MACTX_INT_EN | \
   2639			   B_AX_TMAC_TXCTL_INT_EN | \
   2640			   B_AX_TMAC_RESP_INT_EN | \
   2641			   B_AX_TMAC_TXPLCP_INT_EN)
   2642#define B_AX_TMAC_IMR_SET (B_AX_TMAC_MACTX_INT_EN | \
   2643			   B_AX_TMAC_TXCTL_INT_EN | \
   2644			   B_AX_TMAC_RESP_INT_EN | \
   2645			   B_AX_TMAC_TXPLCP_INT_EN)
   2646
   2647#define R_AX_DBGSEL_TRXPTCL 0xCCF4
   2648#define R_AX_DBGSEL_TRXPTCL_C1 0xECF4
   2649#define B_AX_DBGSEL_TRXPTCL_MASK GENMASK(7, 0)
   2650
   2651#define R_AX_PHYINFO_ERR_IMR_V1 0xCCF8
   2652#define R_AX_PHYINFO_ERR_IMR_V1_C1 0xECF8
   2653#define B_AX_PHYINTF_TIMEOUT_THR_MSAK_V1 GENMASK(21, 16)
   2654#define B_AX_CSI_ON_TIMEOUT_EN BIT(5)
   2655#define B_AX_STS_ON_TIMEOUT_EN BIT(4)
   2656#define B_AX_DATA_ON_TIMEOUT_EN BIT(3)
   2657#define B_AX_OFDM_CCA_TIMEOUT_EN BIT(2)
   2658#define B_AX_CCK_CCA_TIMEOUT_EN BIT(1)
   2659#define B_AX_PHY_TXON_TIMEOUT_EN BIT(0)
   2660#define B_AX_PHYINFO_IMR_CLR_V1 (B_AX_PHY_TXON_TIMEOUT_EN | \
   2661				 B_AX_CCK_CCA_TIMEOUT_EN | \
   2662				 B_AX_OFDM_CCA_TIMEOUT_EN | \
   2663				 B_AX_DATA_ON_TIMEOUT_EN | \
   2664				 B_AX_STS_ON_TIMEOUT_EN | \
   2665				 B_AX_CSI_ON_TIMEOUT_EN)
   2666#define B_AX_PHYINFO_IMR_SET_V1 (B_AX_PHY_TXON_TIMEOUT_EN | \
   2667				 B_AX_CCK_CCA_TIMEOUT_EN | \
   2668				 B_AX_OFDM_CCA_TIMEOUT_EN | \
   2669				 B_AX_DATA_ON_TIMEOUT_EN | \
   2670				 B_AX_STS_ON_TIMEOUT_EN | \
   2671				 B_AX_CSI_ON_TIMEOUT_EN)
   2672
   2673#define R_AX_PHYINFO_ERR_IMR 0xCCFC
   2674#define R_AX_PHYINFO_ERR_IMR_C1 0xECFC
   2675#define B_AX_CSI_ON_TIMEOUT BIT(29)
   2676#define B_AX_STS_ON_TIMEOUT BIT(28)
   2677#define B_AX_DATA_ON_TIMEOUT BIT(27)
   2678#define B_AX_OFDM_CCA_TIMEOUT BIT(26)
   2679#define B_AX_CCK_CCA_TIMEOUT BIT(25)
   2680#define B_AXC_PHY_TXON_TIMEOUT BIT(24)
   2681#define B_AX_CSI_ON_TIMEOUT_INT_EN BIT(21)
   2682#define B_AX_STS_ON_TIMEOUT_INT_EN BIT(20)
   2683#define B_AX_DATA_ON_TIMEOUT_INT_EN BIT(19)
   2684#define B_AX_OFDM_CCA_TIMEOUT_INT_EN BIT(18)
   2685#define B_AX_CCK_CCA_TIMEOUT_INT_EN BIT(17)
   2686#define B_AX_PHY_TXON_TIMEOUT_INT_EN BIT(16)
   2687#define B_AX_PHYINTF_TIMEOUT_THR_MSAK GENMASK(5, 0)
   2688#define B_AX_PHYINFO_IMR_EN_ALL (B_AX_PHY_TXON_TIMEOUT_INT_EN | \
   2689				 B_AX_CCK_CCA_TIMEOUT_INT_EN | \
   2690				 B_AX_OFDM_CCA_TIMEOUT_INT_EN | \
   2691				 B_AX_DATA_ON_TIMEOUT_INT_EN | \
   2692				 B_AX_STS_ON_TIMEOUT_INT_EN | \
   2693				 B_AX_CSI_ON_TIMEOUT_INT_EN)
   2694
   2695#define R_AX_PHYINFO_ERR_ISR 0xCCFC
   2696#define R_AX_PHYINFO_ERR_ISR_C1 0xECFC
   2697
   2698#define R_AX_BFMER_CTRL_0 0xCD78
   2699#define R_AX_BFMER_CTRL_0_C1 0xED78
   2700#define B_AX_BFMER_HE_CSI_OFFSET_MASK GENMASK(31, 24)
   2701#define B_AX_BFMER_VHT_CSI_OFFSET_MASK GENMASK(23, 16)
   2702#define B_AX_BFMER_HT_CSI_OFFSET_MASK GENMASK(15, 8)
   2703#define B_AX_BFMER_NDP_BFEN BIT(2)
   2704#define B_AX_BFMER_VHT_BFPRT_CHK BIT(0)
   2705
   2706#define R_AX_BFMEE_RESP_OPTION 0xCD80
   2707#define R_AX_BFMEE_RESP_OPTION_C1 0xED80
   2708#define B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK GENMASK(31, 24)
   2709#define B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK GENMASK(23, 20)
   2710#define B_AX_MU_BFRPTSEG_SEL_MASK GENMASK(18, 17)
   2711#define B_AX_BFMEE_NDP_RXSTDBY_SEL BIT(16)
   2712#define BFRP_RX_STANDBY_TIMER		0x0
   2713#define NDP_RX_STANDBY_TIMER		0xFF
   2714#define B_AX_BFMEE_HE_NDPA_EN BIT(2)
   2715#define B_AX_BFMEE_VHT_NDPA_EN BIT(1)
   2716#define B_AX_BFMEE_HT_NDPA_EN BIT(0)
   2717
   2718#define R_AX_TRXPTCL_RESP_CSI_CTRL_0 0xCD88
   2719#define R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 0xED88
   2720#define R_AX_TRXPTCL_RESP_CSI_CTRL_1 0xCD94
   2721#define R_AX_TRXPTCL_RESP_CSI_CTRL_1_C1 0xED94
   2722#define B_AX_BFMEE_CSISEQ_SEL BIT(29)
   2723#define B_AX_BFMEE_BFPARAM_SEL BIT(28)
   2724#define B_AX_BFMEE_OFDM_LEN_TH_MASK GENMASK(27, 24)
   2725#define B_AX_BFMEE_BF_PORT_SEL BIT(23)
   2726#define B_AX_BFMEE_USE_NSTS BIT(22)
   2727#define B_AX_BFMEE_CSI_RATE_FB_EN BIT(21)
   2728#define B_AX_BFMEE_CSI_GID_SEL BIT(20)
   2729#define B_AX_BFMEE_CSI_RSC_MASK GENMASK(19, 18)
   2730#define B_AX_BFMEE_CSI_FORCE_RETE_EN BIT(17)
   2731#define B_AX_BFMEE_CSI_USE_NDPARATE BIT(16)
   2732#define B_AX_BFMEE_CSI_WITHHTC_EN BIT(15)
   2733#define B_AX_BFMEE_CSIINFO0_BF_EN BIT(14)
   2734#define B_AX_BFMEE_CSIINFO0_STBC_EN BIT(13)
   2735#define B_AX_BFMEE_CSIINFO0_LDPC_EN BIT(12)
   2736#define B_AX_BFMEE_CSIINFO0_CS_MASK GENMASK(11, 10)
   2737#define B_AX_BFMEE_CSIINFO0_CB_MASK GENMASK(9, 8)
   2738#define B_AX_BFMEE_CSIINFO0_NG_MASK GENMASK(7, 6)
   2739#define B_AX_BFMEE_CSIINFO0_NR_MASK GENMASK(5, 3)
   2740#define B_AX_BFMEE_CSIINFO0_NC_MASK GENMASK(2, 0)
   2741
   2742#define R_AX_TRXPTCL_RESP_CSI_RRSC 0xCD8C
   2743#define R_AX_TRXPTCL_RESP_CSI_RRSC_C1 0xED8C
   2744#define CSI_RRSC_BMAP 0x29292911
   2745
   2746#define R_AX_TRXPTCL_RESP_CSI_RATE 0xCD90
   2747#define R_AX_TRXPTCL_RESP_CSI_RATE_C1 0xED90
   2748#define B_AX_BFMEE_HE_CSI_RATE_MASK GENMASK(22, 16)
   2749#define B_AX_BFMEE_VHT_CSI_RATE_MASK GENMASK(14, 8)
   2750#define B_AX_BFMEE_HT_CSI_RATE_MASK GENMASK(6, 0)
   2751#define CSI_INIT_RATE_HE		0x3
   2752#define CSI_INIT_RATE_VHT		0x3
   2753#define CSI_INIT_RATE_HT		0x3
   2754
   2755#define R_AX_RCR 0xCE00
   2756#define R_AX_RCR_C1 0xEE00
   2757#define B_AX_STOP_RX_IN BIT(11)
   2758#define B_AX_DRV_INFO_SIZE_MASK GENMASK(10, 8)
   2759#define B_AX_CH_EN_MASK GENMASK(3, 0)
   2760
   2761#define R_AX_DLK_PROTECT_CTL 0xCE02
   2762#define R_AX_DLK_PROTECT_CTL_C1 0xEE02
   2763#define B_AX_RX_DLK_CCA_TIME_MASK GENMASK(15, 8)
   2764#define B_AX_RX_DLK_DATA_TIME_MASK GENMASK(7, 4)
   2765
   2766#define R_AX_PLCP_HDR_FLTR 0xCE04
   2767#define R_AX_PLCP_HDR_FLTR_C1 0xEE04
   2768#define B_AX_DIS_CHK_MIN_LEN BIT(8)
   2769#define B_AX_HE_SIGB_CRC_CHK BIT(6)
   2770#define B_AX_VHT_MU_SIGB_CRC_CHK BIT(5)
   2771#define B_AX_VHT_SU_SIGB_CRC_CHK BIT(4)
   2772#define B_AX_SIGA_CRC_CHK BIT(3)
   2773#define B_AX_LSIG_PARITY_CHK_EN BIT(2)
   2774#define B_AX_CCK_SIG_CHK BIT(1)
   2775#define B_AX_CCK_CRC_CHK BIT(0)
   2776
   2777#define R_AX_RX_FLTR_OPT 0xCE20
   2778#define R_AX_RX_FLTR_OPT_C1 0xEE20
   2779#define B_AX_UID_FILTER_MASK GENMASK(31, 24)
   2780#define B_AX_UNSPT_FILTER_SH 22
   2781#define B_AX_UNSPT_FILTER_MASK GENMASK(23, 22)
   2782#define B_AX_RX_MPDU_MAX_LEN_MASK GENMASK(21, 16)
   2783#define B_AX_RX_MPDU_MAX_LEN_SIZE 0x3f
   2784#define B_AX_A_FTM_REQ BIT(14)
   2785#define B_AX_A_ERR_PKT BIT(13)
   2786#define B_AX_A_UNSUP_PKT BIT(12)
   2787#define B_AX_A_CRC32_ERR BIT(11)
   2788#define B_AX_A_PWR_MGNT BIT(10)
   2789#define B_AX_A_BCN_CHK_RULE_MASK GENMASK(9, 8)
   2790#define B_AX_A_BCN_CHK_EN BIT(7)
   2791#define B_AX_A_MC_LIST_CAM_MATCH BIT(6)
   2792#define B_AX_A_BC_CAM_MATCH BIT(5)
   2793#define B_AX_A_UC_CAM_MATCH BIT(4)
   2794#define B_AX_A_MC BIT(3)
   2795#define B_AX_A_BC BIT(2)
   2796#define B_AX_A_A1_MATCH BIT(1)
   2797#define B_AX_SNIFFER_MODE BIT(0)
   2798#define DEFAULT_AX_RX_FLTR (B_AX_A_A1_MATCH | B_AX_A_BC | B_AX_A_MC |	       \
   2799			    B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH |	       \
   2800			    B_AX_A_PWR_MGNT | B_AX_A_FTM_REQ |		       \
   2801			    u32_encode_bits(3, B_AX_UID_FILTER_MASK) |	       \
   2802			    B_AX_A_BCN_CHK_EN)
   2803#define B_AX_RX_FLTR_CFG_MASK ((u32)~B_AX_RX_MPDU_MAX_LEN_MASK)
   2804
   2805#define R_AX_CTRL_FLTR 0xCE24
   2806#define R_AX_CTRL_FLTR_C1 0xEE24
   2807#define R_AX_MGNT_FLTR 0xCE28
   2808#define R_AX_MGNT_FLTR_C1 0xEE28
   2809#define R_AX_DATA_FLTR 0xCE2C
   2810#define R_AX_DATA_FLTR_C1 0xEE2C
   2811#define RX_FLTR_FRAME_DROP	0x00000000
   2812#define RX_FLTR_FRAME_TO_HOST	0x55555555
   2813#define RX_FLTR_FRAME_TO_WLCPU	0xAAAAAAAA
   2814
   2815#define R_AX_ADDR_CAM_CTRL 0xCE34
   2816#define R_AX_ADDR_CAM_CTRL_C1 0xEE34
   2817#define B_AX_ADDR_CAM_RANGE_MASK GENMASK(23, 16)
   2818#define B_AX_ADDR_CAM_CMPLIMT_MASK GENMASK(15, 12)
   2819#define B_AX_ADDR_CAM_CLR BIT(8)
   2820#define B_AX_ADDR_CAM_A2_B0_CHK BIT(2)
   2821#define B_AX_ADDR_CAM_SRCH_PERPKT BIT(1)
   2822#define B_AX_ADDR_CAM_EN BIT(0)
   2823
   2824#define R_AX_RESPBA_CAM_CTRL 0xCE3C
   2825#define R_AX_RESPBA_CAM_CTRL_C1 0xEE3C
   2826#define B_AX_SSN_SEL BIT(2)
   2827#define B_AX_BACAM_RST_MASK GENMASK(1, 0)
   2828#define S_AX_BACAM_RST_ALL 2
   2829
   2830#define R_AX_PPDU_STAT 0xCE40
   2831#define R_AX_PPDU_STAT_C1 0xEE40
   2832#define B_AX_PPDU_STAT_RPT_TRIG BIT(8)
   2833#define B_AX_PPDU_STAT_RPT_CRC32 BIT(5)
   2834#define B_AX_PPDU_STAT_RPT_A1M BIT(4)
   2835#define B_AX_APP_PLCP_HDR_RPT BIT(3)
   2836#define B_AX_APP_RX_CNT_RPT BIT(2)
   2837#define B_AX_APP_MAC_INFO_RPT BIT(1)
   2838#define B_AX_PPDU_STAT_RPT_EN BIT(0)
   2839
   2840#define R_AX_RX_SR_CTRL 0xCE4A
   2841#define R_AX_RX_SR_CTRL_C1 0xEE4A
   2842#define B_AX_SR_EN BIT(0)
   2843
   2844#define R_AX_CSIRPT_OPTION 0xCE64
   2845#define R_AX_CSIRPT_OPTION_C1 0xEE64
   2846#define B_AX_CSIPRT_HESU_AID_EN BIT(25)
   2847#define B_AX_CSIPRT_VHTSU_AID_EN BIT(24)
   2848
   2849#define R_AX_RX_STATE_MONITOR 0xCEF0
   2850#define R_AX_RX_STATE_MONITOR_C1 0xEEF0
   2851#define B_AX_RX_STATE_MONITOR_MASK GENMASK(31, 0)
   2852#define B_AX_STATE_CUR_MASK GENMASK(31, 16)
   2853#define B_AX_STATE_NXT_MASK GENMASK(13, 8)
   2854#define B_AX_STATE_UPD BIT(7)
   2855#define B_AX_STATE_SEL_MASK GENMASK(4, 0)
   2856
   2857#define R_AX_RMAC_ERR_ISR 0xCEF4
   2858#define R_AX_RMAC_ERR_ISR_C1 0xEEF4
   2859#define B_AX_RXERR_INTPS_EN BIT(31)
   2860#define B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN BIT(19)
   2861#define B_AX_RMAC_RX_TIMEOUT_INT_EN BIT(18)
   2862#define B_AX_RMAC_CSI_TIMEOUT_INT_EN BIT(17)
   2863#define B_AX_RMAC_DATA_ON_TIMEOUT_INT_EN BIT(16)
   2864#define B_AX_RMAC_CCA_TIMEOUT_INT_EN BIT(15)
   2865#define B_AX_RMAC_DMA_TIMEOUT_INT_EN BIT(14)
   2866#define B_AX_RMAC_DATA_ON_TO_IDLE_TIMEOUT_INT_EN BIT(13)
   2867#define B_AX_RMAC_CCA_TO_IDLE_TIMEOUT_INT_EN BIT(12)
   2868#define B_AX_RMAC_RX_CSI_TIMEOUT_FLAG BIT(7)
   2869#define B_AX_RMAC_RX_TIMEOUT_FLAG BIT(6)
   2870#define B_AX_BMAC_CSI_TIMEOUT_FLAG BIT(5)
   2871#define B_AX_BMAC_DATA_ON_TIMEOUT_FLAG BIT(4)
   2872#define B_AX_BMAC_CCA_TIMEOUT_FLAG BIT(3)
   2873#define B_AX_BMAC_DMA_TIMEOUT_FLAG BIT(2)
   2874#define B_AX_BMAC_DATA_ON_TO_IDLE_TIMEOUT_FLAG BIT(1)
   2875#define B_AX_BMAC_CCA_TO_IDLE_TIMEOUT_FLAG BIT(0)
   2876#define B_AX_RMAC_IMR_CLR (B_AX_RMAC_CCA_TO_IDLE_TIMEOUT_INT_EN | \
   2877			   B_AX_RMAC_DATA_ON_TO_IDLE_TIMEOUT_INT_EN | \
   2878			   B_AX_RMAC_DMA_TIMEOUT_INT_EN | \
   2879			   B_AX_RMAC_CCA_TIMEOUT_INT_EN | \
   2880			   B_AX_RMAC_DATA_ON_TIMEOUT_INT_EN | \
   2881			   B_AX_RMAC_CSI_TIMEOUT_INT_EN | \
   2882			   B_AX_RMAC_RX_TIMEOUT_INT_EN | \
   2883			   B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN)
   2884#define B_AX_RMAC_IMR_SET (B_AX_RMAC_DMA_TIMEOUT_INT_EN | \
   2885			   B_AX_RMAC_CSI_TIMEOUT_INT_EN | \
   2886			   B_AX_RMAC_RX_TIMEOUT_INT_EN | \
   2887			   B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN)
   2888
   2889#define R_AX_RX_ERR_IMR 0xCEF8
   2890#define R_AX_RX_ERR_IMR_C1 0xEEF8
   2891#define B_AX_RX_ERR_TRIG_ACT_TO_MSK BIT(9)
   2892#define B_AX_RX_ERR_STS_ACT_TO_MSK BIT(8)
   2893#define B_AX_RX_ERR_CSI_ACT_TO_MSK BIT(7)
   2894#define B_AX_RX_ERR_ACT_TO_MSK BIT(6)
   2895#define B_AX_CSI_DATAON_ASSERT_TO_MSK BIT(5)
   2896#define B_AX_DATAON_ASSERT_TO_MSK BIT(4)
   2897#define B_AX_CCA_ASSERT_TO_MSK BIT(3)
   2898#define B_AX_RX_ERR_DMA_TO_MSK BIT(2)
   2899#define B_AX_RX_ERR_DATA_TO_MSK BIT(1)
   2900#define B_AX_RX_ERR_CCA_TO_MSK BIT(0)
   2901#define B_AX_RMAC_IMR_CLR_V1 (B_AX_RX_ERR_CCA_TO_MSK | \
   2902			      B_AX_RX_ERR_DATA_TO_MSK | \
   2903			      B_AX_RX_ERR_DMA_TO_MSK | \
   2904			      B_AX_CCA_ASSERT_TO_MSK | \
   2905			      B_AX_DATAON_ASSERT_TO_MSK | \
   2906			      B_AX_CSI_DATAON_ASSERT_TO_MSK | \
   2907			      B_AX_RX_ERR_ACT_TO_MSK | \
   2908			      B_AX_RX_ERR_CSI_ACT_TO_MSK | \
   2909			      B_AX_RX_ERR_STS_ACT_TO_MSK | \
   2910			      B_AX_RX_ERR_TRIG_ACT_TO_MSK)
   2911#define B_AX_RMAC_IMR_SET_V1 (B_AX_RX_ERR_CCA_TO_MSK | \
   2912			      B_AX_RX_ERR_DATA_TO_MSK | \
   2913			      B_AX_RX_ERR_DMA_TO_MSK | \
   2914			      B_AX_CCA_ASSERT_TO_MSK | \
   2915			      B_AX_DATAON_ASSERT_TO_MSK | \
   2916			      B_AX_CSI_DATAON_ASSERT_TO_MSK | \
   2917			      B_AX_RX_ERR_ACT_TO_MSK | \
   2918			      B_AX_RX_ERR_CSI_ACT_TO_MSK | \
   2919			      B_AX_RX_ERR_STS_ACT_TO_MSK | \
   2920			      B_AX_RX_ERR_TRIG_ACT_TO_MSK)
   2921
   2922#define R_AX_RMAC_PLCP_MON 0xCEF8
   2923#define R_AX_RMAC_PLCP_MON_C1 0xEEF8
   2924#define B_AX_RMAC_PLCP_MON_MASK GENMASK(31, 0)
   2925#define B_AX_PCLP_MON_SEL_MASK GENMASK(31, 28)
   2926#define B_AX_PCLP_MON_CONT_MASK GENMASK(27, 0)
   2927
   2928#define R_AX_RX_DEBUG_SELECT 0xCEFC
   2929#define R_AX_RX_DEBUG_SELECT_C1 0xEEFC
   2930#define B_AX_DEBUG_SEL_MASK GENMASK(7, 0)
   2931
   2932#define R_AX_PWR_RATE_CTRL 0xD200
   2933#define R_AX_PWR_RATE_CTRL_C1 0xF200
   2934#define B_AX_FORCE_PWR_BY_RATE_EN BIT(9)
   2935#define B_AX_FORCE_PWR_BY_RATE_VALUE_MASK GENMASK(8, 0)
   2936
   2937#define R_AX_PWR_RATE_OFST_CTRL 0xD204
   2938#define R_AX_PWR_COEXT_CTRL 0xD220
   2939#define B_AX_TXAGC_BT_EN BIT(1)
   2940#define B_AX_TXAGC_BT_MASK GENMASK(11, 3)
   2941
   2942#define R_AX_PWR_UL_CTRL0 0xD240
   2943#define R_AX_PWR_UL_CTRL2 0xD248
   2944#define B_AX_PWR_UL_CFO_MASK GENMASK(2, 0)
   2945#define B_AX_PWR_UL_CTRL2_MASK 0x07700007
   2946#define R_AX_PWR_UL_TB_CTRL 0xD288
   2947#define B_AX_PWR_UL_TB_CTRL_EN BIT(31)
   2948#define R_AX_PWR_UL_TB_1T 0xD28C
   2949#define B_AX_PWR_UL_TB_1T_MASK GENMASK(4, 0)
   2950#define B_AX_PWR_UL_TB_1T_V1_MASK GENMASK(7, 0)
   2951#define R_AX_PWR_UL_TB_2T 0xD290
   2952#define B_AX_PWR_UL_TB_2T_MASK GENMASK(4, 0)
   2953#define B_AX_PWR_UL_TB_2T_V1_MASK GENMASK(7, 0)
   2954#define R_AX_PWR_BY_RATE_TABLE0 0xD2C0
   2955#define R_AX_PWR_BY_RATE_TABLE10 0xD2E8
   2956#define R_AX_PWR_BY_RATE R_AX_PWR_BY_RATE_TABLE0
   2957#define R_AX_PWR_BY_RATE_MAX R_AX_PWR_BY_RATE_TABLE10
   2958#define R_AX_PWR_LMT_TABLE0 0xD2EC
   2959#define R_AX_PWR_LMT_TABLE19 0xD338
   2960#define R_AX_PWR_LMT R_AX_PWR_LMT_TABLE0
   2961#define R_AX_PWR_LMT_MAX R_AX_PWR_LMT_TABLE19
   2962#define R_AX_PWR_RU_LMT_TABLE0 0xD33C
   2963#define R_AX_PWR_RU_LMT_TABLE11 0xD368
   2964#define R_AX_PWR_RU_LMT R_AX_PWR_RU_LMT_TABLE0
   2965#define R_AX_PWR_RU_LMT_MAX R_AX_PWR_RU_LMT_TABLE11
   2966#define R_AX_PWR_MACID_LMT_TABLE0 0xD36C
   2967#define R_AX_PWR_MACID_LMT_TABLE127 0xD568
   2968
   2969#define R_AX_PATH_COM0 0xD800
   2970#define AX_PATH_COM0_DFVAL 0x00000000
   2971#define AX_PATH_COM0_PATHA 0x08888880
   2972#define AX_PATH_COM0_PATHB 0x11111100
   2973#define AX_PATH_COM0_PATHAB 0x19999980
   2974#define R_AX_PATH_COM1 0xD804
   2975#define AX_PATH_COM1_DFVAL 0x00000000
   2976#define AX_PATH_COM1_PATHA 0x11111111
   2977#define AX_PATH_COM1_PATHB 0x22222222
   2978#define AX_PATH_COM1_PATHAB 0x33333333
   2979#define R_AX_PATH_COM2 0xD808
   2980#define AX_PATH_COM2_DFVAL 0x00000000
   2981#define AX_PATH_COM2_PATHA 0x01209111
   2982#define AX_PATH_COM2_PATHB 0x01209222
   2983#define AX_PATH_COM2_PATHAB 0x01209333
   2984#define R_AX_PATH_COM3 0xD80C
   2985#define AX_PATH_COM3_DFVAL 0x49249249
   2986#define R_AX_PATH_COM4 0xD810
   2987#define AX_PATH_COM4_DFVAL 0x1C9C9C49
   2988#define R_AX_PATH_COM5 0xD814
   2989#define AX_PATH_COM5_DFVAL 0x39393939
   2990#define R_AX_PATH_COM6 0xD818
   2991#define AX_PATH_COM6_DFVAL 0x39393939
   2992#define R_AX_PATH_COM7 0xD81C
   2993#define AX_PATH_COM7_DFVAL 0x39393939
   2994#define AX_PATH_COM7_PATHA 0x39393939
   2995#define AX_PATH_COM7_PATHB 0x39383939
   2996#define AX_PATH_COM7_PATHAB 0x39393939
   2997#define R_AX_PATH_COM8 0xD820
   2998#define AX_PATH_COM8_DFVAL 0x00000000
   2999#define AX_PATH_COM8_PATHA 0x00003939
   3000#define AX_PATH_COM8_PATHB 0x00003938
   3001#define AX_PATH_COM8_PATHAB 0x00003939
   3002#define R_AX_PATH_COM9 0xD824
   3003#define AX_PATH_COM9_DFVAL 0x000007C0
   3004#define R_AX_PATH_COM10 0xD828
   3005#define AX_PATH_COM10_DFVAL 0xE0000000
   3006#define R_AX_PATH_COM11 0xD82C
   3007#define AX_PATH_COM11_DFVAL 0x00000000
   3008#define R_P80_AT_HIGH_FREQ_BB_WRP 0xD848
   3009#define B_P80_AT_HIGH_FREQ_BB_WRP BIT(28)
   3010#define R_AX_TSSI_CTRL_HEAD 0xD908
   3011#define R_AX_BANDEDGE_CFG 0xD94C
   3012#define B_AX_BANDEDGE_CFG_IDX_MASK GENMASK(31, 30)
   3013#define R_AX_TSSI_CTRL_TAIL 0xD95C
   3014
   3015#define R_AX_TXPWR_IMR 0xD9E0
   3016#define R_AX_TXPWR_IMR_C1 0xF9E0
   3017#define R_AX_TXPWR_ISR 0xD9E4
   3018#define R_AX_TXPWR_ISR_C1 0xF9E4
   3019
   3020#define R_AX_BTC_CFG 0xDA00
   3021#define B_AX_BTC_EN BIT(31)
   3022#define B_AX_EN_EXT_BT_PINMUX BIT(29)
   3023#define B_AX_BTC_RST BIT(28)
   3024#define B_AX_BTC_DBG_SRC_SEL BIT(27)
   3025#define B_AX_BTC_MODE_MASK GENMASK(25, 24)
   3026#define B_AX_INV_WL_ACT2 BIT(17)
   3027#define B_AX_BTG_LNA1_GAIN_SEL BIT(16)
   3028#define B_AX_COEX_DLY_CLK_MASK GENMASK(15, 8)
   3029#define B_AX_IGN_GNT_BT2_RX BIT(7)
   3030#define B_AX_IGN_GNT_BT2_TX BIT(6)
   3031#define B_AX_IGN_GNT_BT2 BIT(5)
   3032#define B_AX_BTC_DBG_SEL_MASK GENMASK(4, 3)
   3033#define B_AX_DIS_BTC_CLK_G BIT(2)
   3034#define B_AX_GNT_WL_RX_CTRL BIT(1)
   3035#define B_AX_WL_SRC BIT(0)
   3036
   3037#define R_AX_RTK_MODE_CFG_V1 0xDA04
   3038#define R_AX_RTK_MODE_CFG_V1_C1 0xFA04
   3039#define B_AX_BT_BLE_EN_V1 BIT(24)
   3040#define B_AX_BT_ULTRA_EN BIT(16)
   3041#define B_AX_BT_L_RX_ULTRA_MASK GENMASK(15, 14)
   3042#define B_AX_BT_L_TX_ULTRA_MASK GENMASK(13, 12)
   3043#define B_AX_BT_H_RX_ULTRA_MASK GENMASK(11, 10)
   3044#define B_AX_BT_H_TX_ULTRA_MASK GENMASK(9, 8)
   3045#define B_AX_SAMPLE_CLK_MASK GENMASK(7, 0)
   3046
   3047#define R_AX_WL_PRI_MSK 0xDA10
   3048#define B_AX_PTA_WL_PRI_MASK_BCNQ BIT(8)
   3049
   3050#define R_AX_BT_CNT_CFG 0xDA10
   3051#define R_AX_BT_CNT_CFG_C1 0xFA10
   3052#define B_AX_BT_CNT_RST_V1 BIT(1)
   3053#define B_AX_BT_CNT_EN BIT(0)
   3054
   3055#define R_BTC_BT_CNT_HIGH 0xDA14
   3056#define R_BTC_BT_CNT_LOW 0xDA18
   3057
   3058#define R_AX_BTC_FUNC_EN 0xDA20
   3059#define R_AX_BTC_FUNC_EN_C1 0xFA20
   3060#define B_AX_PTA_WL_TX_EN BIT(1)
   3061#define B_AX_PTA_EDCCA_EN BIT(0)
   3062
   3063#define R_BTC_COEX_WL_REQ 0xDA24
   3064#define B_BTC_TX_BCN_HI BIT(22)
   3065#define B_BTC_RSP_ACK_HI BIT(10)
   3066
   3067#define R_BTC_BREAK_TABLE 0xDA2C
   3068#define BTC_BREAK_PARAM 0xf0ffffff
   3069
   3070#define R_BTC_BT_COEX_MSK_TABLE 0xDA30
   3071#define B_BTC_PRI_MASK_TX_RESP_V1 BIT(3)
   3072
   3073#define R_AX_BT_COEX_CFG_2 0xDA34
   3074#define R_AX_BT_COEX_CFG_2_C1 0xFA34
   3075#define B_AX_GNT_BT_BYPASS_PRIORITY BIT(12)
   3076#define B_AX_GNT_BT_POLARITY BIT(8)
   3077#define B_AX_TIMER_MASK GENMASK(7, 0)
   3078#define MAC_AX_CSR_RATE 80
   3079
   3080#define R_AX_CSR_MODE 0xDA40
   3081#define R_AX_CSR_MODE_C1 0xFA40
   3082#define B_AX_BT_CNT_RST BIT(16)
   3083#define B_AX_BT_STAT_DELAY_MASK GENMASK(15, 12)
   3084#define MAC_AX_CSR_DELAY 0
   3085#define B_AX_BT_TRX_INIT_DETECT_MASK GENMASK(11, 8)
   3086#define MAC_AX_CSR_TRX_TO 4
   3087#define B_AX_BT_PRI_DETECT_TO_MASK GENMASK(7, 4)
   3088#define MAC_AX_CSR_PRI_TO 5
   3089#define B_AX_WL_ACT_MSK BIT(3)
   3090#define B_AX_STATIS_BT_EN BIT(2)
   3091#define B_AX_WL_ACT_MASK_ENABLE BIT(1)
   3092#define B_AX_ENHANCED_BT BIT(0)
   3093
   3094#define R_AX_BT_BREAK_TABLE 0xDA44
   3095
   3096#define R_AX_BT_STAST_HIGH 0xDA44
   3097#define B_AX_STATIS_BT_HI_RX_MASK GENMASK(31, 16)
   3098#define B_AX_STATIS_BT_HI_TX_MASK GENMASK(15, 0)
   3099#define R_AX_BT_STAST_LOW 0xDA48
   3100#define B_AX_STATIS_BT_LO_TX_1_MASK GENMASK(15, 0)
   3101#define B_AX_STATIS_BT_LO_RX_1_MASK GENMASK(31, 16)
   3102
   3103#define R_AX_GNT_SW_CTRL 0xDA48
   3104#define R_AX_GNT_SW_CTRL_C1 0xFA48
   3105#define B_AX_WL_ACT2_VAL BIT(21)
   3106#define B_AX_WL_ACT2_SWCTRL BIT(20)
   3107#define B_AX_WL_ACT_VAL BIT(19)
   3108#define B_AX_WL_ACT_SWCTRL BIT(18)
   3109#define B_AX_GNT_BT_RX_VAL BIT(17)
   3110#define B_AX_GNT_BT_RX_SWCTRL BIT(16)
   3111#define B_AX_GNT_BT_TX_VAL BIT(15)
   3112#define B_AX_GNT_BT_TX_SWCTRL BIT(14)
   3113#define B_AX_GNT_WL_RX_VAL BIT(13)
   3114#define B_AX_GNT_WL_RX_SWCTRL BIT(12)
   3115#define B_AX_GNT_WL_TX_VAL BIT(11)
   3116#define B_AX_GNT_WL_TX_SWCTRL BIT(10)
   3117#define B_AX_GNT_BT_RFC_S1_VAL BIT(9)
   3118#define B_AX_GNT_BT_RFC_S1_SWCTRL BIT(8)
   3119#define B_AX_GNT_WL_RFC_S1_VAL BIT(7)
   3120#define B_AX_GNT_WL_RFC_S1_SWCTRL BIT(6)
   3121#define B_AX_GNT_BT_RFC_S0_VAL BIT(5)
   3122#define B_AX_GNT_BT_RFC_S0_SWCTRL BIT(4)
   3123#define B_AX_GNT_WL_RFC_S0_VAL BIT(3)
   3124#define B_AX_GNT_WL_RFC_S0_SWCTRL BIT(2)
   3125#define B_AX_GNT_WL_BB_VAL BIT(1)
   3126#define B_AX_GNT_WL_BB_SWCTRL BIT(0)
   3127
   3128#define R_AX_TDMA_MODE 0xDA4C
   3129#define R_AX_TDMA_MODE_C1 0xFA4C
   3130#define B_AX_R_BT_CMD_RPT_MASK GENMASK(31, 16)
   3131#define B_AX_R_RPT_FROM_BT_MASK GENMASK(15, 8)
   3132#define B_AX_BT_HID_ISR_SET_MASK GENMASK(7, 6)
   3133#define B_AX_TDMA_BT_START_NOTIFY BIT(5)
   3134#define B_AX_ENABLE_TDMA_FW_MODE BIT(4)
   3135#define B_AX_ENABLE_PTA_TDMA_MODE BIT(3)
   3136#define B_AX_ENABLE_COEXIST_TAB_IN_TDMA BIT(2)
   3137#define B_AX_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA BIT(1)
   3138#define B_AX_RTK_BT_ENABLE BIT(0)
   3139
   3140#define R_AX_BT_COEX_CFG_5 0xDA6C
   3141#define R_AX_BT_COEX_CFG_5_C1 0xFA6C
   3142#define B_AX_BT_TIME_MASK GENMASK(31, 6)
   3143#define B_AX_BT_RPT_SAMPLE_RATE_MASK GENMASK(5, 0)
   3144#define MAC_AX_RTK_RATE 5
   3145
   3146#define R_AX_LTE_CTRL 0xDAF0
   3147#define R_AX_LTE_WDATA 0xDAF4
   3148#define R_AX_LTE_RDATA 0xDAF8
   3149
   3150#define R_AX_MACID_ANT_TABLE 0xDC00
   3151#define R_AX_MACID_ANT_TABLE_LAST 0xDDFC
   3152
   3153#define CMAC1_START_ADDR 0xE000
   3154#define CMAC1_END_ADDR 0xFFFF
   3155#define R_AX_CMAC_REG_END 0xFFFF
   3156
   3157#define R_AX_LTE_SW_CFG_1 0x0038
   3158#define R_AX_LTE_SW_CFG_1_C1 0x2038
   3159#define B_AX_GNT_BT_RFC_S1_SW_VAL BIT(31)
   3160#define B_AX_GNT_BT_RFC_S1_SW_CTRL BIT(30)
   3161#define B_AX_GNT_WL_RFC_S1_SW_VAL BIT(29)
   3162#define B_AX_GNT_WL_RFC_S1_SW_CTRL BIT(28)
   3163#define B_AX_GNT_BT_BB_S1_SW_VAL BIT(27)
   3164#define B_AX_GNT_BT_BB_S1_SW_CTRL BIT(26)
   3165#define B_AX_GNT_WL_BB_S1_SW_VAL BIT(25)
   3166#define B_AX_GNT_WL_BB_S1_SW_CTRL BIT(24)
   3167#define B_AX_BT_SW_CTRL_WL_PRIORITY BIT(19)
   3168#define B_AX_WL_SW_CTRL_WL_PRIORITY BIT(18)
   3169#define B_AX_LTE_PATTERN_2_EN BIT(17)
   3170#define B_AX_LTE_PATTERN_1_EN BIT(16)
   3171#define B_AX_GNT_BT_RFC_S0_SW_VAL BIT(15)
   3172#define B_AX_GNT_BT_RFC_S0_SW_CTRL BIT(14)
   3173#define B_AX_GNT_WL_RFC_S0_SW_VAL BIT(13)
   3174#define B_AX_GNT_WL_RFC_S0_SW_CTRL BIT(12)
   3175#define B_AX_GNT_BT_BB_S0_SW_VAL BIT(11)
   3176#define B_AX_GNT_BT_BB_S0_SW_CTRL BIT(10)
   3177#define B_AX_GNT_WL_BB_S0_SW_VAL BIT(9)
   3178#define B_AX_GNT_WL_BB_S0_SW_CTRL BIT(8)
   3179#define B_AX_LTECOEX_FUN_EN BIT(7)
   3180#define B_AX_LTECOEX_3WIRE_CTRL_MUX BIT(6)
   3181#define B_AX_LTECOEX_OP_MODE_SEL_MASK GENMASK(5, 4)
   3182#define B_AX_LTECOEX_UART_MUX BIT(3)
   3183#define B_AX_LTECOEX_UART_MODE_SEL_MASK GENMASK(2, 0)
   3184
   3185#define R_AX_LTE_SW_CFG_2 0x003C
   3186#define R_AX_LTE_SW_CFG_2_C1 0x203C
   3187#define B_AX_WL_RX_CTRL BIT(8)
   3188#define B_AX_GNT_WL_RX_SW_VAL BIT(7)
   3189#define B_AX_GNT_WL_RX_SW_CTRL BIT(6)
   3190#define B_AX_GNT_WL_TX_SW_VAL BIT(5)
   3191#define B_AX_GNT_WL_TX_SW_CTRL BIT(4)
   3192#define B_AX_GNT_BT_RX_SW_VAL BIT(3)
   3193#define B_AX_GNT_BT_RX_SW_CTRL BIT(2)
   3194#define B_AX_GNT_BT_TX_SW_VAL BIT(1)
   3195#define B_AX_GNT_BT_TX_SW_CTRL BIT(0)
   3196
   3197#define RR_MOD 0x00
   3198#define RR_MOD_V1 0x10000
   3199#define RR_MOD_IQK GENMASK(19, 4)
   3200#define RR_MOD_DPK GENMASK(19, 5)
   3201#define RR_MOD_MASK GENMASK(19, 16)
   3202#define RR_MOD_V_DOWN 0x0
   3203#define RR_MOD_V_STANDBY 0x1
   3204#define RR_MOD_V_TX 0x2
   3205#define RR_MOD_V_RX 0x3
   3206#define RR_MOD_V_TXIQK 0x4
   3207#define RR_MOD_V_DPK 0x5
   3208#define RR_MOD_V_RXK1 0x6
   3209#define RR_MOD_V_RXK2 0x7
   3210#define RR_MOD_NBW GENMASK(15, 14)
   3211#define RR_MOD_M_RXG GENMASK(13, 4)
   3212#define RR_MOD_M_RXBB GENMASK(9, 5)
   3213#define RR_MODOPT 0x01
   3214#define RR_MODOPT_M_TXPWR GENMASK(5, 0)
   3215#define RR_WLSEL 0x02
   3216#define RR_WLSEL_AG GENMASK(18, 16)
   3217#define RR_RSV1 0x05
   3218#define RR_RSV1_RST BIT(0)
   3219#define RR_BBDC 0x10005
   3220#define RR_BBDC_SEL BIT(0)
   3221#define RR_DTXLOK 0x08
   3222#define RR_RSV2 0x09
   3223#define RR_LOKVB 0x0a
   3224#define RR_LOKVB_COI GENMASK(19, 14)
   3225#define RR_LOKVB_COQ GENMASK(9, 4)
   3226#define RR_TXIG 0x11
   3227#define RR_TXIG_TG GENMASK(16, 12)
   3228#define RR_TXIG_GR1 GENMASK(6, 4)
   3229#define RR_TXIG_GR0 GENMASK(1, 0)
   3230#define RR_CHTR 0x17
   3231#define RR_CHTR_MOD GENMASK(11, 10)
   3232#define RR_CHTR_TXRX GENMASK(9, 0)
   3233#define RR_CFGCH 0x18
   3234#define RR_CFGCH_V1 0x10018
   3235#define RR_CFGCH_BAND1 GENMASK(17, 16)
   3236#define CFGCH_BAND1_2G 0
   3237#define CFGCH_BAND1_5G 1
   3238#define CFGCH_BAND1_6G 3
   3239#define RR_CFGCH_BAND0 GENMASK(9, 8)
   3240#define CFGCH_BAND0_2G 0
   3241#define CFGCH_BAND0_5G 1
   3242#define CFGCH_BAND0_6G 0
   3243#define RR_CFGCH_BW GENMASK(11, 10)
   3244#define RR_CFGCH_CH GENMASK(7, 0)
   3245#define CFGCH_BW_20M 3
   3246#define CFGCH_BW_40M 2
   3247#define CFGCH_BW_80M 1
   3248#define CFGCH_BW_160M 0
   3249#define RR_APK 0x19
   3250#define RR_APK_MOD GENMASK(5, 4)
   3251#define RR_BTC 0x1a
   3252#define RR_BTC_TXBB GENMASK(14, 12)
   3253#define RR_BTC_RXBB GENMASK(11, 10)
   3254#define RR_RCKC 0x1b
   3255#define RR_RCKC_CA GENMASK(14, 10)
   3256#define RR_RCKS 0x1c
   3257#define RR_RCKO 0x1d
   3258#define RR_RCKO_OFF GENMASK(13, 9)
   3259#define RR_RXKPLL 0x1e
   3260#define RR_RXKPLL_OFF GENMASK(5, 0)
   3261#define RR_RXKPLL_POW BIT(19)
   3262#define RR_RSV4 0x1f
   3263#define RR_RSV4_AGH GENMASK(17, 16)
   3264#define RR_RSV4_PLLCH GENMASK(9, 0)
   3265#define RR_RXK 0x20
   3266#define RR_RXK_SEL2G BIT(8)
   3267#define RR_RXK_SEL5G BIT(7)
   3268#define RR_RXK_PLLEN BIT(5)
   3269#define RR_LUTWA 0x33
   3270#define RR_LUTWA_MASK GENMASK(9, 0)
   3271#define RR_LUTWA_M2 GENMASK(4, 0)
   3272#define RR_LUTWD1 0x3e
   3273#define RR_LUTWD0 0x3f
   3274#define RR_LUTWD0_LB GENMASK(5, 0)
   3275#define RR_TM 0x42
   3276#define RR_TM_TRI BIT(19)
   3277#define RR_TM_VAL GENMASK(6, 1)
   3278#define RR_TM2 0x43
   3279#define RR_TM2_OFF GENMASK(19, 16)
   3280#define RR_TXG1 0x51
   3281#define RR_TXG1_ATT2 BIT(19)
   3282#define RR_TXG1_ATT1 BIT(11)
   3283#define RR_TXG2 0x52
   3284#define RR_TXG2_ATT0 BIT(11)
   3285#define RR_BSPAD 0x54
   3286#define RR_TXGA 0x55
   3287#define RR_TXGA_TRK_EN BIT(7)
   3288#define RR_TXGA_LOK_EXT GENMASK(4, 0)
   3289#define RR_TXGA_LOK_EN BIT(0)
   3290#define RR_GAINTX 0x56
   3291#define RR_GAINTX_ALL GENMASK(15, 0)
   3292#define RR_GAINTX_PAD GENMASK(9, 5)
   3293#define RR_GAINTX_BB GENMASK(4, 0)
   3294#define RR_TXMO 0x58
   3295#define RR_TXMO_COI GENMASK(19, 15)
   3296#define RR_TXMO_COQ GENMASK(14, 10)
   3297#define RR_TXMO_FII GENMASK(9, 6)
   3298#define RR_TXMO_FIQ GENMASK(5, 2)
   3299#define RR_TXA 0x5d
   3300#define RR_TXA_TRK GENMASK(19, 14)
   3301#define RR_TXRSV 0x5c
   3302#define RR_TXRSV_GAPK BIT(19)
   3303#define RR_BIAS 0x5e
   3304#define RR_BIAS_GAPK BIT(19)
   3305#define RR_BIASA 0x60
   3306#define RR_BIASA_TXG GENMASK(15, 12)
   3307#define RR_BIASA_TXA GENMASK(19, 16)
   3308#define RR_BIASA_A GENMASK(2, 0)
   3309#define RR_BIASA2 0x63
   3310#define RR_BIASA2_LB GENMASK(4, 2)
   3311#define RR_TXATANK 0x64
   3312#define RR_TXATANK_LBSW2 GENMASK(17, 15)
   3313#define RR_TXATANK_LBSW GENMASK(16, 15)
   3314#define RR_TXA2 0x65
   3315#define RR_TXA2_LDO GENMASK(19, 16)
   3316#define RR_TRXIQ 0x66
   3317#define RR_RSV6 0x6d
   3318#define RR_TXPOW 0x7f
   3319#define RR_TXPOW_TXA BIT(8)
   3320#define RR_TXPOW_TXAS BIT(7)
   3321#define RR_TXPOW_TXG BIT(1)
   3322#define RR_RXPOW 0x80
   3323#define RR_RXPOW_IQK GENMASK(17, 16)
   3324#define RR_RXBB 0x83
   3325#define RR_RXBB_VOBUF GENMASK(15, 12)
   3326#define RR_RXBB_C2G GENMASK(16, 10)
   3327#define RR_RXBB_C1G GENMASK(9, 8)
   3328#define RR_RXBB_ATTR GENMASK(7, 4)
   3329#define RR_RXBB_ATTC GENMASK(2, 0)
   3330#define RR_RXG 0x84
   3331#define RR_RXG_IQKMOD GENMASK(19, 16)
   3332#define RR_XGLNA2 0x85
   3333#define RR_XGLNA2_SW GENMASK(1, 0)
   3334#define RR_RXAE 0x89
   3335#define RR_RXAE_IQKMOD GENMASK(3, 0)
   3336#define RR_RXA 0x8a
   3337#define RR_RXA_DPK GENMASK(9, 8)
   3338#define RR_RXA2 0x8c
   3339#define RR_RXA2_C1 GENMASK(12, 10)
   3340#define RR_RXA2_C2 GENMASK(9, 3)
   3341#define RR_RXA2_IATT GENMASK(7, 4)
   3342#define RR_RXA2_ATT GENMASK(3, 0)
   3343#define RR_RXIQGEN 0x8d
   3344#define RR_RXIQGEN_ATTL GENMASK(12, 8)
   3345#define RR_RXIQGEN_ATTH GENMASK(14, 13)
   3346#define RR_RXBB2 0x8f
   3347#define RR_RXBB2_DAC_EN BIT(13)
   3348#define RR_RXBB2_CKT BIT(12)
   3349#define RR_EN_TIA_IDA GENMASK(11, 10)
   3350#define RR_RXBB2_IDAC GENMASK(11, 9)
   3351#define RR_RXBB2_EBW GENMASK(6, 5)
   3352#define RR_XALNA2 0x90
   3353#define RR_XALNA2_SW GENMASK(1, 0)
   3354#define RR_DCK 0x92
   3355#define RR_DCK_DONE GENMASK(7, 5)
   3356#define RR_DCK_FINE BIT(1)
   3357#define RR_DCK_LV BIT(0)
   3358#define RR_DCK1 0x93
   3359#define RR_DCK1_CLR GENMASK(3, 0)
   3360#define RR_DCK1_SEL BIT(3)
   3361#define RR_DCK2 0x94
   3362#define RR_DCK2_CYCLE GENMASK(7, 2)
   3363#define RR_DCKC 0x95
   3364#define RR_DCKC_CHK BIT(3)
   3365#define RR_IQGEN 0x97
   3366#define RR_IQGEN_BIAS GENMASK(11, 8)
   3367#define RR_TXIQK 0x98
   3368#define RR_TXIQK_ATT2 GENMASK(15, 12)
   3369#define RR_TIA 0x9e
   3370#define RR_TIA_N6 BIT(8)
   3371#define RR_MIXER 0x9f
   3372#define RR_MIXER_GN GENMASK(4, 3)
   3373#define RR_LOGEN 0xa3
   3374#define RR_LOGEN_RPT GENMASK(19, 16)
   3375#define RR_XTALX2 0xb8
   3376#define RR_MALSEL 0xbe
   3377#define RR_LCK_TRG 0xd3
   3378#define RR_LCK_TRGSEL BIT(8)
   3379#define RR_IQKPLL 0xdc
   3380#define RR_IQKPLL_MOD GENMASK(9, 8)
   3381#define RR_RCKD 0xde
   3382#define RR_RCKD_POW GENMASK(19, 13)
   3383#define RR_RCKD_BW BIT(2)
   3384#define RR_TXADBG 0xde
   3385#define RR_LUTDBG 0xdf
   3386#define RR_LUTDBG_TIA BIT(12)
   3387#define RR_LUTDBG_LOK BIT(2)
   3388#define RR_LUTWE2 0xee
   3389#define RR_LUTWE2_RTXBW BIT(2)
   3390#define RR_LUTWE 0xef
   3391#define RR_LUTWE_LOK BIT(2)
   3392#define RR_RFC 0xf0
   3393#define RR_RFC_CKEN BIT(1)
   3394
   3395#define R_UPD_P0 0x0000
   3396#define R_RSTB_WATCH_DOG 0x000C
   3397#define B_P0_RSTB_WATCH_DOG BIT(0)
   3398#define B_P1_RSTB_WATCH_DOG BIT(1)
   3399#define B_UPD_P0_EN BIT(31)
   3400#define R_ANAPAR_PW15 0x030C
   3401#define B_ANAPAR_PW15 GENMASK(31, 24)
   3402#define B_ANAPAR_PW15_H GENMASK(27, 24)
   3403#define B_ANAPAR_PW15_H2 GENMASK(27, 26)
   3404#define R_ANAPAR 0x032C
   3405#define B_ANAPAR_15 GENMASK(31, 16)
   3406#define B_ANAPAR_ADCCLK BIT(30)
   3407#define B_ANAPAR_FLTRST BIT(22)
   3408#define B_ANAPAR_CRXBB GENMASK(18, 16)
   3409#define B_ANAPAR_14 GENMASK(15, 0)
   3410#define R_RFE_E_A2 0x0334
   3411#define R_RFE_O_SEL_A2 0x0338
   3412#define R_RFE_SEL0_A2 0x033C
   3413#define R_RFE_SEL32_A2 0x0340
   3414#define R_SWSI_DATA_V1 0x0370
   3415#define B_SWSI_DATA_VAL_V1 GENMASK(19, 0)
   3416#define B_SWSI_DATA_ADDR_V1 GENMASK(27, 20)
   3417#define B_SWSI_DATA_PATH_V1 GENMASK(30, 28)
   3418#define B_SWSI_DATA_BIT_MASK_EN_V1 BIT(31)
   3419#define R_SWSI_BIT_MASK_V1 0x0374
   3420#define B_SWSI_BIT_MASK_V1 GENMASK(19, 0)
   3421#define R_SWSI_READ_ADDR_V1 0x0378
   3422#define B_SWSI_READ_ADDR_ADDR_V1 GENMASK(7, 0)
   3423#define B_SWSI_READ_ADDR_PATH_V1 GENMASK(10, 8)
   3424#define B_SWSI_READ_ADDR_V1 GENMASK(10, 0)
   3425#define R_UPD_CLK_ADC 0x0700
   3426#define B_UPD_CLK_ADC_VAL GENMASK(26, 25)
   3427#define B_UPD_CLK_ADC_ON BIT(24)
   3428#define B_ENABLE_CCK BIT(5)
   3429#define R_RSTB_ASYNC 0x0704
   3430#define B_RSTB_ASYNC_ALL BIT(1)
   3431#define R_MAC_PIN_SEL 0x0734
   3432#define B_CH_IDX_SEG0 GENMASK(23, 16)
   3433#define R_PLCP_HISTOGRAM 0x0738
   3434#define B_STS_DIS_TRIG_BY_BRK BIT(2)
   3435#define B_STS_DIS_TRIG_BY_FAIL BIT(3)
   3436#define R_PHY_STS_BITMAP_ADDR_START R_PHY_STS_BITMAP_SEARCH_FAIL
   3437#define B_PHY_STS_BITMAP_ADDR_MASK GENMASK(6, 2)
   3438#define R_PHY_STS_BITMAP_SEARCH_FAIL 0x073C
   3439#define B_PHY_STS_BITMAP_MSK_52A 0x337cff3f
   3440#define R_PHY_STS_BITMAP_R2T 0x0740
   3441#define R_PHY_STS_BITMAP_CCA_SPOOF 0x0744
   3442#define R_PHY_STS_BITMAP_OFDM_BRK 0x0748
   3443#define R_PHY_STS_BITMAP_CCK_BRK 0x074C
   3444#define R_PHY_STS_BITMAP_DL_MU_SPOOF 0x0750
   3445#define R_PHY_STS_BITMAP_HE_MU 0x0754
   3446#define R_PHY_STS_BITMAP_VHT_MU 0x0758
   3447#define R_PHY_STS_BITMAP_UL_TB_SPOOF 0x075C
   3448#define R_PHY_STS_BITMAP_TRIGBASE 0x0760
   3449#define R_PHY_STS_BITMAP_CCK 0x0764
   3450#define R_PHY_STS_BITMAP_LEGACY 0x0768
   3451#define R_PHY_STS_BITMAP_HT 0x076C
   3452#define R_PHY_STS_BITMAP_VHT 0x0770
   3453#define R_PHY_STS_BITMAP_HE 0x0774
   3454#define R_PMAC_GNT 0x0980
   3455#define B_PMAC_GNT_TXEN BIT(0)
   3456#define B_PMAC_GNT_RXEN BIT(16)
   3457#define B_PMAC_GNT_P1 GENMASK(20, 17)
   3458#define B_PMAC_GNT_P2 GENMASK(29, 26)
   3459#define R_PMAC_RX_CFG1 0x0988
   3460#define B_PMAC_OPT1_MSK GENMASK(11, 0)
   3461#define R_PMAC_RXMOD 0x0994
   3462#define B_PMAC_RXMOD_MSK GENMASK(7, 4)
   3463#define R_MAC_SEL 0x09A4
   3464#define B_MAC_SEL_OFDM_TRI_FILTER BIT(31)
   3465#define B_MAC_SEL_PWR_EN BIT(16)
   3466#define B_MAC_SEL_DPD_EN BIT(10)
   3467#define B_MAC_SEL_MOD GENMASK(4, 2)
   3468#define R_PMAC_TX_CTRL 0x09C0
   3469#define B_PMAC_TXEN_DIS BIT(0)
   3470#define R_PMAC_TX_PRD 0x09C4
   3471#define B_PMAC_TX_PRD_MSK GENMASK(31, 8)
   3472#define B_PMAC_CTX_EN BIT(0)
   3473#define B_PMAC_PTX_EN BIT(4)
   3474#define R_PMAC_TX_CNT 0x09C8
   3475#define B_PMAC_TX_CNT_MSK GENMASK(31, 0)
   3476#define R_P80_AT_HIGH_FREQ 0x09D8
   3477#define B_P80_AT_HIGH_FREQ BIT(26)
   3478#define R_DBCC_80P80_SEL_EVM_RPT 0x0A10
   3479#define B_DBCC_80P80_SEL_EVM_RPT_EN BIT(0)
   3480#define R_CCX 0x0C00
   3481#define B_CCX_EDCCA_OPT_MSK GENMASK(6, 4)
   3482#define B_MEASUREMENT_TRIG_MSK BIT(2)
   3483#define B_CCX_TRIG_OPT_MSK BIT(1)
   3484#define B_CCX_EN_MSK BIT(0)
   3485#define R_IFS_COUNTER 0x0C28
   3486#define B_IFS_CLM_PERIOD_MSK GENMASK(31, 16)
   3487#define B_IFS_CLM_COUNTER_UNIT_MSK GENMASK(15, 14)
   3488#define B_IFS_COUNTER_CLR_MSK BIT(13)
   3489#define B_IFS_COLLECT_EN BIT(12)
   3490#define R_IFS_T1 0x0C2C
   3491#define B_IFS_T1_TH_HIGH_MSK GENMASK(31, 16)
   3492#define B_IFS_T1_EN_MSK BIT(15)
   3493#define B_IFS_T1_TH_LOW_MSK GENMASK(14, 0)
   3494#define R_IFS_T2 0x0C30
   3495#define B_IFS_T2_TH_HIGH_MSK GENMASK(31, 16)
   3496#define B_IFS_T2_EN_MSK BIT(15)
   3497#define B_IFS_T2_TH_LOW_MSK GENMASK(14, 0)
   3498#define R_IFS_T3 0x0C34
   3499#define B_IFS_T3_TH_HIGH_MSK GENMASK(31, 16)
   3500#define B_IFS_T3_EN_MSK BIT(15)
   3501#define B_IFS_T3_TH_LOW_MSK GENMASK(14, 0)
   3502#define R_IFS_T4 0x0C38
   3503#define B_IFS_T4_TH_HIGH_MSK GENMASK(31, 16)
   3504#define B_IFS_T4_EN_MSK BIT(15)
   3505#define B_IFS_T4_TH_LOW_MSK GENMASK(14, 0)
   3506#define R_PD_CTRL 0x0C3C
   3507#define B_PD_HIT_DIS BIT(9)
   3508#define R_IOQ_IQK_DPK 0x0C60
   3509#define B_IOQ_IQK_DPK_EN BIT(1)
   3510#define R_GNT_BT_WGT_EN 0x0C6C
   3511#define B_GNT_BT_WGT_EN BIT(21)
   3512#define R_PD_ARBITER_OFF 0x0C80
   3513#define B_PD_ARBITER_OFF BIT(31)
   3514#define R_SNDCCA_A1 0x0C9C
   3515#define B_SNDCCA_A1_EN GENMASK(19, 12)
   3516#define R_SNDCCA_A2 0x0CA0
   3517#define B_SNDCCA_A2_VAL GENMASK(19, 12)
   3518#define R_RXHT_MCS_LIMIT 0x0D18
   3519#define B_RXHT_MCS_LIMIT GENMASK(9, 8)
   3520#define R_RXVHT_MCS_LIMIT 0x0D18
   3521#define B_RXVHT_MCS_LIMIT GENMASK(22, 21)
   3522#define R_P0_EN_SOUND_WO_NDP 0x0D7C
   3523#define B_P0_EN_SOUND_WO_NDP BIT(1)
   3524#define R_RXHE 0x0D80
   3525#define B_RXHETB_MAX_NSS GENMASK(25, 23)
   3526#define B_RXHE_MAX_NSS GENMASK(16, 14)
   3527#define B_RXHE_USER_MAX GENMASK(13, 6)
   3528#define R_SPOOF_ASYNC_RST 0x0D84
   3529#define B_SPOOF_ASYNC_RST BIT(15)
   3530#define R_NDP_BRK0 0xDA0
   3531#define R_NDP_BRK1 0xDA4
   3532#define B_NDP_RU_BRK BIT(0)
   3533#define R_BRK_ASYNC_RST_EN_1 0x0DC0
   3534#define R_BRK_ASYNC_RST_EN_2 0x0DC4
   3535#define R_BRK_ASYNC_RST_EN_3 0x0DC8
   3536#define R_S0_HW_SI_DIS 0x1200
   3537#define B_S0_HW_SI_DIS_W_R_TRIG GENMASK(30, 28)
   3538#define R_P0_RXCK 0x12A0
   3539#define B_P0_RXCK_BW3 BIT(30)
   3540#define B_P0_TXCK_ALL GENMASK(19, 12)
   3541#define B_P0_RXCK_ON BIT(19)
   3542#define B_P0_RXCK_VAL GENMASK(18, 16)
   3543#define B_P0_TXCK_ON BIT(15)
   3544#define B_P0_TXCK_VAL GENMASK(14, 12)
   3545#define R_P0_NRBW 0x12B8
   3546#define B_P0_NRBW_DBG BIT(30)
   3547#define R_S0_RXDC 0x12D4
   3548#define B_S0_RXDC_I GENMASK(25, 16)
   3549#define B_S0_RXDC_Q GENMASK(31, 26)
   3550#define R_S0_RXDC2 0x12D8
   3551#define B_S0_RXDC2_SEL GENMASK(9, 8)
   3552#define B_S0_RXDC2_AVG GENMASK(7, 6)
   3553#define B_S0_RXDC2_MEN GENMASK(5, 4)
   3554#define B_S0_RXDC2_Q2 GENMASK(3, 0)
   3555#define R_CFO_COMP_SEG0_L 0x1384
   3556#define R_CFO_COMP_SEG0_H 0x1388
   3557#define R_CFO_COMP_SEG0_CTRL 0x138C
   3558#define R_DBG32_D 0x1730
   3559#define R_SWSI_V1 0x174C
   3560#define B_SWSI_W_BUSY_V1 BIT(24)
   3561#define B_SWSI_R_BUSY_V1 BIT(25)
   3562#define B_SWSI_R_DATA_DONE_V1 BIT(26)
   3563#define R_TX_COUNTER 0x1A40
   3564#define R_IFS_CLM_TX_CNT 0x1ACC
   3565#define B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK GENMASK(31, 16)
   3566#define B_IFS_CLM_TX_CNT_MSK GENMASK(15, 0)
   3567#define R_IFS_CLM_CCA 0x1AD0
   3568#define B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK GENMASK(31, 16)
   3569#define B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK GENMASK(15, 0)
   3570#define R_IFS_CLM_FA 0x1AD4
   3571#define B_IFS_CLM_OFDM_FA_MSK GENMASK(31, 16)
   3572#define B_IFS_CLM_CCK_FA_MSK GENMASK(15, 0)
   3573#define R_IFS_HIS 0x1AD8
   3574#define B_IFS_T4_HIS_MSK GENMASK(31, 24)
   3575#define B_IFS_T3_HIS_MSK GENMASK(23, 16)
   3576#define B_IFS_T2_HIS_MSK GENMASK(15, 8)
   3577#define B_IFS_T1_HIS_MSK GENMASK(7, 0)
   3578#define R_IFS_AVG_L 0x1ADC
   3579#define B_IFS_T2_AVG_MSK GENMASK(31, 16)
   3580#define B_IFS_T1_AVG_MSK GENMASK(15, 0)
   3581#define R_IFS_AVG_H 0x1AE0
   3582#define B_IFS_T4_AVG_MSK GENMASK(31, 16)
   3583#define B_IFS_T3_AVG_MSK GENMASK(15, 0)
   3584#define R_IFS_CCA_L 0x1AE4
   3585#define B_IFS_T2_CCA_MSK GENMASK(31, 16)
   3586#define B_IFS_T1_CCA_MSK GENMASK(15, 0)
   3587#define R_IFS_CCA_H 0x1AE8
   3588#define B_IFS_T4_CCA_MSK GENMASK(31, 16)
   3589#define B_IFS_T3_CCA_MSK GENMASK(15, 0)
   3590#define R_IFSCNT 0x1AEC
   3591#define B_IFSCNT_DONE_MSK BIT(16)
   3592#define B_IFSCNT_TOTAL_CNT_MSK GENMASK(15, 0)
   3593#define R_TXAGC_TP 0x1C04
   3594#define B_TXAGC_TP GENMASK(2, 0)
   3595#define R_TSSI_THER 0x1C10
   3596#define B_TSSI_THER GENMASK(29, 24)
   3597#define R_TXAGC_BTP 0x1CA0
   3598#define B_TXAGC_BTP GENMASK(31, 24)
   3599#define R_TXAGC_BB 0x1C60
   3600#define B_TXAGC_BB_OFT GENMASK(31, 16)
   3601#define B_TXAGC_BB GENMASK(31, 24)
   3602#define R_S0_ADDCK 0x1E00
   3603#define B_S0_ADDCK_I GENMASK(9, 0)
   3604#define B_S0_ADDCK_Q GENMASK(19, 10)
   3605#define R_ADC_FIFO 0x20fc
   3606#define B_ADC_FIFO_RST GENMASK(31, 24)
   3607#define B_ADC_FIFO_RXK GENMASK(31, 16)
   3608#define B_ADC_FIFO_A3 BIT(28)
   3609#define B_ADC_FIFO_A2 BIT(24)
   3610#define B_ADC_FIFO_A1 BIT(20)
   3611#define B_ADC_FIFO_A0 BIT(16)
   3612#define R_TXFIR0 0x2300
   3613#define B_TXFIR_C01 GENMASK(23, 0)
   3614#define R_TXFIR2 0x2304
   3615#define B_TXFIR_C23 GENMASK(23, 0)
   3616#define R_TXFIR4 0x2308
   3617#define B_TXFIR_C45 GENMASK(23, 0)
   3618#define R_TXFIR6 0x230c
   3619#define B_TXFIR_C67 GENMASK(23, 0)
   3620#define R_TXFIR8 0x2310
   3621#define B_TXFIR_C89 GENMASK(23, 0)
   3622#define R_TXFIRA 0x2314
   3623#define B_TXFIR_CAB GENMASK(23, 0)
   3624#define R_TXFIRC 0x2318
   3625#define B_TXFIR_CCD GENMASK(23, 0)
   3626#define R_TXFIRE 0x231c
   3627#define B_TXFIR_CEF GENMASK(23, 0)
   3628#define R_11B_RX_V1 0x2320
   3629#define B_11B_RXCCA_DIS_V1 BIT(0)
   3630#define R_RPL_OFST 0x2340
   3631#define B_RPL_OFST_MASK GENMASK(14, 8)
   3632#define R_RXCCA 0x2344
   3633#define B_RXCCA_DIS BIT(31)
   3634#define R_RXCCA_V1 0x2320
   3635#define B_RXCCA_DIS_V1 BIT(0)
   3636#define R_RXSC 0x237C
   3637#define B_RXSC_EN BIT(0)
   3638#define R_RXSCOBC 0x23B0
   3639#define B_RXSCOBC_TH GENMASK(18, 0)
   3640#define R_RXSCOCCK 0x23B4
   3641#define B_RXSCOCCK_TH GENMASK(18, 0)
   3642#define R_P80_AT_HIGH_FREQ_RU_ALLOC 0x2410
   3643#define B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY1 BIT(14)
   3644#define B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY0 BIT(13)
   3645#define R_DBCC_80P80_SEL_EVM_RPT2 0x2A10
   3646#define B_DBCC_80P80_SEL_EVM_RPT2_EN BIT(0)
   3647#define R_P1_EN_SOUND_WO_NDP 0x2D7C
   3648#define B_P1_EN_SOUND_WO_NDP BIT(1)
   3649#define R_S1_HW_SI_DIS 0x3200
   3650#define B_S1_HW_SI_DIS_W_R_TRIG GENMASK(30, 28)
   3651#define R_P1_DBGMOD 0x32B8
   3652#define B_P1_DBGMOD_ON BIT(30)
   3653#define R_S1_RXDC 0x32D4
   3654#define B_S1_RXDC_I GENMASK(25, 16)
   3655#define B_S1_RXDC_Q GENMASK(31, 26)
   3656#define R_S1_RXDC2 0x32D8
   3657#define B_S1_RXDC2_EN GENMASK(5, 4)
   3658#define B_S1_RXDC2_SEL GENMASK(9, 8)
   3659#define B_S1_RXDC2_Q2 GENMASK(3, 0)
   3660#define R_TXAGC_BB_S1 0x3C60
   3661#define B_TXAGC_BB_S1_OFT GENMASK(31, 16)
   3662#define B_TXAGC_BB_S1 GENMASK(31, 24)
   3663#define R_S1_ADDCK 0x3E00
   3664#define B_S1_ADDCK_I GENMASK(9, 0)
   3665#define B_S1_ADDCK_Q GENMASK(19, 10)
   3666#define R_DCFO 0x4264
   3667#define B_DCFO GENMASK(1, 0)
   3668#define R_SEG0CSI 0x42AC
   3669#define B_SEG0CSI_IDX GENMASK(11, 0)
   3670#define R_SEG0CSI_EN 0x42C4
   3671#define B_SEG0CSI_EN BIT(23)
   3672#define R_BSS_CLR_MAP 0x43ac
   3673#define B_BSS_CLR_MAP_VLD0 BIT(28)
   3674#define B_BSS_CLR_MAP_TGT GENMASK(27, 22)
   3675#define B_BSS_CLR_MAP_STAID GENMASK(21, 11)
   3676#define R_CFO_TRK0 0x4404
   3677#define R_CFO_TRK1 0x440C
   3678#define B_CFO_TRK_MSK GENMASK(14, 10)
   3679#define R_T2F_GI_COMB 0x4424
   3680#define B_T2F_GI_COMB_EN BIT(2)
   3681#define R_BT_DYN_DC_EST_EN 0x441C
   3682#define B_BT_DYN_DC_EST_EN_MSK BIT(31)
   3683#define R_ASSIGN_SBD_OPT 0x4450
   3684#define B_ASSIGN_SBD_OPT_EN BIT(24)
   3685#define R_DCFO_COMP_S0 0x448C
   3686#define B_DCFO_COMP_S0_MSK GENMASK(11, 0)
   3687#define R_DCFO_WEIGHT 0x4490
   3688#define B_DCFO_WEIGHT_MSK GENMASK(27, 24)
   3689#define R_DCFO_OPT 0x4494
   3690#define B_DCFO_OPT_EN BIT(29)
   3691#define R_BANDEDGE 0x4498
   3692#define B_BANDEDGE_EN BIT(30)
   3693#define R_TXPATH_SEL 0x458C
   3694#define B_TXPATH_SEL_MSK GENMASK(31, 28)
   3695#define R_TXPWR 0x4594
   3696#define B_TXPWR_MSK GENMASK(30, 22)
   3697#define R_TXNSS_MAP 0x45B4
   3698#define B_TXNSS_MAP_MSK GENMASK(20, 17)
   3699#define R_PCOEFF0_V1 0x45BC
   3700#define B_PCOEFF01_MSK_V1 GENMASK(23, 0)
   3701#define R_PCOEFF2_V1 0x45CC
   3702#define B_PCOEFF23_MSK_V1 GENMASK(23, 0)
   3703#define R_PCOEFF4_V1 0x45D0
   3704#define B_PCOEFF45_MSK_V1 GENMASK(23, 0)
   3705#define R_PCOEFF6_V1 0x45D4
   3706#define B_PCOEFF67_MSK_V1 GENMASK(23, 0)
   3707#define R_PCOEFF8_V1 0x45D8
   3708#define B_PCOEFF89_MSK_V1 GENMASK(23, 0)
   3709#define R_PCOEFFA_V1 0x45C0
   3710#define B_PCOEFFAB_MSK_V1 GENMASK(23, 0)
   3711#define R_PCOEFFC_V1 0x45C4
   3712#define B_PCOEFFCD_MSK_V1 GENMASK(23, 0)
   3713#define R_PCOEFFE_V1 0x45C8
   3714#define B_PCOEFFEF_MSK_V1 GENMASK(23, 0)
   3715#define R_PATH0_IB_PKPW 0x4628
   3716#define B_PATH0_IB_PKPW_MSK GENMASK(11, 6)
   3717#define R_PATH0_LNA_ERR1 0x462C
   3718#define B_PATH0_LNA_ERR_G1_A_MSK GENMASK(29, 24)
   3719#define B_PATH0_LNA_ERR_G0_G_MSK GENMASK(17, 12)
   3720#define B_PATH0_LNA_ERR_G0_A_MSK GENMASK(11, 6)
   3721#define R_PATH0_LNA_ERR2 0x4630
   3722#define B_PATH0_LNA_ERR_G2_G_MSK GENMASK(23, 18)
   3723#define B_PATH0_LNA_ERR_G2_A_MSK GENMASK(17, 12)
   3724#define B_PATH0_LNA_ERR_G1_G_MSK GENMASK(5, 0)
   3725#define R_PATH0_LNA_ERR3 0x4634
   3726#define B_PATH0_LNA_ERR_G4_G_MSK GENMASK(29, 24)
   3727#define B_PATH0_LNA_ERR_G4_A_MSK GENMASK(23, 18)
   3728#define B_PATH0_LNA_ERR_G3_G_MSK GENMASK(11, 6)
   3729#define B_PATH0_LNA_ERR_G3_A_MSK GENMASK(5, 0)
   3730#define R_PATH0_LNA_ERR4 0x4638
   3731#define B_PATH0_LNA_ERR_G6_A_MSK GENMASK(29, 24)
   3732#define B_PATH0_LNA_ERR_G5_G_MSK GENMASK(17, 12)
   3733#define B_PATH0_LNA_ERR_G5_A_MSK GENMASK(11, 6)
   3734#define R_PATH0_LNA_ERR5 0x463C
   3735#define B_PATH0_LNA_ERR_G6_G_MSK GENMASK(5, 0)
   3736#define R_PATH0_TIA_ERR_G0 0x4640
   3737#define B_PATH0_TIA_ERR_G0_G_MSK GENMASK(23, 18)
   3738#define B_PATH0_TIA_ERR_G0_A_MSK GENMASK(17, 12)
   3739#define R_PATH0_TIA_ERR_G1 0x4644
   3740#define B_PATH0_TIA_ERR_G1_SEL GENMASK(31, 30)
   3741#define B_PATH0_TIA_ERR_G1_G_MSK GENMASK(11, 6)
   3742#define B_PATH0_TIA_ERR_G1_A_MSK GENMASK(5, 0)
   3743#define R_PATH0_IB_PBK 0x4650
   3744#define B_PATH0_IB_PBK_MSK GENMASK(14, 10)
   3745#define R_PATH0_RXB_INIT 0x4658
   3746#define B_PATH0_RXB_INIT_IDX_MSK GENMASK(9, 5)
   3747#define R_PATH0_LNA_INIT 0x4668
   3748#define B_PATH0_LNA_INIT_IDX_MSK GENMASK(26, 24)
   3749#define R_PATH0_BTG 0x466C
   3750#define B_PATH0_BTG_SHEN GENMASK(18, 17)
   3751#define R_PATH0_TIA_INIT 0x4674
   3752#define B_PATH0_TIA_INIT_IDX_MSK BIT(17)
   3753#define R_PATH0_P20_FOLLOW_BY_PAGCUGC 0x46A0
   3754#define B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5)
   3755#define R_PATH0_S20_FOLLOW_BY_PAGCUGC 0x46A4
   3756#define B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5)
   3757#define R_PATH0_G_LNA6_OP1DB_V1 0x4688
   3758#define B_PATH0_G_LNA6_OP1DB_V1 GENMASK(31, 24)
   3759#define R_PATH0_G_TIA0_LNA6_OP1DB_V1 0x4694
   3760#define B_PATH0_G_TIA0_LNA6_OP1DB_V1 GENMASK(7, 0)
   3761#define R_PATH0_G_TIA1_LNA6_OP1DB_V1 0x4694
   3762#define B_PATH0_R_G_OFST_MASK GENMASK(23, 16)
   3763#define B_PATH0_G_TIA1_LNA6_OP1DB_V1 GENMASK(15, 8)
   3764#define R_CDD_EVM_CHK_EN 0x46C0
   3765#define B_CDD_EVM_CHK_EN BIT(0)
   3766#define R_PATH0_BAND_SEL_V1 0x4738
   3767#define B_PATH0_BAND_SEL_MSK_V1 BIT(17)
   3768#define R_PATH0_BT_SHARE_V1 0x4738
   3769#define B_PATH0_BT_SHARE_V1 BIT(19)
   3770#define R_PATH0_BTG_PATH_V1 0x4738
   3771#define B_PATH0_BTG_PATH_V1 BIT(22)
   3772#define R_P0_NBIIDX 0x469C
   3773#define B_P0_NBIIDX_VAL GENMASK(11, 0)
   3774#define B_P0_NBIIDX_NOTCH_EN BIT(12)
   3775#define R_P0_BACKOFF_IBADC_V1 0x469C
   3776#define B_P0_BACKOFF_IBADC_V1 GENMASK(31, 26)
   3777#define B_P0_NBIIDX_NOTCH_EN_V1 BIT(12)
   3778#define R_P1_MODE 0x4718
   3779#define B_P1_MODE_SEL GENMASK(31, 30)
   3780#define R_P0_AGC_CTL 0x4730
   3781#define B_P0_AGC_EN BIT(31)
   3782#define R_PATH1_LNA_INIT 0x473C
   3783#define B_PATH1_LNA_INIT_IDX_MSK GENMASK(26, 24)
   3784#define R_PATH1_TIA_INIT 0x4748
   3785#define B_PATH1_TIA_INIT_IDX_MSK BIT(17)
   3786#define R_PATH1_BTG 0x4740
   3787#define B_PATH1_BTG_SHEN GENMASK(18, 17)
   3788#define R_PATH1_RXB_INIT 0x472C
   3789#define B_PATH1_RXB_INIT_IDX_MSK GENMASK(9, 5)
   3790#define R_PATH1_G_LNA6_OP1DB_V1 0x476C
   3791#define B_PATH1_G_LNA6_OP1DB_V1 GENMASK(31, 24)
   3792#define R_PATH1_P20_FOLLOW_BY_PAGCUGC 0x4774
   3793#define B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5)
   3794#define R_PATH1_S20_FOLLOW_BY_PAGCUGC 0x4778
   3795#define B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5)
   3796#define R_PATH1_G_TIA0_LNA6_OP1DB_V1 0x4778
   3797#define B_PATH1_G_TIA0_LNA6_OP1DB_V1 GENMASK(7, 0)
   3798#define R_PATH1_G_TIA1_LNA6_OP1DB_V1 0x4778
   3799#define B_PATH1_G_TIA1_LNA6_OP1DB_V1 GENMASK(15, 8)
   3800#define R_PATH1_BAND_SEL_V1 0x4AA4
   3801#define B_PATH1_BAND_SEL_MSK_V1 BIT(17)
   3802#define R_PATH1_BT_SHARE_V1 0x4AA4
   3803#define B_PATH1_BT_SHARE_V1 BIT(19)
   3804#define R_PATH1_BTG_PATH_V1 0x4AA4
   3805#define B_PATH1_BTG_PATH_V1 BIT(22)
   3806#define R_P1_NBIIDX 0x4770
   3807#define B_P1_NBIIDX_VAL GENMASK(11, 0)
   3808#define B_P1_NBIIDX_NOTCH_EN BIT(12)
   3809#define R_SEG0R_PD 0x481C
   3810#define B_SEG0R_PD_SPATIAL_REUSE_EN_MSK BIT(29)
   3811#define B_SEG0R_PD_LOWER_BOUND_MSK GENMASK(10, 6)
   3812#define R_2P4G_BAND 0x4970
   3813#define B_2P4G_BAND_SEL BIT(1)
   3814#define R_FC0_BW 0x4974
   3815#define B_FC0_BW_INV GENMASK(6, 0)
   3816#define B_FC0_BW_SET GENMASK(31, 30)
   3817#define B_ANT_RX_BT_SEG0 GENMASK(25, 22)
   3818#define B_ANT_RX_1RCCA_SEG1 GENMASK(21, 18)
   3819#define B_ANT_RX_1RCCA_SEG0 GENMASK(17, 14)
   3820#define R_CHBW_MOD 0x4978
   3821#define B_BT_SHARE BIT(14)
   3822#define B_CHBW_MOD_SBW GENMASK(13, 12)
   3823#define B_CHBW_MOD_PRICH GENMASK(11, 8)
   3824#define B_ANT_RX_SEG0 GENMASK(3, 0)
   3825#define R_PD_BOOST_EN 0x49E8
   3826#define B_PD_BOOST_EN BIT(7)
   3827#define R_P1_BACKOFF_IBADC_V1 0x49F0
   3828#define B_P1_BACKOFF_IBADC_V1 GENMASK(31, 26)
   3829#define R_BK_FC0_INV_V1 0x4A1C
   3830#define B_BK_FC0_INV_MSK_V1 GENMASK(18, 0)
   3831#define R_CCK_FC0_INV_V1 0x4A20
   3832#define B_CCK_FC0_INV_MSK_V1 GENMASK(18, 0)
   3833#define R_P1_AGC_CTL 0x4A9C
   3834#define B_P1_AGC_EN BIT(31)
   3835#define R_PATH0_RXBB_V1 0x4AD4
   3836#define B_PATH0_RXBB_MSK_V1 GENMASK(31, 0)
   3837#define R_PATH1_RXBB_V1 0x4AE0
   3838#define B_PATH1_RXBB_MSK_V1 GENMASK(31, 0)
   3839#define R_PATH0_BT_BACKOFF_V1 0x4AE4
   3840#define B_PATH0_BT_BACKOFF_V1 GENMASK(23, 0)
   3841#define R_PATH1_BT_BACKOFF_V1 0x4AEC
   3842#define B_PATH1_BT_BACKOFF_V1 GENMASK(23, 0)
   3843#define R_PATH0_FRC_FIR_TYPE_V1 0x4C00
   3844#define B_PATH0_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0)
   3845#define R_PATH0_NOTCH 0x4C14
   3846#define B_PATH0_NOTCH_EN BIT(12)
   3847#define B_PATH0_NOTCH_VAL GENMASK(11, 0)
   3848#define R_PATH0_NOTCH2 0x4C20
   3849#define B_PATH0_NOTCH2_EN BIT(12)
   3850#define B_PATH0_NOTCH2_VAL GENMASK(11, 0)
   3851#define R_PATH0_5MDET 0x4C4C
   3852#define B_PATH0_5MDET_EN BIT(12)
   3853#define B_PATH0_5MDET_SB2 BIT(8)
   3854#define B_PATH0_5MDET_SB0 BIT(6)
   3855#define B_PATH0_5MDET_TH GENMASK(5, 0)
   3856#define R_PATH1_FRC_FIR_TYPE_V1 0x4CC4
   3857#define B_PATH1_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0)
   3858#define R_PATH1_NOTCH 0x4CD8
   3859#define B_PATH1_NOTCH_EN BIT(12)
   3860#define B_PATH1_NOTCH_VAL GENMASK(11, 0)
   3861#define R_PATH1_NOTCH2 0x4CE4
   3862#define B_PATH1_NOTCH2_EN BIT(12)
   3863#define B_PATH1_NOTCH2_VAL GENMASK(11, 0)
   3864#define R_PATH1_5MDET 0x4D10
   3865#define B_PATH1_5MDET_EN BIT(12)
   3866#define B_PATH1_5MDET_SB2 BIT(8)
   3867#define B_PATH1_5MDET_SB0 BIT(6)
   3868#define B_PATH1_5MDET_TH GENMASK(5, 0)
   3869#define R_RPL_BIAS_COMP 0x4DF0
   3870#define B_RPL_BIAS_COMP_MASK GENMASK(7, 0)
   3871#define R_RPL_PATHAB 0x4E0C
   3872#define B_RPL_PATHB_MASK GENMASK(23, 16)
   3873#define B_RPL_PATHA_MASK GENMASK(15, 8)
   3874#define R_RSSI_M_PATHAB 0x4E2C
   3875#define B_RSSI_M_PATHB_MASK GENMASK(15, 8)
   3876#define B_RSSI_M_PATHA_MASK GENMASK(7, 0)
   3877#define R_FC0_V1 0x4E30
   3878#define B_FC0_MSK_V1 GENMASK(12, 0)
   3879#define R_RX_BW40_2XFFT_EN_V1 0x4E30
   3880#define B_RX_BW40_2XFFT_EN_MSK_V1 BIT(26)
   3881#define R_DCFO_COMP_S0_V1 0x4A40
   3882#define B_DCFO_COMP_S0_V1_MSK GENMASK(13, 0)
   3883#define R_BMODE_PDTH_V1 0x4B64
   3884#define B_BMODE_PDTH_LOWER_BOUND_MSK_V1 GENMASK(31, 24)
   3885#define R_BMODE_PDTH_EN_V1 0x4B74
   3886#define B_BMODE_PDTH_LIMIT_EN_MSK_V1 BIT(30)
   3887#define R_CFO_COMP_SEG1_L 0x5384
   3888#define R_CFO_COMP_SEG1_H 0x5388
   3889#define R_CFO_COMP_SEG1_CTRL 0x538C
   3890#define B_CFO_COMP_VALID_BIT BIT(29)
   3891#define B_CFO_COMP_WEIGHT_MSK GENMASK(27, 24)
   3892#define B_CFO_COMP_VAL_MSK GENMASK(11, 0)
   3893#define R_UPD_CLK 0x5670
   3894#define B_DAC_VAL BIT(31)
   3895#define B_ACK_VAL GENMASK(30, 29)
   3896#define B_DPD_DIS BIT(14)
   3897#define B_DPD_GDIS BIT(13)
   3898#define B_IQK_RFC_ON BIT(1)
   3899#define R_TXPWRB 0x56CC
   3900#define B_TXPWRB_ON BIT(28)
   3901#define B_TXPWRB_VAL GENMASK(27, 19)
   3902#define R_DPD_OFT_EN 0x5800
   3903#define B_DPD_OFT_EN BIT(28)
   3904#define R_DPD_OFT_ADDR 0x5804
   3905#define B_DPD_OFT_ADDR GENMASK(31, 27)
   3906#define R_TXPWRB_H 0x580c
   3907#define B_TXPWRB_RDY BIT(15)
   3908#define R_P0_TMETER 0x5810
   3909#define B_P0_TMETER GENMASK(15, 10)
   3910#define B_P0_TMETER_DIS BIT(16)
   3911#define B_P0_TMETER_TRK BIT(24)
   3912#define R_P0_TSSI_TRK 0x5818
   3913#define B_P0_TSSI_TRK_EN BIT(30)
   3914#define B_P0_TSSI_OFT_EN BIT(28)
   3915#define B_P0_TSSI_OFT GENMASK(7, 0)
   3916#define R_P0_TSSI_AVG 0x5820
   3917#define B_P0_TSSI_AVG GENMASK(15, 12)
   3918#define R_P0_RFCTM 0x5864
   3919#define B_P0_RFCTM_VAL GENMASK(25, 20)
   3920#define R_P0_RFCTM_RDY BIT(26)
   3921#define R_P0_TRSW 0x5868
   3922#define B_P0_TRSW_B BIT(0)
   3923#define B_P0_TRSW_A BIT(1)
   3924#define B_P0_TRSW_X BIT(2)
   3925#define B_P0_TRSW_SO_A2 GENMASK(7, 5)
   3926#define R_P0_RFM 0x5894
   3927#define B_P0_RFM_DIS_WL BIT(7)
   3928#define B_P0_RFM_TX_OPT BIT(6)
   3929#define B_P0_RFM_BT_EN BIT(5)
   3930#define B_P0_RFM_OUT GENMASK(4, 0)
   3931#define R_P0_TXDPD 0x58D4
   3932#define B_P0_TXDPD GENMASK(31, 28)
   3933#define R_P0_TXPW_RSTB 0x58DC
   3934#define B_P0_TXPW_RSTB_MANON BIT(30)
   3935#define B_P0_TXPW_RSTB_TSSI BIT(31)
   3936#define R_P0_TSSI_MV_AVG 0x58E4
   3937#define B_P0_TSSI_MV_AVG GENMASK(13, 11)
   3938#define R_TXGAIN_SCALE 0x58F0
   3939#define B_TXGAIN_SCALE_EN BIT(19)
   3940#define B_TXGAIN_SCALE_OFT GENMASK(31, 24)
   3941#define R_P0_TSSI_BASE 0x5C00
   3942#define R_S0_DACKI 0x5E00
   3943#define B_S0_DACKI_AR GENMASK(31, 28)
   3944#define B_S0_DACKI_EN BIT(3)
   3945#define R_S0_DACKI2 0x5E30
   3946#define B_S0_DACKI2_K GENMASK(21, 12)
   3947#define R_S0_DACKI7 0x5E44
   3948#define B_S0_DACKI7_K GENMASK(15, 8)
   3949#define R_S0_DACKI8 0x5E48
   3950#define B_S0_DACKI8_K GENMASK(15, 8)
   3951#define R_S0_DACKQ 0x5E50
   3952#define B_S0_DACKQ_AR GENMASK(31, 28)
   3953#define B_S0_DACKQ_EN BIT(3)
   3954#define R_S0_DACKQ2 0x5E80
   3955#define B_S0_DACKQ2_K GENMASK(21, 12)
   3956#define R_S0_DACKQ7 0x5E94
   3957#define B_S0_DACKQ7_K GENMASK(15, 8)
   3958#define R_S0_DACKQ8 0x5E98
   3959#define B_S0_DACKQ8_K GENMASK(15, 8)
   3960#define R_RPL_BIAS_COMP1 0x6DF0
   3961#define B_RPL_BIAS_COMP1_MASK GENMASK(7, 0)
   3962#define R_P1_TMETER 0x7810
   3963#define B_P1_TMETER GENMASK(15, 10)
   3964#define B_P1_TMETER_DIS BIT(16)
   3965#define B_P1_TMETER_TRK BIT(24)
   3966#define R_P1_TSSI_TRK 0x7818
   3967#define B_P1_TSSI_TRK_EN BIT(30)
   3968#define B_P1_TSSI_OFT_EN BIT(28)
   3969#define B_P1_TSSI_OFT GENMASK(7, 0)
   3970#define R_P1_TSSI_AVG 0x7820
   3971#define B_P1_TSSI_AVG GENMASK(15, 12)
   3972#define R_P1_RFCTM 0x7864
   3973#define R_P1_RFCTM_RDY BIT(26)
   3974#define B_P1_RFCTM_VAL GENMASK(25, 20)
   3975#define R_P1_TXPW_RSTB 0x78DC
   3976#define B_P1_TXPW_RSTB_MANON BIT(30)
   3977#define B_P1_TXPW_RSTB_TSSI BIT(31)
   3978#define R_P1_TSSI_MV_AVG 0x78E4
   3979#define B_P1_TSSI_MV_AVG GENMASK(13, 11)
   3980#define R_TSSI_THOF 0x7C00
   3981#define R_S1_DACKI 0x7E00
   3982#define B_S1_DACKI_AR GENMASK(31, 28)
   3983#define B_S1_DACKI_EN BIT(3)
   3984#define R_S1_DACKI2 0x7E30
   3985#define B_S1_DACKI2_K GENMASK(21, 12)
   3986#define R_S1_DACKI7 0x7E44
   3987#define B_S1_DACKI_K GENMASK(15, 8)
   3988#define R_S1_DACKI8 0x7E48
   3989#define B_S1_DACKI8_K GENMASK(15, 8)
   3990#define R_S1_DACKQ 0x7E50
   3991#define B_S1_DACKQ_AR GENMASK(31, 28)
   3992#define B_S1_DACKQ_EN BIT(3)
   3993#define R_S1_DACKQ2 0x7E80
   3994#define B_S1_DACKQ2_K GENMASK(21, 12)
   3995#define R_S1_DACKQ7 0x7E94
   3996#define B_S1_DACKQ7_K GENMASK(15, 8)
   3997#define R_S1_DACKQ8 0x7E98
   3998#define B_S1_DACKQ8_K GENMASK(15, 8)
   3999#define R_NCTL_CFG 0x8000
   4000#define B_NCTL_CFG_SPAGE GENMASK(2, 1)
   4001#define R_NCTL_RPT 0x8008
   4002#define B_NCTL_RPT_FLG BIT(26)
   4003#define R_NCTL_N1 0x8010
   4004#define B_NCTL_N1_CIP GENMASK(7, 0)
   4005#define R_NCTL_N2 0x8014
   4006#define R_IQK_COM 0x8018
   4007#define R_IQK_DIF 0x801C
   4008#define B_IQK_DIF_TRX GENMASK(1, 0)
   4009#define R_IQK_DIF1 0x8020
   4010#define B_IQK_DIF1_TXPI GENMASK(19, 0)
   4011#define R_IQK_DIF2 0x8024
   4012#define B_IQK_DIF2_RXPI GENMASK(19, 0)
   4013#define R_IQK_DIF4 0x802C
   4014#define B_IQK_DIF4_RXT GENMASK(27, 16)
   4015#define B_IQK_DIF4_TXT GENMASK(11, 0)
   4016#define IQK_DF4_TXT_8_25MHZ 0x021
   4017#define R_IQK_CFG 0x8034
   4018#define B_IQK_CFG_SET GENMASK(5, 4)
   4019#define R_TPG_SEL 0x8068
   4020#define R_TPG_MOD 0x806C
   4021#define B_TPG_MOD_F GENMASK(2, 1)
   4022#define R_MDPK_SYNC 0x8070
   4023#define B_MDPK_SYNC_SEL BIT(31)
   4024#define B_MDPK_SYNC_MAN GENMASK(31, 28)
   4025#define R_MDPK_RX_DCK 0x8074
   4026#define B_MDPK_RX_DCK_EN BIT(31)
   4027#define R_KIP_MOD 0x8078
   4028#define B_KIP_MOD GENMASK(19, 0)
   4029#define R_NCTL_RW 0x8080
   4030#define R_KIP_SYSCFG 0x8088
   4031#define R_KIP_CLK 0x808C
   4032#define R_DPK_IDL 0x809C
   4033#define B_DPK_IDL BIT(8)
   4034#define R_LDL_NORM 0x80A0
   4035#define B_LDL_NORM_MA BIT(16)
   4036#define B_LDL_NORM_PN GENMASK(12, 8)
   4037#define B_LDL_NORM_OP GENMASK(1, 0)
   4038#define R_DPK_CTL 0x80B0
   4039#define B_DPK_CTL_EN BIT(28)
   4040#define R_DPK_CFG 0x80B8
   4041#define B_DPK_CFG_IDX GENMASK(14, 12)
   4042#define R_DPK_CFG2 0x80BC
   4043#define B_DPK_CFG2_ST BIT(14)
   4044#define R_DPK_CFG3 0x80C0
   4045#define R_KPATH_CFG 0x80D0
   4046#define B_KPATH_CFG_ED GENMASK(21, 20)
   4047#define R_KIP_RPT1 0x80D4
   4048#define B_KIP_RPT1_SEL GENMASK(21, 16)
   4049#define R_SRAM_IQRX 0x80D8
   4050#define R_GAPK 0x80E0
   4051#define B_GAPK_ADR BIT(0)
   4052#define R_SRAM_IQRX2 0x80E8
   4053#define R_DPK_MPA 0x80EC
   4054#define B_DPK_MPA_T0 BIT(10)
   4055#define B_DPK_MPA_T1 BIT(9)
   4056#define B_DPK_MPA_T2 BIT(8)
   4057#define R_DPK_WR 0x80F4
   4058#define B_DPK_WR_ST BIT(29)
   4059#define R_DPK_TRK 0x80f0
   4060#define B_DPK_TRK_DIS BIT(31)
   4061#define R_RPT_COM 0x80FC
   4062#define B_PRT_COM_SYNERR BIT(30)
   4063#define B_PRT_COM_DCI GENMASK(27, 16)
   4064#define B_PRT_COM_CORV GENMASK(15, 8)
   4065#define B_PRT_COM_DCQ GENMASK(11, 0)
   4066#define B_PRT_COM_RXOV BIT(8)
   4067#define B_PRT_COM_GL GENMASK(7, 4)
   4068#define B_PRT_COM_CORI GENMASK(7, 0)
   4069#define B_PRT_COM_RXBB GENMASK(5, 0)
   4070#define B_PRT_COM_DONE BIT(0)
   4071#define R_COEF_SEL 0x8104
   4072#define B_COEF_SEL_IQC BIT(0)
   4073#define B_COEF_SEL_MDPD BIT(8)
   4074#define R_CFIR_SYS 0x8120
   4075#define R_IQK_RES 0x8124
   4076#define B_IQK_RES_TXCFIR GENMASK(11, 8)
   4077#define B_IQK_RES_RXCFIR GENMASK(3, 0)
   4078#define R_TXIQC 0x8138
   4079#define R_RXIQC 0x813c
   4080#define B_RXIQC_BYPASS BIT(0)
   4081#define B_RXIQC_BYPASS2 BIT(2)
   4082#define B_RXIQC_NEWP GENMASK(19, 8)
   4083#define B_RXIQC_NEWX GENMASK(31, 20)
   4084#define R_KIP 0x8140
   4085#define B_KIP_DBCC BIT(0)
   4086#define B_KIP_RFGAIN BIT(8)
   4087#define R_RFGAIN 0x8144
   4088#define B_RFGAIN_PAD GENMASK(4, 0)
   4089#define B_RFGAIN_TXBB GENMASK(12, 8)
   4090#define R_RFGAIN_BND 0x8148
   4091#define B_RFGAIN_BND GENMASK(4, 0)
   4092#define R_CFIR_MAP 0x8150
   4093#define R_CFIR_LUT 0x8154
   4094#define B_CFIR_LUT_SEL BIT(8)
   4095#define B_CFIR_LUT_SET BIT(4)
   4096#define B_CFIR_LUT_G3 BIT(3)
   4097#define B_CFIR_LUT_G2 BIT(2)
   4098#define B_CFIR_LUT_GP_V1 GENMASK(2, 0)
   4099#define B_CFIR_LUT_GP GENMASK(1, 0)
   4100#define R_DPK_GN 0x819C
   4101#define B_DPK_GN_EN GENMASK(17, 16)
   4102#define B_DPK_GN_AG GENMASK(9, 0)
   4103#define R_DPD_V1 0x81a0
   4104#define B_DPD_LBK BIT(7)
   4105#define R_DPD_CH0 0x81AC
   4106#define R_DPD_BND 0x81B4
   4107#define R_DPD_CH0A 0x81BC
   4108#define B_DPD_MEN GENMASK(31, 28)
   4109#define B_DPD_ORDER GENMASK(26, 24)
   4110#define B_DPD_SEL GENMASK(13, 8)
   4111#define R_TXAGC_RFK 0x81C4
   4112#define B_TXAGC_RFK_CH0 GENMASK(5, 0)
   4113#define R_DPD_COM 0x81C8
   4114#define R_KIP_IQP 0x81CC
   4115#define B_KIP_IQP_SW GENMASK(13, 12)
   4116#define B_KIP_IQP_IQSW GENMASK(5, 0)
   4117#define R_KIP_RPT 0x81D4
   4118#define B_KIP_RPT_SEL GENMASK(21, 16)
   4119#define R_W_COEF 0x81D8
   4120#define R_LOAD_COEF 0x81DC
   4121#define B_LOAD_COEF_MDPD BIT(16)
   4122#define B_LOAD_COEF_CFIR GENMASK(1, 0)
   4123#define B_LOAD_COEF_DI BIT(1)
   4124#define B_LOAD_COEF_AUTO BIT(0)
   4125#define R_DPK_GL 0x81F0
   4126#define B_DPK_GL_A0 GENMASK(31, 28)
   4127#define B_DPK_GL_A1 GENMASK(17, 0)
   4128#define R_RPT_PER 0x81FC
   4129#define B_RPT_PER_TSSI GENMASK(28, 16)
   4130#define B_RPT_PER_OF GENMASK(15, 8)
   4131#define B_RPT_PER_TH GENMASK(5, 0)
   4132#define R_RXCFIR_P0C0 0x8D40
   4133#define R_RXCFIR_P0C1 0x8D84
   4134#define R_RXCFIR_P0C2 0x8DC8
   4135#define R_RXCFIR_P0C3 0x8E0C
   4136#define R_TXCFIR_P0C0 0x8F50
   4137#define R_TXCFIR_P0C1 0x8F84
   4138#define R_TXCFIR_P0C2 0x8FB8
   4139#define R_TXCFIR_P0C3 0x8FEC
   4140#define R_RXCFIR_P1C0 0x9140
   4141#define R_RXCFIR_P1C1 0x9184
   4142#define R_RXCFIR_P1C2 0x91C8
   4143#define R_RXCFIR_P1C3 0x920C
   4144#define R_TXCFIR_P1C0 0x9350
   4145#define R_TXCFIR_P1C1 0x9384
   4146#define R_TXCFIR_P1C2 0x93B8
   4147#define R_TXCFIR_P1C3 0x93EC
   4148#define R_IQKINF 0x9FE0
   4149#define B_IQKINF_VER GENMASK(31, 24)
   4150#define B_IQKINF_FAIL_RXGRP GENMASK(23, 16)
   4151#define B_IQKINF_FAIL_TXGRP GENMASK(15, 8)
   4152#define B_IQKINF_FAIL GENMASK(3, 0)
   4153#define B_IQKINF_F_RX BIT(3)
   4154#define B_IQKINF_FTX BIT(2)
   4155#define B_IQKINF_FFIN BIT(1)
   4156#define B_IQKINF_FCOR BIT(0)
   4157#define R_IQKCH 0x9FE4
   4158#define B_IQKCH_CH GENMASK(15, 8)
   4159#define B_IQKCH_BW GENMASK(7, 4)
   4160#define B_IQKCH_BAND GENMASK(3, 0)
   4161#define R_IQKINF2 0x9FE8
   4162#define B_IQKINF2_FCNT GENMASK(23, 16)
   4163#define B_IQKINF2_KCNT GENMASK(15, 8)
   4164#define B_IQKINF2_NCTLV GENMASK(7, 0)
   4165#define R_DCOF0 0xC000
   4166#define B_DCOF0_V GENMASK(4, 1)
   4167#define R_DCOF1 0xC004
   4168#define B_DCOF1_S BIT(0)
   4169#define R_DCOF8 0xC020
   4170#define B_DCOF8_V GENMASK(4, 1)
   4171#define R_DACK_S0P0 0xC040
   4172#define B_DACK_S0P0_OK BIT(31)
   4173#define R_DACK_BIAS00 0xc048
   4174#define B_DACK_BIAS00 GENMASK(11, 2)
   4175#define R_DACK_S0P2 0xC05C
   4176#define B_DACK_S0M0 GENMASK(31, 24)
   4177#define B_DACK_S0P2_OK BIT(2)
   4178#define R_DACK_DADCK00 0xC060
   4179#define B_DACK_DADCK00 GENMASK(31, 24)
   4180#define R_DACK_S0P1 0xC064
   4181#define B_DACK_S0P1_OK BIT(31)
   4182#define R_DACK_BIAS01 0xC06C
   4183#define B_DACK_BIAS01 GENMASK(11, 2)
   4184#define R_DACK_S0P3 0xC080
   4185#define B_DACK_S0M1 GENMASK(31, 24)
   4186#define B_DACK_S0P3_OK BIT(2)
   4187#define R_DACK_DADCK01 0xC084
   4188#define B_DACK_DADCK01 GENMASK(31, 24)
   4189#define R_DRCK 0xC0C4
   4190#define B_DRCK_IDLE BIT(9)
   4191#define B_DRCK_EN BIT(6)
   4192#define B_DRCK_VAL GENMASK(4, 0)
   4193#define R_DRCK_RES 0xC0C8
   4194#define B_DRCK_RES GENMASK(19, 15)
   4195#define B_DRCK_POL BIT(3)
   4196#define R_PATH0_SAMPL_DLY_T_V1 0xC0D4
   4197#define B_PATH0_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26)
   4198#define R_P0_CFCH_BW0 0xC0D4
   4199#define B_P0_CFCH_BW0 GENMASK(27, 26)
   4200#define R_P0_CFCH_BW1 0xC0D8
   4201#define B_P0_CFCH_BW1 GENMASK(8, 5)
   4202#define R_ADDCK0 0xC0F4
   4203#define B_ADDCK0 GENMASK(9, 8)
   4204#define B_ADDCK0_EN BIT(4)
   4205#define B_ADDCK0_RST BIT(2)
   4206#define R_ADDCK0_RL 0xC0F8
   4207#define B_ADDCK0_RLS GENMASK(29, 28)
   4208#define B_ADDCK0_RL1 GENMASK(27, 18)
   4209#define B_ADDCK0_RL0 GENMASK(17, 8)
   4210#define R_ADDCKR0 0xC0FC
   4211#define B_ADDCKR0_A0 GENMASK(19, 10)
   4212#define B_ADDCKR0_A1 GENMASK(9, 0)
   4213#define R_DACK10 0xC100
   4214#define B_DACK10 GENMASK(4, 1)
   4215#define R_DACK1_K 0xc104
   4216#define B_DACK1_EN BIT(0)
   4217#define R_DACK11 0xC120
   4218#define B_DACK11 GENMASK(4, 1)
   4219#define R_DACK_S1P0 0xC140
   4220#define B_DACK_S1P0_OK BIT(31)
   4221#define R_DACK_BIAS10 0xC148
   4222#define B_DACK_BIAS10 GENMASK(11, 2)
   4223#define R_DACK10S 0xC15C
   4224#define B_DACK10S GENMASK(31, 24)
   4225#define R_DACK_S1P2 0xC15C
   4226#define B_DACK_S1P2_OK BIT(2)
   4227#define R_DACK_DADCK10 0xC160
   4228#define B_DACK_DADCK10 GENMASK(31, 24)
   4229#define R_DACK_S1P1 0xC164
   4230#define B_DACK_S1P1_OK BIT(31)
   4231#define R_DACK_BIAS11 0xC16C
   4232#define B_DACK_BIAS11 GENMASK(11, 2)
   4233#define R_DACK11S 0xC180
   4234#define B_DACK11S GENMASK(31, 24)
   4235#define R_DACK_S1P3 0xC180
   4236#define B_DACK_S1P3_OK BIT(2)
   4237#define R_DACK_DADCK11 0xC184
   4238#define B_DACK_DADCK11 GENMASK(31, 24)
   4239#define R_PATH1_SAMPL_DLY_T_V1 0xC1D4
   4240#define B_PATH1_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26)
   4241#define R_PATH0_BW_SEL_V1 0xC0D8
   4242#define B_PATH0_BW_SEL_MSK_V1 GENMASK(8, 5)
   4243#define R_PATH1_BW_SEL_V1 0xC1D8
   4244#define B_PATH1_BW_SEL_MSK_V1 GENMASK(8, 5)
   4245#define R_ADDCK1 0xC1F4
   4246#define B_ADDCK1 GENMASK(9, 8)
   4247#define B_ADDCK1_EN BIT(4)
   4248#define B_ADDCK1_RST BIT(2)
   4249#define R_ADDCK1_RL 0xC1F8
   4250#define B_ADDCK1_RLS GENMASK(29, 28)
   4251#define B_ADDCK1_RL1 GENMASK(27, 18)
   4252#define B_ADDCK1_RL0 GENMASK(17, 8)
   4253#define R_ADDCKR1 0xC1fC
   4254#define B_ADDCKR1_A0 GENMASK(19, 10)
   4255#define B_ADDCKR1_A1 GENMASK(9, 0)
   4256
   4257/* WiFi CPU local domain */
   4258#define R_AX_WDT_CTRL 0x0040
   4259#define B_AX_WDT_EN BIT(31)
   4260#define B_AX_WDT_OPT_RESET_PLATFORM_EN BIT(29)
   4261#define B_AX_IO_HANG_IMR BIT(27)
   4262#define B_AX_IO_HANG_CMAC_RDATA_EN BIT(26)
   4263#define B_AX_IO_HANG_DMAC_EN BIT(25)
   4264#define B_AX_WDT_CLR BIT(16)
   4265#define B_AX_WDT_COUNT_MASK GENMASK(15, 0)
   4266#define WDT_CTRL_ALL_DIS 0
   4267
   4268#define R_AX_WDT_STATUS 0x0044
   4269#define B_AX_FS_WDT_INT BIT(8)
   4270#define B_AX_FS_WDT_INT_MSK BIT(0)
   4271
   4272#endif