cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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rtw8852a.h (2422B)

      1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
      2/* Copyright(c) 2019-2020  Realtek Corporation
      3 */
      4
      5#ifndef __RTW89_8852A_H__
      6#define __RTW89_8852A_H__
      7
      8#include "core.h"
      9
     10#define RF_PATH_NUM_8852A 2
     11#define NTX_NUM_8852A 2
     12
     13enum rtw8852a_pmac_mode {
     14	NONE_TEST,
     15	PKTS_TX,
     16	PKTS_RX,
     17	CONT_TX
     18};
     19
     20struct rtw8852au_efuse {
     21	u8 rsvd[0x38];
     22	u8 mac_addr[ETH_ALEN];
     23};
     24
     25struct rtw8852ae_efuse {
     26	u8 mac_addr[ETH_ALEN];
     27};
     28
     29struct rtw8852a_tssi_offset {
     30	u8 cck_tssi[TSSI_CCK_CH_GROUP_NUM];
     31	u8 bw40_tssi[TSSI_MCS_2G_CH_GROUP_NUM];
     32	u8 rsvd[7];
     33	u8 bw40_1s_tssi_5g[TSSI_MCS_5G_CH_GROUP_NUM];
     34} __packed;
     35
     36struct rtw8852a_efuse {
     37	u8 rsvd[0x210];
     38	struct rtw8852a_tssi_offset path_a_tssi;
     39	u8 rsvd1[10];
     40	struct rtw8852a_tssi_offset path_b_tssi;
     41	u8 rsvd2[94];
     42	u8 channel_plan;
     43	u8 xtal_k;
     44	u8 rsvd3;
     45	u8 iqk_lck;
     46	u8 rsvd4[5];
     47	u8 reg_setting:2;
     48	u8 tx_diversity:1;
     49	u8 rx_diversity:2;
     50	u8 ac_mode:1;
     51	u8 module_type:2;
     52	u8 rsvd5;
     53	u8 shared_ant:1;
     54	u8 coex_type:3;
     55	u8 ant_iso:1;
     56	u8 radio_on_off:1;
     57	u8 rsvd6:2;
     58	u8 eeprom_version;
     59	u8 customer_id;
     60	u8 tx_bb_swing_2g;
     61	u8 tx_bb_swing_5g;
     62	u8 tx_cali_pwr_trk_mode;
     63	u8 trx_path_selection;
     64	u8 rfe_type;
     65	u8 country_code[2];
     66	u8 rsvd7[3];
     67	u8 path_a_therm;
     68	u8 path_b_therm;
     69	u8 rsvd8[46];
     70	u8 path_a_cck_pwr_idx[6];
     71	u8 path_a_bw40_1tx_pwr_idx[5];
     72	u8 path_a_ofdm_1tx_pwr_idx_diff:4;
     73	u8 path_a_bw20_1tx_pwr_idx_diff:4;
     74	u8 path_a_bw20_2tx_pwr_idx_diff:4;
     75	u8 path_a_bw40_2tx_pwr_idx_diff:4;
     76	u8 path_a_cck_2tx_pwr_idx_diff:4;
     77	u8 path_a_ofdm_2tx_pwr_idx_diff:4;
     78	u8 rsvd9[0xf2];
     79	union {
     80		struct rtw8852au_efuse u;
     81		struct rtw8852ae_efuse e;
     82	};
     83} __packed;
     84
     85struct rtw8852a_bb_pmac_info {
     86	u8 en_pmac_tx:1;
     87	u8 is_cck:1;
     88	u8 mode:3;
     89	u8 rsvd:3;
     90	u16 tx_cnt;
     91	u16 period;
     92	u16 tx_time;
     93	u8 duty_cycle;
     94};
     95
     96extern const struct rtw89_chip_info rtw8852a_chip_info;
     97
     98void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev);
     99void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev,
    100			     struct rtw8852a_bb_pmac_info *tx_info,
    101			     enum rtw89_phy_idx idx);
    102void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable,
    103				 u16 tx_cnt, u16 period, u16 tx_time,
    104				 enum rtw89_phy_idx idx);
    105void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm,
    106			   enum rtw89_phy_idx idx);
    107void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path);
    108void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev,
    109				enum rtw89_phy_idx idx, u8 mode);
    110
    111#endif