cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

nfcmrvl.h (2442B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * Marvell NFC driver
      4 *
      5 * Copyright (C) 2014-2015, Marvell International Ltd.
      6 */
      7
      8#ifndef _NFCMRVL_H_
      9#define _NFCMRVL_H_
     10
     11#include <linux/platform_data/nfcmrvl.h>
     12
     13#include "fw_dnld.h"
     14
     15/* Define private flags: */
     16#define NFCMRVL_NCI_RUNNING			1
     17#define NFCMRVL_PHY_ERROR			2
     18
     19#define NFCMRVL_EXT_COEX_ID			0xE0
     20#define NFCMRVL_NOT_ALLOWED_ID			0xE1
     21#define NFCMRVL_ACTIVE_ID			0xE2
     22#define NFCMRVL_EXT_COEX_ENABLE			1
     23#define NFCMRVL_GPIO_PIN_NFC_NOT_ALLOWED	0xA
     24#define NFCMRVL_GPIO_PIN_NFC_ACTIVE		0xB
     25#define NFCMRVL_NCI_MAX_EVENT_SIZE		260
     26
     27/*
     28 * NCI FW Parameters
     29 */
     30
     31#define NFCMRVL_PB_BAIL_OUT			0x11
     32#define NFCMRVL_PROP_REF_CLOCK			0xF0
     33#define NFCMRVL_PROP_SET_HI_CONFIG		0xF1
     34
     35/*
     36 * HCI defines
     37 */
     38
     39#define NFCMRVL_HCI_EVENT_HEADER_SIZE		0x04
     40#define NFCMRVL_HCI_EVENT_CODE			0x04
     41#define NFCMRVL_HCI_NFC_EVENT_CODE		0xFF
     42#define NFCMRVL_HCI_COMMAND_CODE		0x01
     43#define NFCMRVL_HCI_OGF				0x81
     44#define NFCMRVL_HCI_OCF				0xFE
     45
     46enum nfcmrvl_phy {
     47	NFCMRVL_PHY_USB		= 0,
     48	NFCMRVL_PHY_UART	= 1,
     49	NFCMRVL_PHY_I2C		= 2,
     50	NFCMRVL_PHY_SPI		= 3,
     51};
     52
     53struct nfcmrvl_private {
     54
     55	unsigned long flags;
     56
     57	/* Platform configuration */
     58	struct nfcmrvl_platform_data config;
     59
     60	/* Parent dev */
     61	struct nci_dev *ndev;
     62
     63	/* FW download context */
     64	struct nfcmrvl_fw_dnld fw_dnld;
     65
     66	/* FW download support */
     67	bool support_fw_dnld;
     68
     69	/*
     70	 * PHY related information
     71	 */
     72
     73	/* PHY driver context */
     74	void *drv_data;
     75	/* PHY device */
     76	struct device *dev;
     77	/* PHY type */
     78	enum nfcmrvl_phy phy;
     79	/* Low level driver ops */
     80	const struct nfcmrvl_if_ops *if_ops;
     81};
     82
     83struct nfcmrvl_if_ops {
     84	int (*nci_open) (struct nfcmrvl_private *priv);
     85	int (*nci_close) (struct nfcmrvl_private *priv);
     86	int (*nci_send) (struct nfcmrvl_private *priv, struct sk_buff *skb);
     87	void (*nci_update_config)(struct nfcmrvl_private *priv,
     88				  const void *param);
     89};
     90
     91void nfcmrvl_nci_unregister_dev(struct nfcmrvl_private *priv);
     92int nfcmrvl_nci_recv_frame(struct nfcmrvl_private *priv, struct sk_buff *skb);
     93struct nfcmrvl_private *nfcmrvl_nci_register_dev(enum nfcmrvl_phy phy,
     94				void *drv_data,
     95				const struct nfcmrvl_if_ops *ops,
     96				struct device *dev,
     97				const struct nfcmrvl_platform_data *pdata);
     98
     99
    100void nfcmrvl_chip_reset(struct nfcmrvl_private *priv);
    101void nfcmrvl_chip_halt(struct nfcmrvl_private *priv);
    102
    103int nfcmrvl_parse_dt(struct device_node *node,
    104		     struct nfcmrvl_platform_data *pdata);
    105
    106#endif