cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pci-layerscape-ep.c (4627B)

      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * PCIe controller EP driver for Freescale Layerscape SoCs
      4 *
      5 * Copyright (C) 2018 NXP Semiconductor.
      6 *
      7 * Author: Xiaowei Bao <xiaowei.bao@nxp.com>
      8 */
      9
     10#include <linux/kernel.h>
     11#include <linux/init.h>
     12#include <linux/of_pci.h>
     13#include <linux/of_platform.h>
     14#include <linux/of_address.h>
     15#include <linux/pci.h>
     16#include <linux/platform_device.h>
     17#include <linux/resource.h>
     18
     19#include "pcie-designware.h"
     20
     21#define to_ls_pcie_ep(x)	dev_get_drvdata((x)->dev)
     22
     23struct ls_pcie_ep_drvdata {
     24	u32				func_offset;
     25	const struct dw_pcie_ep_ops	*ops;
     26	const struct dw_pcie_ops	*dw_pcie_ops;
     27};
     28
     29struct ls_pcie_ep {
     30	struct dw_pcie			*pci;
     31	struct pci_epc_features		*ls_epc;
     32	const struct ls_pcie_ep_drvdata *drvdata;
     33};
     34
     35static int ls_pcie_establish_link(struct dw_pcie *pci)
     36{
     37	return 0;
     38}
     39
     40static const struct dw_pcie_ops dw_ls_pcie_ep_ops = {
     41	.start_link = ls_pcie_establish_link,
     42};
     43
     44static const struct pci_epc_features*
     45ls_pcie_ep_get_features(struct dw_pcie_ep *ep)
     46{
     47	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
     48	struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
     49
     50	return pcie->ls_epc;
     51}
     52
     53static void ls_pcie_ep_init(struct dw_pcie_ep *ep)
     54{
     55	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
     56	struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
     57	struct dw_pcie_ep_func *ep_func;
     58	enum pci_barno bar;
     59
     60	ep_func = dw_pcie_ep_get_func_from_ep(ep, 0);
     61	if (!ep_func)
     62		return;
     63
     64	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
     65		dw_pcie_ep_reset_bar(pci, bar);
     66
     67	pcie->ls_epc->msi_capable = ep_func->msi_cap ? true : false;
     68	pcie->ls_epc->msix_capable = ep_func->msix_cap ? true : false;
     69}
     70
     71static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
     72				enum pci_epc_irq_type type, u16 interrupt_num)
     73{
     74	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
     75
     76	switch (type) {
     77	case PCI_EPC_IRQ_LEGACY:
     78		return dw_pcie_ep_raise_legacy_irq(ep, func_no);
     79	case PCI_EPC_IRQ_MSI:
     80		return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
     81	case PCI_EPC_IRQ_MSIX:
     82		return dw_pcie_ep_raise_msix_irq_doorbell(ep, func_no,
     83							  interrupt_num);
     84	default:
     85		dev_err(pci->dev, "UNKNOWN IRQ type\n");
     86		return -EINVAL;
     87	}
     88}
     89
     90static unsigned int ls_pcie_ep_func_conf_select(struct dw_pcie_ep *ep,
     91						u8 func_no)
     92{
     93	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
     94	struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
     95
     96	WARN_ON(func_no && !pcie->drvdata->func_offset);
     97	return pcie->drvdata->func_offset * func_no;
     98}
     99
    100static const struct dw_pcie_ep_ops ls_pcie_ep_ops = {
    101	.ep_init = ls_pcie_ep_init,
    102	.raise_irq = ls_pcie_ep_raise_irq,
    103	.get_features = ls_pcie_ep_get_features,
    104	.func_conf_select = ls_pcie_ep_func_conf_select,
    105};
    106
    107static const struct ls_pcie_ep_drvdata ls1_ep_drvdata = {
    108	.ops = &ls_pcie_ep_ops,
    109	.dw_pcie_ops = &dw_ls_pcie_ep_ops,
    110};
    111
    112static const struct ls_pcie_ep_drvdata ls2_ep_drvdata = {
    113	.func_offset = 0x20000,
    114	.ops = &ls_pcie_ep_ops,
    115	.dw_pcie_ops = &dw_ls_pcie_ep_ops,
    116};
    117
    118static const struct ls_pcie_ep_drvdata lx2_ep_drvdata = {
    119	.func_offset = 0x8000,
    120	.ops = &ls_pcie_ep_ops,
    121	.dw_pcie_ops = &dw_ls_pcie_ep_ops,
    122};
    123
    124static const struct of_device_id ls_pcie_ep_of_match[] = {
    125	{ .compatible = "fsl,ls1046a-pcie-ep", .data = &ls1_ep_drvdata },
    126	{ .compatible = "fsl,ls1088a-pcie-ep", .data = &ls2_ep_drvdata },
    127	{ .compatible = "fsl,ls2088a-pcie-ep", .data = &ls2_ep_drvdata },
    128	{ .compatible = "fsl,lx2160ar2-pcie-ep", .data = &lx2_ep_drvdata },
    129	{ },
    130};
    131
    132static int __init ls_pcie_ep_probe(struct platform_device *pdev)
    133{
    134	struct device *dev = &pdev->dev;
    135	struct dw_pcie *pci;
    136	struct ls_pcie_ep *pcie;
    137	struct pci_epc_features *ls_epc;
    138	struct resource *dbi_base;
    139
    140	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
    141	if (!pcie)
    142		return -ENOMEM;
    143
    144	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
    145	if (!pci)
    146		return -ENOMEM;
    147
    148	ls_epc = devm_kzalloc(dev, sizeof(*ls_epc), GFP_KERNEL);
    149	if (!ls_epc)
    150		return -ENOMEM;
    151
    152	pcie->drvdata = of_device_get_match_data(dev);
    153
    154	pci->dev = dev;
    155	pci->ops = pcie->drvdata->dw_pcie_ops;
    156
    157	ls_epc->bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4);
    158
    159	pcie->pci = pci;
    160	pcie->ls_epc = ls_epc;
    161
    162	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
    163	pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
    164	if (IS_ERR(pci->dbi_base))
    165		return PTR_ERR(pci->dbi_base);
    166
    167	pci->ep.ops = &ls_pcie_ep_ops;
    168
    169	platform_set_drvdata(pdev, pcie);
    170
    171	return dw_pcie_ep_init(&pci->ep);
    172}
    173
    174static struct platform_driver ls_pcie_ep_driver = {
    175	.driver = {
    176		.name = "layerscape-pcie-ep",
    177		.of_match_table = ls_pcie_ep_of_match,
    178		.suppress_bind_attrs = true,
    179	},
    180};
    181builtin_platform_driver_probe(ls_pcie_ep_driver, ls_pcie_ep_probe);