cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pci-layerscape.c (3696B)

      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * PCIe host controller driver for Freescale Layerscape SoCs
      4 *
      5 * Copyright (C) 2014 Freescale Semiconductor.
      6 * Copyright 2021 NXP
      7 *
      8 * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
      9 */
     10
     11#include <linux/kernel.h>
     12#include <linux/interrupt.h>
     13#include <linux/init.h>
     14#include <linux/of_pci.h>
     15#include <linux/of_platform.h>
     16#include <linux/of_irq.h>
     17#include <linux/of_address.h>
     18#include <linux/pci.h>
     19#include <linux/platform_device.h>
     20#include <linux/resource.h>
     21#include <linux/mfd/syscon.h>
     22#include <linux/regmap.h>
     23
     24#include "pcie-designware.h"
     25
     26/* PEX Internal Configuration Registers */
     27#define PCIE_STRFMR1		0x71c /* Symbol Timer & Filter Mask Register1 */
     28#define PCIE_ABSERR		0x8d0 /* Bridge Slave Error Response Register */
     29#define PCIE_ABSERR_SETTING	0x9401 /* Forward error of non-posted request */
     30
     31#define PCIE_IATU_NUM		6
     32
     33struct ls_pcie {
     34	struct dw_pcie *pci;
     35};
     36
     37#define to_ls_pcie(x)	dev_get_drvdata((x)->dev)
     38
     39static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
     40{
     41	struct dw_pcie *pci = pcie->pci;
     42	u32 header_type;
     43
     44	header_type = ioread8(pci->dbi_base + PCI_HEADER_TYPE);
     45	header_type &= 0x7f;
     46
     47	return header_type == PCI_HEADER_TYPE_BRIDGE;
     48}
     49
     50/* Clear multi-function bit */
     51static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
     52{
     53	struct dw_pcie *pci = pcie->pci;
     54
     55	iowrite8(PCI_HEADER_TYPE_BRIDGE, pci->dbi_base + PCI_HEADER_TYPE);
     56}
     57
     58/* Drop MSG TLP except for Vendor MSG */
     59static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
     60{
     61	u32 val;
     62	struct dw_pcie *pci = pcie->pci;
     63
     64	val = ioread32(pci->dbi_base + PCIE_STRFMR1);
     65	val &= 0xDFFFFFFF;
     66	iowrite32(val, pci->dbi_base + PCIE_STRFMR1);
     67}
     68
     69/* Forward error response of outbound non-posted requests */
     70static void ls_pcie_fix_error_response(struct ls_pcie *pcie)
     71{
     72	struct dw_pcie *pci = pcie->pci;
     73
     74	iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR);
     75}
     76
     77static int ls_pcie_host_init(struct pcie_port *pp)
     78{
     79	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
     80	struct ls_pcie *pcie = to_ls_pcie(pci);
     81
     82	ls_pcie_fix_error_response(pcie);
     83
     84	dw_pcie_dbi_ro_wr_en(pci);
     85	ls_pcie_clear_multifunction(pcie);
     86	dw_pcie_dbi_ro_wr_dis(pci);
     87
     88	ls_pcie_drop_msg_tlp(pcie);
     89
     90	return 0;
     91}
     92
     93static const struct dw_pcie_host_ops ls_pcie_host_ops = {
     94	.host_init = ls_pcie_host_init,
     95};
     96
     97static const struct of_device_id ls_pcie_of_match[] = {
     98	{ .compatible = "fsl,ls1012a-pcie", },
     99	{ .compatible = "fsl,ls1021a-pcie", },
    100	{ .compatible = "fsl,ls1028a-pcie", },
    101	{ .compatible = "fsl,ls1043a-pcie", },
    102	{ .compatible = "fsl,ls1046a-pcie", },
    103	{ .compatible = "fsl,ls2080a-pcie", },
    104	{ .compatible = "fsl,ls2085a-pcie", },
    105	{ .compatible = "fsl,ls2088a-pcie", },
    106	{ .compatible = "fsl,ls1088a-pcie", },
    107	{ },
    108};
    109
    110static int ls_pcie_probe(struct platform_device *pdev)
    111{
    112	struct device *dev = &pdev->dev;
    113	struct dw_pcie *pci;
    114	struct ls_pcie *pcie;
    115	struct resource *dbi_base;
    116
    117	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
    118	if (!pcie)
    119		return -ENOMEM;
    120
    121	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
    122	if (!pci)
    123		return -ENOMEM;
    124
    125	pci->dev = dev;
    126	pci->pp.ops = &ls_pcie_host_ops;
    127
    128	pcie->pci = pci;
    129
    130	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
    131	pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
    132	if (IS_ERR(pci->dbi_base))
    133		return PTR_ERR(pci->dbi_base);
    134
    135	if (!ls_pcie_is_bridge(pcie))
    136		return -ENODEV;
    137
    138	platform_set_drvdata(pdev, pcie);
    139
    140	return dw_pcie_host_init(&pci->pp);
    141}
    142
    143static struct platform_driver ls_pcie_driver = {
    144	.probe = ls_pcie_probe,
    145	.driver = {
    146		.name = "layerscape-pcie",
    147		.of_match_table = ls_pcie_of_match,
    148		.suppress_bind_attrs = true,
    149	},
    150};
    151builtin_platform_driver(ls_pcie_driver);