cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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msi.h (1228B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2
      3#include <linux/pci.h>
      4#include <linux/msi.h>
      5
      6#define msix_table_size(flags)	((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
      7
      8extern int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
      9extern void pci_msi_teardown_msi_irqs(struct pci_dev *dev);
     10
     11#ifdef CONFIG_PCI_MSI_ARCH_FALLBACKS
     12extern int pci_msi_legacy_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
     13extern void pci_msi_legacy_teardown_msi_irqs(struct pci_dev *dev);
     14#else
     15static inline int pci_msi_legacy_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
     16{
     17	WARN_ON_ONCE(1);
     18	return -ENODEV;
     19}
     20
     21static inline void pci_msi_legacy_teardown_msi_irqs(struct pci_dev *dev)
     22{
     23	WARN_ON_ONCE(1);
     24}
     25#endif
     26
     27/*
     28 * PCI 2.3 does not specify mask bits for each MSI interrupt.  Attempting to
     29 * mask all MSI interrupts by clearing the MSI enable bit does not work
     30 * reliably as devices without an INTx disable bit will then generate a
     31 * level IRQ which will never be cleared.
     32 */
     33static inline __attribute_const__ u32 msi_multi_mask(struct msi_desc *desc)
     34{
     35	/* Don't shift by >= width of type */
     36	if (desc->pci.msi_attrib.multi_cap >= 5)
     37		return 0xffffffff;
     38	return (1 << (1 << desc->pci.msi_attrib.multi_cap)) - 1;
     39}