cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

pci-bridge-emul.c (17722B)


      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Copyright (C) 2018 Marvell
      4 *
      5 * Author: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
      6 *
      7 * This file helps PCI controller drivers implement a fake root port
      8 * PCI bridge when the HW doesn't provide such a root port PCI
      9 * bridge.
     10 *
     11 * It emulates a PCI bridge by providing a fake PCI configuration
     12 * space (and optionally a PCIe capability configuration space) in
     13 * memory. By default the read/write operations simply read and update
     14 * this fake configuration space in memory. However, PCI controller
     15 * drivers can provide through the 'struct pci_sw_bridge_ops'
     16 * structure a set of operations to override or complement this
     17 * default behavior.
     18 */
     19
     20#include <linux/pci.h>
     21#include "pci-bridge-emul.h"
     22
     23#define PCI_BRIDGE_CONF_END	PCI_STD_HEADER_SIZEOF
     24#define PCI_CAP_SSID_SIZEOF	(PCI_SSVID_DEVICE_ID + 2)
     25#define PCI_CAP_SSID_START	PCI_BRIDGE_CONF_END
     26#define PCI_CAP_SSID_END	(PCI_CAP_SSID_START + PCI_CAP_SSID_SIZEOF)
     27#define PCI_CAP_PCIE_SIZEOF	(PCI_EXP_SLTSTA2 + 2)
     28#define PCI_CAP_PCIE_START	PCI_CAP_SSID_END
     29#define PCI_CAP_PCIE_END	(PCI_CAP_PCIE_START + PCI_CAP_PCIE_SIZEOF)
     30
     31/**
     32 * struct pci_bridge_reg_behavior - register bits behaviors
     33 * @ro:		Read-Only bits
     34 * @rw:		Read-Write bits
     35 * @w1c:	Write-1-to-Clear bits
     36 *
     37 * Reads and Writes will be filtered by specified behavior. All other bits not
     38 * declared are assumed 'Reserved' and will return 0 on reads, per PCIe 5.0:
     39 * "Reserved register fields must be read only and must return 0 (all 0's for
     40 * multi-bit fields) when read".
     41 */
     42struct pci_bridge_reg_behavior {
     43	/* Read-only bits */
     44	u32 ro;
     45
     46	/* Read-write bits */
     47	u32 rw;
     48
     49	/* Write-1-to-clear bits */
     50	u32 w1c;
     51};
     52
     53static const
     54struct pci_bridge_reg_behavior pci_regs_behavior[PCI_STD_HEADER_SIZEOF / 4] = {
     55	[PCI_VENDOR_ID / 4] = { .ro = ~0 },
     56	[PCI_COMMAND / 4] = {
     57		.rw = (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
     58		       PCI_COMMAND_MASTER | PCI_COMMAND_PARITY |
     59		       PCI_COMMAND_SERR),
     60		.ro = ((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE |
     61			PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT |
     62			PCI_COMMAND_FAST_BACK) |
     63		       (PCI_STATUS_CAP_LIST | PCI_STATUS_66MHZ |
     64			PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MASK) << 16),
     65		.w1c = PCI_STATUS_ERROR_BITS << 16,
     66	},
     67	[PCI_CLASS_REVISION / 4] = { .ro = ~0 },
     68
     69	/*
     70	 * Cache Line Size register: implement as read-only, we do not
     71	 * pretend implementing "Memory Write and Invalidate"
     72	 * transactions"
     73	 *
     74	 * Latency Timer Register: implemented as read-only, as "A
     75	 * bridge that is not capable of a burst transfer of more than
     76	 * two data phases on its primary interface is permitted to
     77	 * hardwire the Latency Timer to a value of 16 or less"
     78	 *
     79	 * Header Type: always read-only
     80	 *
     81	 * BIST register: implemented as read-only, as "A bridge that
     82	 * does not support BIST must implement this register as a
     83	 * read-only register that returns 0 when read"
     84	 */
     85	[PCI_CACHE_LINE_SIZE / 4] = { .ro = ~0 },
     86
     87	/*
     88	 * Base Address registers not used must be implemented as
     89	 * read-only registers that return 0 when read.
     90	 */
     91	[PCI_BASE_ADDRESS_0 / 4] = { .ro = ~0 },
     92	[PCI_BASE_ADDRESS_1 / 4] = { .ro = ~0 },
     93
     94	[PCI_PRIMARY_BUS / 4] = {
     95		/* Primary, secondary and subordinate bus are RW */
     96		.rw = GENMASK(24, 0),
     97		/* Secondary latency is read-only */
     98		.ro = GENMASK(31, 24),
     99	},
    100
    101	[PCI_IO_BASE / 4] = {
    102		/* The high four bits of I/O base/limit are RW */
    103		.rw = (GENMASK(15, 12) | GENMASK(7, 4)),
    104
    105		/* The low four bits of I/O base/limit are RO */
    106		.ro = (((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
    107			 PCI_STATUS_DEVSEL_MASK) << 16) |
    108		       GENMASK(11, 8) | GENMASK(3, 0)),
    109
    110		.w1c = PCI_STATUS_ERROR_BITS << 16,
    111	},
    112
    113	[PCI_MEMORY_BASE / 4] = {
    114		/* The high 12-bits of mem base/limit are RW */
    115		.rw = GENMASK(31, 20) | GENMASK(15, 4),
    116
    117		/* The low four bits of mem base/limit are RO */
    118		.ro = GENMASK(19, 16) | GENMASK(3, 0),
    119	},
    120
    121	[PCI_PREF_MEMORY_BASE / 4] = {
    122		/* The high 12-bits of pref mem base/limit are RW */
    123		.rw = GENMASK(31, 20) | GENMASK(15, 4),
    124
    125		/* The low four bits of pref mem base/limit are RO */
    126		.ro = GENMASK(19, 16) | GENMASK(3, 0),
    127	},
    128
    129	[PCI_PREF_BASE_UPPER32 / 4] = {
    130		.rw = ~0,
    131	},
    132
    133	[PCI_PREF_LIMIT_UPPER32 / 4] = {
    134		.rw = ~0,
    135	},
    136
    137	[PCI_IO_BASE_UPPER16 / 4] = {
    138		.rw = ~0,
    139	},
    140
    141	[PCI_CAPABILITY_LIST / 4] = {
    142		.ro = GENMASK(7, 0),
    143	},
    144
    145	/*
    146	 * If expansion ROM is unsupported then ROM Base Address register must
    147	 * be implemented as read-only register that return 0 when read, same
    148	 * as for unused Base Address registers.
    149	 */
    150	[PCI_ROM_ADDRESS1 / 4] = {
    151		.ro = ~0,
    152	},
    153
    154	/*
    155	 * Interrupt line (bits 7:0) are RW, interrupt pin (bits 15:8)
    156	 * are RO, and bridge control (31:16) are a mix of RW, RO,
    157	 * reserved and W1C bits
    158	 */
    159	[PCI_INTERRUPT_LINE / 4] = {
    160		/* Interrupt line is RW */
    161		.rw = (GENMASK(7, 0) |
    162		       ((PCI_BRIDGE_CTL_PARITY |
    163			 PCI_BRIDGE_CTL_SERR |
    164			 PCI_BRIDGE_CTL_ISA |
    165			 PCI_BRIDGE_CTL_VGA |
    166			 PCI_BRIDGE_CTL_MASTER_ABORT |
    167			 PCI_BRIDGE_CTL_BUS_RESET |
    168			 BIT(8) | BIT(9) | BIT(11)) << 16)),
    169
    170		/* Interrupt pin is RO */
    171		.ro = (GENMASK(15, 8) | ((PCI_BRIDGE_CTL_FAST_BACK) << 16)),
    172
    173		.w1c = BIT(10) << 16,
    174	},
    175};
    176
    177static const
    178struct pci_bridge_reg_behavior pcie_cap_regs_behavior[PCI_CAP_PCIE_SIZEOF / 4] = {
    179	[PCI_CAP_LIST_ID / 4] = {
    180		/*
    181		 * Capability ID, Next Capability Pointer and
    182		 * bits [14:0] of Capabilities register are all read-only.
    183		 * Bit 15 of Capabilities register is reserved.
    184		 */
    185		.ro = GENMASK(30, 0),
    186	},
    187
    188	[PCI_EXP_DEVCAP / 4] = {
    189		/*
    190		 * Bits [31:29] and [17:16] are reserved.
    191		 * Bits [27:18] are reserved for non-upstream ports.
    192		 * Bits 28 and [14:6] are reserved for non-endpoint devices.
    193		 * Other bits are read-only.
    194		 */
    195		.ro = BIT(15) | GENMASK(5, 0),
    196	},
    197
    198	[PCI_EXP_DEVCTL / 4] = {
    199		/*
    200		 * Device control register is RW, except bit 15 which is
    201		 * reserved for non-endpoints or non-PCIe-to-PCI/X bridges.
    202		 */
    203		.rw = GENMASK(14, 0),
    204
    205		/*
    206		 * Device status register has bits 6 and [3:0] W1C, [5:4] RO,
    207		 * the rest is reserved. Also bit 6 is reserved for non-upstream
    208		 * ports.
    209		 */
    210		.w1c = GENMASK(3, 0) << 16,
    211		.ro = GENMASK(5, 4) << 16,
    212	},
    213
    214	[PCI_EXP_LNKCAP / 4] = {
    215		/*
    216		 * All bits are RO, except bit 23 which is reserved and
    217		 * bit 18 which is reserved for non-upstream ports.
    218		 */
    219		.ro = lower_32_bits(~(BIT(23) | PCI_EXP_LNKCAP_CLKPM)),
    220	},
    221
    222	[PCI_EXP_LNKCTL / 4] = {
    223		/*
    224		 * Link control has bits [15:14], [11:3] and [1:0] RW, the
    225		 * rest is reserved. Bit 8 is reserved for non-upstream ports.
    226		 *
    227		 * Link status has bits [13:0] RO, and bits [15:14]
    228		 * W1C.
    229		 */
    230		.rw = GENMASK(15, 14) | GENMASK(11, 9) | GENMASK(7, 3) | GENMASK(1, 0),
    231		.ro = GENMASK(13, 0) << 16,
    232		.w1c = GENMASK(15, 14) << 16,
    233	},
    234
    235	[PCI_EXP_SLTCAP / 4] = {
    236		.ro = ~0,
    237	},
    238
    239	[PCI_EXP_SLTCTL / 4] = {
    240		/*
    241		 * Slot control has bits [14:0] RW, the rest is
    242		 * reserved.
    243		 *
    244		 * Slot status has bits 8 and [4:0] W1C, bits [7:5] RO, the
    245		 * rest is reserved.
    246		 */
    247		.rw = GENMASK(14, 0),
    248		.w1c = (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
    249			PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
    250			PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC) << 16,
    251		.ro = (PCI_EXP_SLTSTA_MRLSS | PCI_EXP_SLTSTA_PDS |
    252		       PCI_EXP_SLTSTA_EIS) << 16,
    253	},
    254
    255	[PCI_EXP_RTCTL / 4] = {
    256		/*
    257		 * Root control has bits [4:0] RW, the rest is
    258		 * reserved.
    259		 *
    260		 * Root capabilities has bit 0 RO, the rest is reserved.
    261		 */
    262		.rw = (PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
    263		       PCI_EXP_RTCTL_SEFEE | PCI_EXP_RTCTL_PMEIE |
    264		       PCI_EXP_RTCTL_CRSSVE),
    265		.ro = PCI_EXP_RTCAP_CRSVIS << 16,
    266	},
    267
    268	[PCI_EXP_RTSTA / 4] = {
    269		/*
    270		 * Root status has bits 17 and [15:0] RO, bit 16 W1C, the rest
    271		 * is reserved.
    272		 */
    273		.ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING,
    274		.w1c = PCI_EXP_RTSTA_PME,
    275	},
    276
    277	[PCI_EXP_DEVCAP2 / 4] = {
    278		/*
    279		 * Device capabilities 2 register has reserved bits [30:27].
    280		 * Also bits [26:24] are reserved for non-upstream ports.
    281		 */
    282		.ro = BIT(31) | GENMASK(23, 0),
    283	},
    284
    285	[PCI_EXP_DEVCTL2 / 4] = {
    286		/*
    287		 * Device control 2 register is RW. Bit 11 is reserved for
    288		 * non-upstream ports.
    289		 *
    290		 * Device status 2 register is reserved.
    291		 */
    292		.rw = GENMASK(15, 12) | GENMASK(10, 0),
    293	},
    294
    295	[PCI_EXP_LNKCAP2 / 4] = {
    296		/* Link capabilities 2 register has reserved bits [30:25] and 0. */
    297		.ro = BIT(31) | GENMASK(24, 1),
    298	},
    299
    300	[PCI_EXP_LNKCTL2 / 4] = {
    301		/*
    302		 * Link control 2 register is RW.
    303		 *
    304		 * Link status 2 register has bits 5, 15 W1C;
    305		 * bits 10, 11 reserved and others are RO.
    306		 */
    307		.rw = GENMASK(15, 0),
    308		.w1c = (BIT(15) | BIT(5)) << 16,
    309		.ro = (GENMASK(14, 12) | GENMASK(9, 6) | GENMASK(4, 0)) << 16,
    310	},
    311
    312	[PCI_EXP_SLTCAP2 / 4] = {
    313		/* Slot capabilities 2 register is reserved. */
    314	},
    315
    316	[PCI_EXP_SLTCTL2 / 4] = {
    317		/* Both Slot control 2 and Slot status 2 registers are reserved. */
    318	},
    319};
    320
    321static pci_bridge_emul_read_status_t
    322pci_bridge_emul_read_ssid(struct pci_bridge_emul *bridge, int reg, u32 *value)
    323{
    324	switch (reg) {
    325	case PCI_CAP_LIST_ID:
    326		*value = PCI_CAP_ID_SSVID |
    327			(bridge->has_pcie ? (PCI_CAP_PCIE_START << 8) : 0);
    328		return PCI_BRIDGE_EMUL_HANDLED;
    329
    330	case PCI_SSVID_VENDOR_ID:
    331		*value = bridge->subsystem_vendor_id |
    332			(bridge->subsystem_id << 16);
    333		return PCI_BRIDGE_EMUL_HANDLED;
    334
    335	default:
    336		return PCI_BRIDGE_EMUL_NOT_HANDLED;
    337	}
    338}
    339
    340/*
    341 * Initialize a pci_bridge_emul structure to represent a fake PCI
    342 * bridge configuration space. The caller needs to have initialized
    343 * the PCI configuration space with whatever values make sense
    344 * (typically at least vendor, device, revision), the ->ops pointer,
    345 * and optionally ->data and ->has_pcie.
    346 */
    347int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
    348			 unsigned int flags)
    349{
    350	BUILD_BUG_ON(sizeof(bridge->conf) != PCI_BRIDGE_CONF_END);
    351
    352	/*
    353	 * class_revision: Class is high 24 bits and revision is low 8 bit
    354	 * of this member, while class for PCI Bridge Normal Decode has the
    355	 * 24-bit value: PCI_CLASS_BRIDGE_PCI_NORMAL
    356	 */
    357	bridge->conf.class_revision |=
    358		cpu_to_le32(PCI_CLASS_BRIDGE_PCI_NORMAL << 8);
    359	bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE;
    360	bridge->conf.cache_line_size = 0x10;
    361	bridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST);
    362	bridge->pci_regs_behavior = kmemdup(pci_regs_behavior,
    363					    sizeof(pci_regs_behavior),
    364					    GFP_KERNEL);
    365	if (!bridge->pci_regs_behavior)
    366		return -ENOMEM;
    367
    368	if (bridge->subsystem_vendor_id)
    369		bridge->conf.capabilities_pointer = PCI_CAP_SSID_START;
    370	else if (bridge->has_pcie)
    371		bridge->conf.capabilities_pointer = PCI_CAP_PCIE_START;
    372	else
    373		bridge->conf.capabilities_pointer = 0;
    374
    375	if (bridge->conf.capabilities_pointer)
    376		bridge->conf.status |= cpu_to_le16(PCI_STATUS_CAP_LIST);
    377
    378	if (bridge->has_pcie) {
    379		bridge->pcie_conf.cap_id = PCI_CAP_ID_EXP;
    380		bridge->pcie_conf.cap |= cpu_to_le16(PCI_EXP_TYPE_ROOT_PORT << 4);
    381		bridge->pcie_cap_regs_behavior =
    382			kmemdup(pcie_cap_regs_behavior,
    383				sizeof(pcie_cap_regs_behavior),
    384				GFP_KERNEL);
    385		if (!bridge->pcie_cap_regs_behavior) {
    386			kfree(bridge->pci_regs_behavior);
    387			return -ENOMEM;
    388		}
    389		/* These bits are applicable only for PCI and reserved on PCIe */
    390		bridge->pci_regs_behavior[PCI_CACHE_LINE_SIZE / 4].ro &=
    391			~GENMASK(15, 8);
    392		bridge->pci_regs_behavior[PCI_COMMAND / 4].ro &=
    393			~((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE |
    394			   PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT |
    395			   PCI_COMMAND_FAST_BACK) |
    396			  (PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
    397			   PCI_STATUS_DEVSEL_MASK) << 16);
    398		bridge->pci_regs_behavior[PCI_PRIMARY_BUS / 4].ro &=
    399			~GENMASK(31, 24);
    400		bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro &=
    401			~((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
    402			   PCI_STATUS_DEVSEL_MASK) << 16);
    403		bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].rw &=
    404			~((PCI_BRIDGE_CTL_MASTER_ABORT |
    405			   BIT(8) | BIT(9) | BIT(11)) << 16);
    406		bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].ro &=
    407			~((PCI_BRIDGE_CTL_FAST_BACK) << 16);
    408		bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].w1c &=
    409			~(BIT(10) << 16);
    410	}
    411
    412	if (flags & PCI_BRIDGE_EMUL_NO_PREFMEM_FORWARD) {
    413		bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].ro = ~0;
    414		bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].rw = 0;
    415	}
    416
    417	if (flags & PCI_BRIDGE_EMUL_NO_IO_FORWARD) {
    418		bridge->pci_regs_behavior[PCI_COMMAND / 4].ro |= PCI_COMMAND_IO;
    419		bridge->pci_regs_behavior[PCI_COMMAND / 4].rw &= ~PCI_COMMAND_IO;
    420		bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro |= GENMASK(15, 0);
    421		bridge->pci_regs_behavior[PCI_IO_BASE / 4].rw &= ~GENMASK(15, 0);
    422		bridge->pci_regs_behavior[PCI_IO_BASE_UPPER16 / 4].ro = ~0;
    423		bridge->pci_regs_behavior[PCI_IO_BASE_UPPER16 / 4].rw = 0;
    424	}
    425
    426	return 0;
    427}
    428EXPORT_SYMBOL_GPL(pci_bridge_emul_init);
    429
    430/*
    431 * Cleanup a pci_bridge_emul structure that was previously initialized
    432 * using pci_bridge_emul_init().
    433 */
    434void pci_bridge_emul_cleanup(struct pci_bridge_emul *bridge)
    435{
    436	if (bridge->has_pcie)
    437		kfree(bridge->pcie_cap_regs_behavior);
    438	kfree(bridge->pci_regs_behavior);
    439}
    440EXPORT_SYMBOL_GPL(pci_bridge_emul_cleanup);
    441
    442/*
    443 * Should be called by the PCI controller driver when reading the PCI
    444 * configuration space of the fake bridge. It will call back the
    445 * ->ops->read_base or ->ops->read_pcie operations.
    446 */
    447int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
    448			      int size, u32 *value)
    449{
    450	int ret;
    451	int reg = where & ~3;
    452	pci_bridge_emul_read_status_t (*read_op)(struct pci_bridge_emul *bridge,
    453						 int reg, u32 *value);
    454	__le32 *cfgspace;
    455	const struct pci_bridge_reg_behavior *behavior;
    456
    457	if (reg < PCI_BRIDGE_CONF_END) {
    458		/* Emulated PCI space */
    459		read_op = bridge->ops->read_base;
    460		cfgspace = (__le32 *) &bridge->conf;
    461		behavior = bridge->pci_regs_behavior;
    462	} else if (reg >= PCI_CAP_SSID_START && reg < PCI_CAP_SSID_END && bridge->subsystem_vendor_id) {
    463		/* Emulated PCI Bridge Subsystem Vendor ID capability */
    464		reg -= PCI_CAP_SSID_START;
    465		read_op = pci_bridge_emul_read_ssid;
    466		cfgspace = NULL;
    467		behavior = NULL;
    468	} else if (reg >= PCI_CAP_PCIE_START && reg < PCI_CAP_PCIE_END && bridge->has_pcie) {
    469		/* Our emulated PCIe capability */
    470		reg -= PCI_CAP_PCIE_START;
    471		read_op = bridge->ops->read_pcie;
    472		cfgspace = (__le32 *) &bridge->pcie_conf;
    473		behavior = bridge->pcie_cap_regs_behavior;
    474	} else if (reg >= PCI_CFG_SPACE_SIZE && bridge->has_pcie) {
    475		/* PCIe extended capability space */
    476		reg -= PCI_CFG_SPACE_SIZE;
    477		read_op = bridge->ops->read_ext;
    478		cfgspace = NULL;
    479		behavior = NULL;
    480	} else {
    481		/* Not implemented */
    482		*value = 0;
    483		return PCIBIOS_SUCCESSFUL;
    484	}
    485
    486	if (read_op)
    487		ret = read_op(bridge, reg, value);
    488	else
    489		ret = PCI_BRIDGE_EMUL_NOT_HANDLED;
    490
    491	if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED) {
    492		if (cfgspace)
    493			*value = le32_to_cpu(cfgspace[reg / 4]);
    494		else
    495			*value = 0;
    496	}
    497
    498	/*
    499	 * Make sure we never return any reserved bit with a value
    500	 * different from 0.
    501	 */
    502	if (behavior)
    503		*value &= behavior[reg / 4].ro | behavior[reg / 4].rw |
    504			  behavior[reg / 4].w1c;
    505
    506	if (size == 1)
    507		*value = (*value >> (8 * (where & 3))) & 0xff;
    508	else if (size == 2)
    509		*value = (*value >> (8 * (where & 3))) & 0xffff;
    510	else if (size != 4)
    511		return PCIBIOS_BAD_REGISTER_NUMBER;
    512
    513	return PCIBIOS_SUCCESSFUL;
    514}
    515EXPORT_SYMBOL_GPL(pci_bridge_emul_conf_read);
    516
    517/*
    518 * Should be called by the PCI controller driver when writing the PCI
    519 * configuration space of the fake bridge. It will call back the
    520 * ->ops->write_base or ->ops->write_pcie operations.
    521 */
    522int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
    523			       int size, u32 value)
    524{
    525	int reg = where & ~3;
    526	int mask, ret, old, new, shift;
    527	void (*write_op)(struct pci_bridge_emul *bridge, int reg,
    528			 u32 old, u32 new, u32 mask);
    529	__le32 *cfgspace;
    530	const struct pci_bridge_reg_behavior *behavior;
    531
    532	ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old);
    533	if (ret != PCIBIOS_SUCCESSFUL)
    534		return ret;
    535
    536	if (reg < PCI_BRIDGE_CONF_END) {
    537		/* Emulated PCI space */
    538		write_op = bridge->ops->write_base;
    539		cfgspace = (__le32 *) &bridge->conf;
    540		behavior = bridge->pci_regs_behavior;
    541	} else if (reg >= PCI_CAP_PCIE_START && reg < PCI_CAP_PCIE_END && bridge->has_pcie) {
    542		/* Our emulated PCIe capability */
    543		reg -= PCI_CAP_PCIE_START;
    544		write_op = bridge->ops->write_pcie;
    545		cfgspace = (__le32 *) &bridge->pcie_conf;
    546		behavior = bridge->pcie_cap_regs_behavior;
    547	} else if (reg >= PCI_CFG_SPACE_SIZE && bridge->has_pcie) {
    548		/* PCIe extended capability space */
    549		reg -= PCI_CFG_SPACE_SIZE;
    550		write_op = bridge->ops->write_ext;
    551		cfgspace = NULL;
    552		behavior = NULL;
    553	} else {
    554		/* Not implemented */
    555		return PCIBIOS_SUCCESSFUL;
    556	}
    557
    558	shift = (where & 0x3) * 8;
    559
    560	if (size == 4)
    561		mask = 0xffffffff;
    562	else if (size == 2)
    563		mask = 0xffff << shift;
    564	else if (size == 1)
    565		mask = 0xff << shift;
    566	else
    567		return PCIBIOS_BAD_REGISTER_NUMBER;
    568
    569	if (behavior) {
    570		/* Keep all bits, except the RW bits */
    571		new = old & (~mask | ~behavior[reg / 4].rw);
    572
    573		/* Update the value of the RW bits */
    574		new |= (value << shift) & (behavior[reg / 4].rw & mask);
    575
    576		/* Clear the W1C bits */
    577		new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));
    578	} else {
    579		new = old & ~mask;
    580		new |= (value << shift) & mask;
    581	}
    582
    583	if (cfgspace) {
    584		/* Save the new value with the cleared W1C bits into the cfgspace */
    585		cfgspace[reg / 4] = cpu_to_le32(new);
    586	}
    587
    588	if (behavior) {
    589		/*
    590		 * Clear the W1C bits not specified by the write mask, so that the
    591		 * write_op() does not clear them.
    592		 */
    593		new &= ~(behavior[reg / 4].w1c & ~mask);
    594
    595		/*
    596		 * Set the W1C bits specified by the write mask, so that write_op()
    597		 * knows about that they are to be cleared.
    598		 */
    599		new |= (value << shift) & (behavior[reg / 4].w1c & mask);
    600	}
    601
    602	if (write_op)
    603		write_op(bridge, reg, old, new, mask);
    604
    605	return PCIBIOS_SUCCESSFUL;
    606}
    607EXPORT_SYMBOL_GPL(pci_bridge_emul_conf_write);