cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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phy-mvebu-sata.c (3001B)

      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/*
      3 *	phy-mvebu-sata.c: SATA Phy driver for the Marvell mvebu SoCs.
      4 *
      5 *	Copyright (C) 2013 Andrew Lunn <andrew@lunn.ch>
      6 */
      7
      8#include <linux/kernel.h>
      9#include <linux/init.h>
     10#include <linux/clk.h>
     11#include <linux/phy/phy.h>
     12#include <linux/io.h>
     13#include <linux/platform_device.h>
     14
     15struct priv {
     16	struct clk	*clk;
     17	void __iomem	*base;
     18};
     19
     20#define SATA_PHY_MODE_2	0x0330
     21#define  MODE_2_FORCE_PU_TX	BIT(0)
     22#define  MODE_2_FORCE_PU_RX	BIT(1)
     23#define  MODE_2_PU_PLL		BIT(2)
     24#define  MODE_2_PU_IVREF	BIT(3)
     25#define SATA_IF_CTRL	0x0050
     26#define  CTRL_PHY_SHUTDOWN	BIT(9)
     27
     28static int phy_mvebu_sata_power_on(struct phy *phy)
     29{
     30	struct priv *priv = phy_get_drvdata(phy);
     31	u32 reg;
     32
     33	clk_prepare_enable(priv->clk);
     34
     35	/* Enable PLL and IVREF */
     36	reg = readl(priv->base + SATA_PHY_MODE_2);
     37	reg |= (MODE_2_FORCE_PU_TX | MODE_2_FORCE_PU_RX |
     38		MODE_2_PU_PLL | MODE_2_PU_IVREF);
     39	writel(reg , priv->base + SATA_PHY_MODE_2);
     40
     41	/* Enable PHY */
     42	reg = readl(priv->base + SATA_IF_CTRL);
     43	reg &= ~CTRL_PHY_SHUTDOWN;
     44	writel(reg, priv->base + SATA_IF_CTRL);
     45
     46	clk_disable_unprepare(priv->clk);
     47
     48	return 0;
     49}
     50
     51static int phy_mvebu_sata_power_off(struct phy *phy)
     52{
     53	struct priv *priv = phy_get_drvdata(phy);
     54	u32 reg;
     55
     56	clk_prepare_enable(priv->clk);
     57
     58	/* Disable PLL and IVREF */
     59	reg = readl(priv->base + SATA_PHY_MODE_2);
     60	reg &= ~(MODE_2_FORCE_PU_TX | MODE_2_FORCE_PU_RX |
     61		 MODE_2_PU_PLL | MODE_2_PU_IVREF);
     62	writel(reg, priv->base + SATA_PHY_MODE_2);
     63
     64	/* Disable PHY */
     65	reg = readl(priv->base + SATA_IF_CTRL);
     66	reg |= CTRL_PHY_SHUTDOWN;
     67	writel(reg, priv->base + SATA_IF_CTRL);
     68
     69	clk_disable_unprepare(priv->clk);
     70
     71	return 0;
     72}
     73
     74static const struct phy_ops phy_mvebu_sata_ops = {
     75	.power_on	= phy_mvebu_sata_power_on,
     76	.power_off	= phy_mvebu_sata_power_off,
     77	.owner		= THIS_MODULE,
     78};
     79
     80static int phy_mvebu_sata_probe(struct platform_device *pdev)
     81{
     82	struct phy_provider *phy_provider;
     83	struct priv *priv;
     84	struct phy *phy;
     85
     86	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
     87	if (!priv)
     88		return -ENOMEM;
     89
     90	priv->base = devm_platform_ioremap_resource(pdev, 0);
     91	if (IS_ERR(priv->base))
     92		return PTR_ERR(priv->base);
     93
     94	priv->clk = devm_clk_get(&pdev->dev, "sata");
     95	if (IS_ERR(priv->clk))
     96		return PTR_ERR(priv->clk);
     97
     98	phy = devm_phy_create(&pdev->dev, NULL, &phy_mvebu_sata_ops);
     99	if (IS_ERR(phy))
    100		return PTR_ERR(phy);
    101
    102	phy_set_drvdata(phy, priv);
    103
    104	phy_provider = devm_of_phy_provider_register(&pdev->dev,
    105						     of_phy_simple_xlate);
    106	if (IS_ERR(phy_provider))
    107		return PTR_ERR(phy_provider);
    108
    109	/* The boot loader may of left it on. Turn it off. */
    110	phy_mvebu_sata_power_off(phy);
    111
    112	return 0;
    113}
    114
    115static const struct of_device_id phy_mvebu_sata_of_match[] = {
    116	{ .compatible = "marvell,mvebu-sata-phy" },
    117	{ },
    118};
    119
    120static struct platform_driver phy_mvebu_sata_driver = {
    121	.probe	= phy_mvebu_sata_probe,
    122	.driver = {
    123		.name	= "phy-mvebu-sata",
    124		.of_match_table	= phy_mvebu_sata_of_match,
    125	}
    126};
    127builtin_platform_driver(phy_mvebu_sata_driver);