cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pinctrl-owl.c (23721B)


      1// SPDX-License-Identifier: GPL-2.0+
      2/*
      3 * OWL SoC's Pinctrl driver
      4 *
      5 * Copyright (c) 2014 Actions Semi Inc.
      6 * Author: David Liu <liuwei@actions-semi.com>
      7 *
      8 * Copyright (c) 2018 Linaro Ltd.
      9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
     10 */
     11
     12#include <linux/clk.h>
     13#include <linux/err.h>
     14#include <linux/gpio/driver.h>
     15#include <linux/io.h>
     16#include <linux/irq.h>
     17#include <linux/module.h>
     18#include <linux/of.h>
     19#include <linux/platform_device.h>
     20#include <linux/pinctrl/machine.h>
     21#include <linux/pinctrl/pinctrl.h>
     22#include <linux/pinctrl/pinmux.h>
     23#include <linux/pinctrl/pinconf.h>
     24#include <linux/pinctrl/pinconf-generic.h>
     25#include <linux/slab.h>
     26#include <linux/spinlock.h>
     27
     28#include "../core.h"
     29#include "../pinctrl-utils.h"
     30#include "pinctrl-owl.h"
     31
     32/**
     33 * struct owl_pinctrl - pinctrl state of the device
     34 * @dev: device handle
     35 * @pctrldev: pinctrl handle
     36 * @chip: gpio chip
     37 * @lock: spinlock to protect registers
     38 * @clk: clock control
     39 * @soc: reference to soc_data
     40 * @base: pinctrl register base address
     41 * @irq_chip: IRQ chip information
     42 * @num_irq: number of possible interrupts
     43 * @irq: interrupt numbers
     44 */
     45struct owl_pinctrl {
     46	struct device *dev;
     47	struct pinctrl_dev *pctrldev;
     48	struct gpio_chip chip;
     49	raw_spinlock_t lock;
     50	struct clk *clk;
     51	const struct owl_pinctrl_soc_data *soc;
     52	void __iomem *base;
     53	struct irq_chip irq_chip;
     54	unsigned int num_irq;
     55	unsigned int *irq;
     56};
     57
     58static void owl_update_bits(void __iomem *base, u32 mask, u32 val)
     59{
     60	u32 reg_val;
     61
     62	reg_val = readl_relaxed(base);
     63
     64	reg_val = (reg_val & ~mask) | (val & mask);
     65
     66	writel_relaxed(reg_val, base);
     67}
     68
     69static u32 owl_read_field(struct owl_pinctrl *pctrl, u32 reg,
     70				u32 bit, u32 width)
     71{
     72	u32 tmp, mask;
     73
     74	tmp = readl_relaxed(pctrl->base + reg);
     75	mask = (1 << width) - 1;
     76
     77	return (tmp >> bit) & mask;
     78}
     79
     80static void owl_write_field(struct owl_pinctrl *pctrl, u32 reg, u32 arg,
     81				u32 bit, u32 width)
     82{
     83	u32 mask;
     84
     85	mask = (1 << width) - 1;
     86	mask = mask << bit;
     87
     88	owl_update_bits(pctrl->base + reg, mask, (arg << bit));
     89}
     90
     91static int owl_get_groups_count(struct pinctrl_dev *pctrldev)
     92{
     93	struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
     94
     95	return pctrl->soc->ngroups;
     96}
     97
     98static const char *owl_get_group_name(struct pinctrl_dev *pctrldev,
     99				unsigned int group)
    100{
    101	struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
    102
    103	return pctrl->soc->groups[group].name;
    104}
    105
    106static int owl_get_group_pins(struct pinctrl_dev *pctrldev,
    107				unsigned int group,
    108				const unsigned int **pins,
    109				unsigned int *num_pins)
    110{
    111	struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
    112
    113	*pins = pctrl->soc->groups[group].pads;
    114	*num_pins = pctrl->soc->groups[group].npads;
    115
    116	return 0;
    117}
    118
    119static void owl_pin_dbg_show(struct pinctrl_dev *pctrldev,
    120				struct seq_file *s,
    121				unsigned int offset)
    122{
    123	struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
    124
    125	seq_printf(s, "%s", dev_name(pctrl->dev));
    126}
    127
    128static const struct pinctrl_ops owl_pinctrl_ops = {
    129	.get_groups_count = owl_get_groups_count,
    130	.get_group_name = owl_get_group_name,
    131	.get_group_pins = owl_get_group_pins,
    132	.pin_dbg_show = owl_pin_dbg_show,
    133	.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
    134	.dt_free_map = pinctrl_utils_free_map,
    135};
    136
    137static int owl_get_funcs_count(struct pinctrl_dev *pctrldev)
    138{
    139	struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
    140
    141	return pctrl->soc->nfunctions;
    142}
    143
    144static const char *owl_get_func_name(struct pinctrl_dev *pctrldev,
    145				unsigned int function)
    146{
    147	struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
    148
    149	return pctrl->soc->functions[function].name;
    150}
    151
    152static int owl_get_func_groups(struct pinctrl_dev *pctrldev,
    153				unsigned int function,
    154				const char * const **groups,
    155				unsigned int * const num_groups)
    156{
    157	struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
    158
    159	*groups = pctrl->soc->functions[function].groups;
    160	*num_groups = pctrl->soc->functions[function].ngroups;
    161
    162	return 0;
    163}
    164
    165static inline int get_group_mfp_mask_val(const struct owl_pingroup *g,
    166				int function,
    167				u32 *mask,
    168				u32 *val)
    169{
    170	int id;
    171	u32 option_num;
    172	u32 option_mask;
    173
    174	for (id = 0; id < g->nfuncs; id++) {
    175		if (g->funcs[id] == function)
    176			break;
    177	}
    178	if (WARN_ON(id == g->nfuncs))
    179		return -EINVAL;
    180
    181	option_num = (1 << g->mfpctl_width);
    182	if (id > option_num)
    183		id -= option_num;
    184
    185	option_mask = option_num - 1;
    186	*mask = (option_mask  << g->mfpctl_shift);
    187	*val = (id << g->mfpctl_shift);
    188
    189	return 0;
    190}
    191
    192static int owl_set_mux(struct pinctrl_dev *pctrldev,
    193				unsigned int function,
    194				unsigned int group)
    195{
    196	struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
    197	const struct owl_pingroup *g;
    198	unsigned long flags;
    199	u32 val, mask;
    200
    201	g = &pctrl->soc->groups[group];
    202
    203	if (get_group_mfp_mask_val(g, function, &mask, &val))
    204		return -EINVAL;
    205
    206	raw_spin_lock_irqsave(&pctrl->lock, flags);
    207
    208	owl_update_bits(pctrl->base + g->mfpctl_reg, mask, val);
    209
    210	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
    211
    212	return 0;
    213}
    214
    215static const struct pinmux_ops owl_pinmux_ops = {
    216	.get_functions_count = owl_get_funcs_count,
    217	.get_function_name = owl_get_func_name,
    218	.get_function_groups = owl_get_func_groups,
    219	.set_mux = owl_set_mux,
    220};
    221
    222static int owl_pad_pinconf_reg(const struct owl_padinfo *info,
    223				unsigned int param,
    224				u32 *reg,
    225				u32 *bit,
    226				u32 *width)
    227{
    228	switch (param) {
    229	case PIN_CONFIG_BIAS_BUS_HOLD:
    230	case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
    231	case PIN_CONFIG_BIAS_PULL_DOWN:
    232	case PIN_CONFIG_BIAS_PULL_UP:
    233		if (!info->pullctl)
    234			return -EINVAL;
    235		*reg = info->pullctl->reg;
    236		*bit = info->pullctl->shift;
    237		*width = info->pullctl->width;
    238		break;
    239	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
    240		if (!info->st)
    241			return -EINVAL;
    242		*reg = info->st->reg;
    243		*bit = info->st->shift;
    244		*width = info->st->width;
    245		break;
    246	default:
    247		return -ENOTSUPP;
    248	}
    249
    250	return 0;
    251}
    252
    253static int owl_pin_config_get(struct pinctrl_dev *pctrldev,
    254				unsigned int pin,
    255				unsigned long *config)
    256{
    257	int ret = 0;
    258	struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
    259	const struct owl_padinfo *info;
    260	unsigned int param = pinconf_to_config_param(*config);
    261	u32 reg, bit, width, arg;
    262
    263	info = &pctrl->soc->padinfo[pin];
    264
    265	ret = owl_pad_pinconf_reg(info, param, &reg, &bit, &width);
    266	if (ret)
    267		return ret;
    268
    269	arg = owl_read_field(pctrl, reg, bit, width);
    270
    271	if (!pctrl->soc->padctl_val2arg)
    272		return -ENOTSUPP;
    273
    274	ret = pctrl->soc->padctl_val2arg(info, param, &arg);
    275	if (ret)
    276		return ret;
    277
    278	*config = pinconf_to_config_packed(param, arg);
    279
    280	return ret;
    281}
    282
    283static int owl_pin_config_set(struct pinctrl_dev *pctrldev,
    284				unsigned int pin,
    285				unsigned long *configs,
    286				unsigned int num_configs)
    287{
    288	struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
    289	const struct owl_padinfo *info;
    290	unsigned long flags;
    291	unsigned int param;
    292	u32 reg, bit, width, arg;
    293	int ret = 0, i;
    294
    295	info = &pctrl->soc->padinfo[pin];
    296
    297	for (i = 0; i < num_configs; i++) {
    298		param = pinconf_to_config_param(configs[i]);
    299		arg = pinconf_to_config_argument(configs[i]);
    300
    301		ret = owl_pad_pinconf_reg(info, param, &reg, &bit, &width);
    302		if (ret)
    303			return ret;
    304
    305		if (!pctrl->soc->padctl_arg2val)
    306			return -ENOTSUPP;
    307
    308		ret = pctrl->soc->padctl_arg2val(info, param, &arg);
    309		if (ret)
    310			return ret;
    311
    312		raw_spin_lock_irqsave(&pctrl->lock, flags);
    313
    314		owl_write_field(pctrl, reg, arg, bit, width);
    315
    316		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
    317	}
    318
    319	return ret;
    320}
    321
    322static int owl_group_pinconf_reg(const struct owl_pingroup *g,
    323				unsigned int param,
    324				u32 *reg,
    325				u32 *bit,
    326				u32 *width)
    327{
    328	switch (param) {
    329	case PIN_CONFIG_DRIVE_STRENGTH:
    330		if (g->drv_reg < 0)
    331			return -EINVAL;
    332		*reg = g->drv_reg;
    333		*bit = g->drv_shift;
    334		*width = g->drv_width;
    335		break;
    336	case PIN_CONFIG_SLEW_RATE:
    337		if (g->sr_reg < 0)
    338			return -EINVAL;
    339		*reg = g->sr_reg;
    340		*bit = g->sr_shift;
    341		*width = g->sr_width;
    342		break;
    343	default:
    344		return -ENOTSUPP;
    345	}
    346
    347	return 0;
    348}
    349
    350static int owl_group_pinconf_arg2val(const struct owl_pingroup *g,
    351				unsigned int param,
    352				u32 *arg)
    353{
    354	switch (param) {
    355	case PIN_CONFIG_DRIVE_STRENGTH:
    356		switch (*arg) {
    357		case 2:
    358			*arg = OWL_PINCONF_DRV_2MA;
    359			break;
    360		case 4:
    361			*arg = OWL_PINCONF_DRV_4MA;
    362			break;
    363		case 8:
    364			*arg = OWL_PINCONF_DRV_8MA;
    365			break;
    366		case 12:
    367			*arg = OWL_PINCONF_DRV_12MA;
    368			break;
    369		default:
    370			return -EINVAL;
    371		}
    372		break;
    373	case PIN_CONFIG_SLEW_RATE:
    374		if (*arg)
    375			*arg = OWL_PINCONF_SLEW_FAST;
    376		else
    377			*arg = OWL_PINCONF_SLEW_SLOW;
    378		break;
    379	default:
    380		return -ENOTSUPP;
    381	}
    382
    383	return 0;
    384}
    385
    386static int owl_group_pinconf_val2arg(const struct owl_pingroup *g,
    387				unsigned int param,
    388				u32 *arg)
    389{
    390	switch (param) {
    391	case PIN_CONFIG_DRIVE_STRENGTH:
    392		switch (*arg) {
    393		case OWL_PINCONF_DRV_2MA:
    394			*arg = 2;
    395			break;
    396		case OWL_PINCONF_DRV_4MA:
    397			*arg = 4;
    398			break;
    399		case OWL_PINCONF_DRV_8MA:
    400			*arg = 8;
    401			break;
    402		case OWL_PINCONF_DRV_12MA:
    403			*arg = 12;
    404			break;
    405		default:
    406			return -EINVAL;
    407		}
    408		break;
    409	case PIN_CONFIG_SLEW_RATE:
    410		if (*arg)
    411			*arg = 1;
    412		else
    413			*arg = 0;
    414		break;
    415	default:
    416		return -ENOTSUPP;
    417	}
    418
    419	return 0;
    420}
    421
    422static int owl_group_config_get(struct pinctrl_dev *pctrldev,
    423				unsigned int group,
    424				unsigned long *config)
    425{
    426	const struct owl_pingroup *g;
    427	struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
    428	unsigned int param = pinconf_to_config_param(*config);
    429	u32 reg, bit, width, arg;
    430	int ret;
    431
    432	g = &pctrl->soc->groups[group];
    433
    434	ret = owl_group_pinconf_reg(g, param, &reg, &bit, &width);
    435	if (ret)
    436		return ret;
    437
    438	arg = owl_read_field(pctrl, reg, bit, width);
    439
    440	ret = owl_group_pinconf_val2arg(g, param, &arg);
    441	if (ret)
    442		return ret;
    443
    444	*config = pinconf_to_config_packed(param, arg);
    445
    446	return ret;
    447}
    448
    449static int owl_group_config_set(struct pinctrl_dev *pctrldev,
    450				unsigned int group,
    451				unsigned long *configs,
    452				unsigned int num_configs)
    453{
    454	const struct owl_pingroup *g;
    455	struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
    456	unsigned long flags;
    457	unsigned int param;
    458	u32 reg, bit, width, arg;
    459	int ret, i;
    460
    461	g = &pctrl->soc->groups[group];
    462
    463	for (i = 0; i < num_configs; i++) {
    464		param = pinconf_to_config_param(configs[i]);
    465		arg = pinconf_to_config_argument(configs[i]);
    466
    467		ret = owl_group_pinconf_reg(g, param, &reg, &bit, &width);
    468		if (ret)
    469			return ret;
    470
    471		ret = owl_group_pinconf_arg2val(g, param, &arg);
    472		if (ret)
    473			return ret;
    474
    475		/* Update register */
    476		raw_spin_lock_irqsave(&pctrl->lock, flags);
    477
    478		owl_write_field(pctrl, reg, arg, bit, width);
    479
    480		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
    481	}
    482
    483	return 0;
    484}
    485
    486static const struct pinconf_ops owl_pinconf_ops = {
    487	.is_generic = true,
    488	.pin_config_get = owl_pin_config_get,
    489	.pin_config_set = owl_pin_config_set,
    490	.pin_config_group_get = owl_group_config_get,
    491	.pin_config_group_set = owl_group_config_set,
    492};
    493
    494static struct pinctrl_desc owl_pinctrl_desc = {
    495	.pctlops = &owl_pinctrl_ops,
    496	.pmxops = &owl_pinmux_ops,
    497	.confops = &owl_pinconf_ops,
    498	.owner = THIS_MODULE,
    499};
    500
    501static const struct owl_gpio_port *
    502owl_gpio_get_port(struct owl_pinctrl *pctrl, unsigned int *pin)
    503{
    504	unsigned int start = 0, i;
    505
    506	for (i = 0; i < pctrl->soc->nports; i++) {
    507		const struct owl_gpio_port *port = &pctrl->soc->ports[i];
    508
    509		if (*pin >= start && *pin < start + port->pins) {
    510			*pin -= start;
    511			return port;
    512		}
    513
    514		start += port->pins;
    515	}
    516
    517	return NULL;
    518}
    519
    520static void owl_gpio_update_reg(void __iomem *base, unsigned int pin, int flag)
    521{
    522	u32 val;
    523
    524	val = readl_relaxed(base);
    525
    526	if (flag)
    527		val |= BIT(pin);
    528	else
    529		val &= ~BIT(pin);
    530
    531	writel_relaxed(val, base);
    532}
    533
    534static int owl_gpio_request(struct gpio_chip *chip, unsigned int offset)
    535{
    536	struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
    537	const struct owl_gpio_port *port;
    538	void __iomem *gpio_base;
    539	unsigned long flags;
    540
    541	port = owl_gpio_get_port(pctrl, &offset);
    542	if (WARN_ON(port == NULL))
    543		return -ENODEV;
    544
    545	gpio_base = pctrl->base + port->offset;
    546
    547	/*
    548	 * GPIOs have higher priority over other modules, so either setting
    549	 * them as OUT or IN is sufficient
    550	 */
    551	raw_spin_lock_irqsave(&pctrl->lock, flags);
    552	owl_gpio_update_reg(gpio_base + port->outen, offset, true);
    553	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
    554
    555	return 0;
    556}
    557
    558static void owl_gpio_free(struct gpio_chip *chip, unsigned int offset)
    559{
    560	struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
    561	const struct owl_gpio_port *port;
    562	void __iomem *gpio_base;
    563	unsigned long flags;
    564
    565	port = owl_gpio_get_port(pctrl, &offset);
    566	if (WARN_ON(port == NULL))
    567		return;
    568
    569	gpio_base = pctrl->base + port->offset;
    570
    571	raw_spin_lock_irqsave(&pctrl->lock, flags);
    572	/* disable gpio output */
    573	owl_gpio_update_reg(gpio_base + port->outen, offset, false);
    574
    575	/* disable gpio input */
    576	owl_gpio_update_reg(gpio_base + port->inen, offset, false);
    577	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
    578}
    579
    580static int owl_gpio_get(struct gpio_chip *chip, unsigned int offset)
    581{
    582	struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
    583	const struct owl_gpio_port *port;
    584	void __iomem *gpio_base;
    585	unsigned long flags;
    586	u32 val;
    587
    588	port = owl_gpio_get_port(pctrl, &offset);
    589	if (WARN_ON(port == NULL))
    590		return -ENODEV;
    591
    592	gpio_base = pctrl->base + port->offset;
    593
    594	raw_spin_lock_irqsave(&pctrl->lock, flags);
    595	val = readl_relaxed(gpio_base + port->dat);
    596	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
    597
    598	return !!(val & BIT(offset));
    599}
    600
    601static void owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
    602{
    603	struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
    604	const struct owl_gpio_port *port;
    605	void __iomem *gpio_base;
    606	unsigned long flags;
    607
    608	port = owl_gpio_get_port(pctrl, &offset);
    609	if (WARN_ON(port == NULL))
    610		return;
    611
    612	gpio_base = pctrl->base + port->offset;
    613
    614	raw_spin_lock_irqsave(&pctrl->lock, flags);
    615	owl_gpio_update_reg(gpio_base + port->dat, offset, value);
    616	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
    617}
    618
    619static int owl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
    620{
    621	struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
    622	const struct owl_gpio_port *port;
    623	void __iomem *gpio_base;
    624	unsigned long flags;
    625
    626	port = owl_gpio_get_port(pctrl, &offset);
    627	if (WARN_ON(port == NULL))
    628		return -ENODEV;
    629
    630	gpio_base = pctrl->base + port->offset;
    631
    632	raw_spin_lock_irqsave(&pctrl->lock, flags);
    633	owl_gpio_update_reg(gpio_base + port->outen, offset, false);
    634	owl_gpio_update_reg(gpio_base + port->inen, offset, true);
    635	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
    636
    637	return 0;
    638}
    639
    640static int owl_gpio_direction_output(struct gpio_chip *chip,
    641				unsigned int offset, int value)
    642{
    643	struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
    644	const struct owl_gpio_port *port;
    645	void __iomem *gpio_base;
    646	unsigned long flags;
    647
    648	port = owl_gpio_get_port(pctrl, &offset);
    649	if (WARN_ON(port == NULL))
    650		return -ENODEV;
    651
    652	gpio_base = pctrl->base + port->offset;
    653
    654	raw_spin_lock_irqsave(&pctrl->lock, flags);
    655	owl_gpio_update_reg(gpio_base + port->inen, offset, false);
    656	owl_gpio_update_reg(gpio_base + port->outen, offset, true);
    657	owl_gpio_update_reg(gpio_base + port->dat, offset, value);
    658	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
    659
    660	return 0;
    661}
    662
    663static void irq_set_type(struct owl_pinctrl *pctrl, int gpio, unsigned int type)
    664{
    665	const struct owl_gpio_port *port;
    666	void __iomem *gpio_base;
    667	unsigned long flags;
    668	unsigned int offset, value, irq_type = 0;
    669
    670	switch (type) {
    671	case IRQ_TYPE_EDGE_BOTH:
    672		/*
    673		 * Since the hardware doesn't support interrupts on both edges,
    674		 * emulate it in the software by setting the single edge
    675		 * interrupt and switching to the opposite edge while ACKing
    676		 * the interrupt
    677		 */
    678		if (owl_gpio_get(&pctrl->chip, gpio))
    679			irq_type = OWL_GPIO_INT_EDGE_FALLING;
    680		else
    681			irq_type = OWL_GPIO_INT_EDGE_RISING;
    682		break;
    683
    684	case IRQ_TYPE_EDGE_RISING:
    685		irq_type = OWL_GPIO_INT_EDGE_RISING;
    686		break;
    687
    688	case IRQ_TYPE_EDGE_FALLING:
    689		irq_type = OWL_GPIO_INT_EDGE_FALLING;
    690		break;
    691
    692	case IRQ_TYPE_LEVEL_HIGH:
    693		irq_type = OWL_GPIO_INT_LEVEL_HIGH;
    694		break;
    695
    696	case IRQ_TYPE_LEVEL_LOW:
    697		irq_type = OWL_GPIO_INT_LEVEL_LOW;
    698		break;
    699
    700	default:
    701		break;
    702	}
    703
    704	port = owl_gpio_get_port(pctrl, &gpio);
    705	if (WARN_ON(port == NULL))
    706		return;
    707
    708	gpio_base = pctrl->base + port->offset;
    709
    710	raw_spin_lock_irqsave(&pctrl->lock, flags);
    711
    712	offset = (gpio < 16) ? 4 : 0;
    713	value = readl_relaxed(gpio_base + port->intc_type + offset);
    714	value &= ~(OWL_GPIO_INT_MASK << ((gpio % 16) * 2));
    715	value |= irq_type << ((gpio % 16) * 2);
    716	writel_relaxed(value, gpio_base + port->intc_type + offset);
    717
    718	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
    719}
    720
    721static void owl_gpio_irq_mask(struct irq_data *data)
    722{
    723	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
    724	struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
    725	const struct owl_gpio_port *port;
    726	void __iomem *gpio_base;
    727	unsigned long flags;
    728	unsigned int gpio = data->hwirq;
    729	u32 val;
    730
    731	port = owl_gpio_get_port(pctrl, &gpio);
    732	if (WARN_ON(port == NULL))
    733		return;
    734
    735	gpio_base = pctrl->base + port->offset;
    736
    737	raw_spin_lock_irqsave(&pctrl->lock, flags);
    738
    739	owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, false);
    740
    741	/* disable port interrupt if no interrupt pending bit is active */
    742	val = readl_relaxed(gpio_base + port->intc_msk);
    743	if (val == 0)
    744		owl_gpio_update_reg(gpio_base + port->intc_ctl,
    745					OWL_GPIO_CTLR_ENABLE + port->shared_ctl_offset * 5, false);
    746
    747	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
    748}
    749
    750static void owl_gpio_irq_unmask(struct irq_data *data)
    751{
    752	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
    753	struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
    754	const struct owl_gpio_port *port;
    755	void __iomem *gpio_base;
    756	unsigned long flags;
    757	unsigned int gpio = data->hwirq;
    758	u32 value;
    759
    760	port = owl_gpio_get_port(pctrl, &gpio);
    761	if (WARN_ON(port == NULL))
    762		return;
    763
    764	gpio_base = pctrl->base + port->offset;
    765	raw_spin_lock_irqsave(&pctrl->lock, flags);
    766
    767	/* enable port interrupt */
    768	value = readl_relaxed(gpio_base + port->intc_ctl);
    769	value |= ((BIT(OWL_GPIO_CTLR_ENABLE) | BIT(OWL_GPIO_CTLR_SAMPLE_CLK_24M))
    770			<< port->shared_ctl_offset * 5);
    771	writel_relaxed(value, gpio_base + port->intc_ctl);
    772
    773	/* enable GPIO interrupt */
    774	owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, true);
    775
    776	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
    777}
    778
    779static void owl_gpio_irq_ack(struct irq_data *data)
    780{
    781	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
    782	struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
    783	const struct owl_gpio_port *port;
    784	void __iomem *gpio_base;
    785	unsigned long flags;
    786	unsigned int gpio = data->hwirq;
    787
    788	/*
    789	 * Switch the interrupt edge to the opposite edge of the interrupt
    790	 * which got triggered for the case of emulating both edges
    791	 */
    792	if (irqd_get_trigger_type(data) == IRQ_TYPE_EDGE_BOTH) {
    793		if (owl_gpio_get(gc, gpio))
    794			irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_FALLING);
    795		else
    796			irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_RISING);
    797	}
    798
    799	port = owl_gpio_get_port(pctrl, &gpio);
    800	if (WARN_ON(port == NULL))
    801		return;
    802
    803	gpio_base = pctrl->base + port->offset;
    804
    805	raw_spin_lock_irqsave(&pctrl->lock, flags);
    806
    807	owl_gpio_update_reg(gpio_base + port->intc_ctl,
    808				OWL_GPIO_CTLR_PENDING + port->shared_ctl_offset * 5, true);
    809
    810	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
    811}
    812
    813static int owl_gpio_irq_set_type(struct irq_data *data, unsigned int type)
    814{
    815	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
    816	struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
    817
    818	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
    819		irq_set_handler_locked(data, handle_level_irq);
    820	else
    821		irq_set_handler_locked(data, handle_edge_irq);
    822
    823	irq_set_type(pctrl, data->hwirq, type);
    824
    825	return 0;
    826}
    827
    828static void owl_gpio_irq_handler(struct irq_desc *desc)
    829{
    830	struct owl_pinctrl *pctrl = irq_desc_get_handler_data(desc);
    831	struct irq_chip *chip = irq_desc_get_chip(desc);
    832	struct irq_domain *domain = pctrl->chip.irq.domain;
    833	unsigned int parent = irq_desc_get_irq(desc);
    834	const struct owl_gpio_port *port;
    835	void __iomem *base;
    836	unsigned int pin, offset = 0, i;
    837	unsigned long pending_irq;
    838
    839	chained_irq_enter(chip, desc);
    840
    841	for (i = 0; i < pctrl->soc->nports; i++) {
    842		port = &pctrl->soc->ports[i];
    843		base = pctrl->base + port->offset;
    844
    845		/* skip ports that are not associated with this irq */
    846		if (parent != pctrl->irq[i])
    847			goto skip;
    848
    849		pending_irq = readl_relaxed(base + port->intc_pd);
    850
    851		for_each_set_bit(pin, &pending_irq, port->pins) {
    852			generic_handle_domain_irq(domain, offset + pin);
    853
    854			/* clear pending interrupt */
    855			owl_gpio_update_reg(base + port->intc_pd, pin, true);
    856		}
    857
    858skip:
    859		offset += port->pins;
    860	}
    861
    862	chained_irq_exit(chip, desc);
    863}
    864
    865static int owl_gpio_init(struct owl_pinctrl *pctrl)
    866{
    867	struct gpio_chip *chip;
    868	struct gpio_irq_chip *gpio_irq;
    869	int ret, i, j, offset;
    870
    871	chip = &pctrl->chip;
    872	chip->base = -1;
    873	chip->ngpio = pctrl->soc->ngpios;
    874	chip->label = dev_name(pctrl->dev);
    875	chip->parent = pctrl->dev;
    876	chip->owner = THIS_MODULE;
    877
    878	pctrl->irq_chip.name = chip->of_node->name;
    879	pctrl->irq_chip.irq_ack = owl_gpio_irq_ack;
    880	pctrl->irq_chip.irq_mask = owl_gpio_irq_mask;
    881	pctrl->irq_chip.irq_unmask = owl_gpio_irq_unmask;
    882	pctrl->irq_chip.irq_set_type = owl_gpio_irq_set_type;
    883
    884	gpio_irq = &chip->irq;
    885	gpio_irq->chip = &pctrl->irq_chip;
    886	gpio_irq->handler = handle_simple_irq;
    887	gpio_irq->default_type = IRQ_TYPE_NONE;
    888	gpio_irq->parent_handler = owl_gpio_irq_handler;
    889	gpio_irq->parent_handler_data = pctrl;
    890	gpio_irq->num_parents = pctrl->num_irq;
    891	gpio_irq->parents = pctrl->irq;
    892
    893	gpio_irq->map = devm_kcalloc(pctrl->dev, chip->ngpio,
    894				sizeof(*gpio_irq->map), GFP_KERNEL);
    895	if (!gpio_irq->map)
    896		return -ENOMEM;
    897
    898	for (i = 0, offset = 0; i < pctrl->soc->nports; i++) {
    899		const struct owl_gpio_port *port = &pctrl->soc->ports[i];
    900
    901		for (j = 0; j < port->pins; j++)
    902			gpio_irq->map[offset + j] = gpio_irq->parents[i];
    903
    904		offset += port->pins;
    905	}
    906
    907	ret = gpiochip_add_data(&pctrl->chip, pctrl);
    908	if (ret) {
    909		dev_err(pctrl->dev, "failed to register gpiochip\n");
    910		return ret;
    911	}
    912
    913	return 0;
    914}
    915
    916int owl_pinctrl_probe(struct platform_device *pdev,
    917				struct owl_pinctrl_soc_data *soc_data)
    918{
    919	struct owl_pinctrl *pctrl;
    920	int ret, i;
    921
    922	pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
    923	if (!pctrl)
    924		return -ENOMEM;
    925
    926	pctrl->base = devm_platform_ioremap_resource(pdev, 0);
    927	if (IS_ERR(pctrl->base))
    928		return PTR_ERR(pctrl->base);
    929
    930	/* enable GPIO/MFP clock */
    931	pctrl->clk = devm_clk_get(&pdev->dev, NULL);
    932	if (IS_ERR(pctrl->clk)) {
    933		dev_err(&pdev->dev, "no clock defined\n");
    934		return PTR_ERR(pctrl->clk);
    935	}
    936
    937	ret = clk_prepare_enable(pctrl->clk);
    938	if (ret) {
    939		dev_err(&pdev->dev, "clk enable failed\n");
    940		return ret;
    941	}
    942
    943	raw_spin_lock_init(&pctrl->lock);
    944
    945	owl_pinctrl_desc.name = dev_name(&pdev->dev);
    946	owl_pinctrl_desc.pins = soc_data->pins;
    947	owl_pinctrl_desc.npins = soc_data->npins;
    948
    949	pctrl->chip.direction_input  = owl_gpio_direction_input;
    950	pctrl->chip.direction_output = owl_gpio_direction_output;
    951	pctrl->chip.get = owl_gpio_get;
    952	pctrl->chip.set = owl_gpio_set;
    953	pctrl->chip.request = owl_gpio_request;
    954	pctrl->chip.free = owl_gpio_free;
    955
    956	pctrl->soc = soc_data;
    957	pctrl->dev = &pdev->dev;
    958
    959	pctrl->pctrldev = devm_pinctrl_register(&pdev->dev,
    960					&owl_pinctrl_desc, pctrl);
    961	if (IS_ERR(pctrl->pctrldev)) {
    962		dev_err(&pdev->dev, "could not register Actions OWL pinmux driver\n");
    963		ret = PTR_ERR(pctrl->pctrldev);
    964		goto err_exit;
    965	}
    966
    967	ret = platform_irq_count(pdev);
    968	if (ret < 0)
    969		goto err_exit;
    970
    971	pctrl->num_irq = ret;
    972
    973	pctrl->irq = devm_kcalloc(&pdev->dev, pctrl->num_irq,
    974					sizeof(*pctrl->irq), GFP_KERNEL);
    975	if (!pctrl->irq) {
    976		ret = -ENOMEM;
    977		goto err_exit;
    978	}
    979
    980	for (i = 0; i < pctrl->num_irq ; i++) {
    981		ret = platform_get_irq(pdev, i);
    982		if (ret < 0)
    983			goto err_exit;
    984		pctrl->irq[i] = ret;
    985	}
    986
    987	ret = owl_gpio_init(pctrl);
    988	if (ret)
    989		goto err_exit;
    990
    991	platform_set_drvdata(pdev, pctrl);
    992
    993	return 0;
    994
    995err_exit:
    996	clk_disable_unprepare(pctrl->clk);
    997
    998	return ret;
    999}