cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pinctrl-cs47l15.c (1439B)


      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Pinctrl for Cirrus Logic CS47L15
      4 *
      5 * Copyright (C) 2018-2019 Cirrus Logic, Inc. and
      6 *                         Cirrus Logic International Semiconductor Ltd.
      7 */
      8
      9#include <linux/err.h>
     10#include <linux/mfd/madera/core.h>
     11
     12#include "pinctrl-madera.h"
     13
     14/*
     15 * The alt func groups are the most commonly used functions we place these at
     16 * the lower function indexes for convenience, and the less commonly used gpio
     17 * functions at higher indexes.
     18 *
     19 * To stay consistent with the datasheet the function names are the same as
     20 * the group names for that function's pins
     21 *
     22 * Note - all 1 less than in datasheet because these are zero-indexed
     23 */
     24static const unsigned int cs47l15_aif1_pins[] = { 0, 1, 2, 3 };
     25static const unsigned int cs47l15_aif2_pins[] = { 4, 5, 6, 7 };
     26static const unsigned int cs47l15_aif3_pins[] = { 8, 9, 10, 11 };
     27static const unsigned int cs47l15_spk1_pins[] = { 12, 13, 14 };
     28
     29static const struct madera_pin_groups cs47l15_pin_groups[] = {
     30	{ "aif1", cs47l15_aif1_pins, ARRAY_SIZE(cs47l15_aif1_pins) },
     31	{ "aif2", cs47l15_aif2_pins, ARRAY_SIZE(cs47l15_aif2_pins) },
     32	{ "aif3", cs47l15_aif3_pins, ARRAY_SIZE(cs47l15_aif3_pins) },
     33	{ "pdmspk1", cs47l15_spk1_pins, ARRAY_SIZE(cs47l15_spk1_pins) },
     34};
     35
     36const struct madera_pin_chip cs47l15_pin_chip = {
     37	.n_pins = CS47L15_NUM_GPIOS,
     38	.pin_groups = cs47l15_pin_groups,
     39	.n_pin_groups = ARRAY_SIZE(cs47l15_pin_groups),
     40};