cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pinctrl-cs47l90.c (2241B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Pinctrl for Cirrus Logic CS47L90
      4 *
      5 * Copyright (C) 2016-2017 Cirrus Logic
      6 */
      7
      8#include <linux/err.h>
      9#include <linux/mfd/madera/core.h>
     10
     11#include "pinctrl-madera.h"
     12
     13/*
     14 * The alt func groups are the most commonly used functions we place these at
     15 * the lower function indexes for convenience, and the less commonly used gpio
     16 * functions at higher indexes.
     17 *
     18 * To stay consistent with the datasheet the function names are the same as
     19 * the group names for that function's pins
     20 *
     21 * Note - all 1 less than in datasheet because these are zero-indexed
     22 */
     23static const unsigned int cs47l90_mif1_pins[] = { 8, 9 };
     24static const unsigned int cs47l90_mif2_pins[] = { 10, 11 };
     25static const unsigned int cs47l90_mif3_pins[] = { 12, 13 };
     26static const unsigned int cs47l90_aif1_pins[] = { 14, 15, 16, 17 };
     27static const unsigned int cs47l90_aif2_pins[] = { 18, 19, 20, 21 };
     28static const unsigned int cs47l90_aif3_pins[] = { 22, 23, 24, 25 };
     29static const unsigned int cs47l90_aif4_pins[] = { 26, 27, 28, 29 };
     30static const unsigned int cs47l90_dmic4_pins[] = { 30, 31 };
     31static const unsigned int cs47l90_dmic5_pins[] = { 32, 33 };
     32static const unsigned int cs47l90_dmic3_pins[] = { 34, 35 };
     33static const unsigned int cs47l90_spk1_pins[] = { 36, 37 };
     34
     35static const struct madera_pin_groups cs47l90_pin_groups[] = {
     36	{ "aif1", cs47l90_aif1_pins, ARRAY_SIZE(cs47l90_aif1_pins) },
     37	{ "aif2", cs47l90_aif2_pins, ARRAY_SIZE(cs47l90_aif2_pins) },
     38	{ "aif3", cs47l90_aif3_pins, ARRAY_SIZE(cs47l90_aif3_pins) },
     39	{ "aif4", cs47l90_aif4_pins, ARRAY_SIZE(cs47l90_aif4_pins) },
     40	{ "mif1", cs47l90_mif1_pins, ARRAY_SIZE(cs47l90_mif1_pins) },
     41	{ "mif2", cs47l90_mif2_pins, ARRAY_SIZE(cs47l90_mif2_pins) },
     42	{ "mif3", cs47l90_mif3_pins, ARRAY_SIZE(cs47l90_mif3_pins) },
     43	{ "dmic3", cs47l90_dmic3_pins, ARRAY_SIZE(cs47l90_dmic3_pins) },
     44	{ "dmic4", cs47l90_dmic4_pins, ARRAY_SIZE(cs47l90_dmic4_pins) },
     45	{ "dmic5", cs47l90_dmic5_pins, ARRAY_SIZE(cs47l90_dmic5_pins) },
     46	{ "pdmspk1", cs47l90_spk1_pins, ARRAY_SIZE(cs47l90_spk1_pins) },
     47};
     48
     49const struct madera_pin_chip cs47l90_pin_chip = {
     50	.n_pins = CS47L90_NUM_GPIOS,
     51	.pin_groups = cs47l90_pin_groups,
     52	.n_pin_groups = ARRAY_SIZE(cs47l90_pin_groups),
     53};