cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

pinctrl-icelake.c (23410B)


      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Intel Ice Lake PCH pinctrl/GPIO driver
      4 *
      5 * Copyright (C) 2018, 2022 Intel Corporation
      6 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
      7 *	    Mika Westerberg <mika.westerberg@linux.intel.com>
      8 */
      9
     10#include <linux/acpi.h>
     11#include <linux/module.h>
     12#include <linux/platform_device.h>
     13
     14#include <linux/pinctrl/pinctrl.h>
     15
     16#include "pinctrl-intel.h"
     17
     18#define ICL_PAD_OWN	0x020
     19#define ICL_PADCFGLOCK	0x080
     20#define ICL_HOSTSW_OWN	0x0b0
     21#define ICL_GPI_IS	0x100
     22#define ICL_LP_GPI_IE	0x110
     23#define ICL_N_GPI_IE	0x120
     24
     25#define ICL_GPP(r, s, e, g)				\
     26	{						\
     27		.reg_num = (r),				\
     28		.base = (s),				\
     29		.size = ((e) - (s) + 1),		\
     30		.gpio_base = (g),			\
     31	}
     32
     33#define ICL_COMMUNITY(b, s, e, ie, g)			\
     34	{						\
     35		.barno = (b),				\
     36		.padown_offset = ICL_PAD_OWN,		\
     37		.padcfglock_offset = ICL_PADCFGLOCK,	\
     38		.hostown_offset = ICL_HOSTSW_OWN,	\
     39		.is_offset = ICL_GPI_IS,		\
     40		.ie_offset = (ie),			\
     41		.pin_base = (s),			\
     42		.npins = ((e) - (s) + 1),		\
     43		.gpps = (g),				\
     44		.ngpps = ARRAY_SIZE(g),			\
     45	}
     46
     47#define ICL_LP_COMMUNITY(b, s, e, g)			\
     48	ICL_COMMUNITY(b, s, e, ICL_LP_GPI_IE, g)
     49
     50#define ICL_N_COMMUNITY(b, s, e, g)			\
     51	ICL_COMMUNITY(b, s, e, ICL_N_GPI_IE, g)
     52
     53/* Ice Lake-LP */
     54static const struct pinctrl_pin_desc icllp_pins[] = {
     55	/* GPP_G */
     56	PINCTRL_PIN(0, "SD3_CMD"),
     57	PINCTRL_PIN(1, "SD3_D0"),
     58	PINCTRL_PIN(2, "SD3_D1"),
     59	PINCTRL_PIN(3, "SD3_D2"),
     60	PINCTRL_PIN(4, "SD3_D3"),
     61	PINCTRL_PIN(5, "SD3_CDB"),
     62	PINCTRL_PIN(6, "SD3_CLK"),
     63	PINCTRL_PIN(7, "SD3_WP"),
     64	/* GPP_B */
     65	PINCTRL_PIN(8, "CORE_VID_0"),
     66	PINCTRL_PIN(9, "CORE_VID_1"),
     67	PINCTRL_PIN(10, "VRALERTB"),
     68	PINCTRL_PIN(11, "CPU_GP_2"),
     69	PINCTRL_PIN(12, "CPU_GP_3"),
     70	PINCTRL_PIN(13, "ISH_I2C0_SDA"),
     71	PINCTRL_PIN(14, "ISH_I2C0_SCL"),
     72	PINCTRL_PIN(15, "ISH_I2C1_SDA"),
     73	PINCTRL_PIN(16, "ISH_I2C1_SCL"),
     74	PINCTRL_PIN(17, "I2C5_SDA"),
     75	PINCTRL_PIN(18, "I2C5_SCL"),
     76	PINCTRL_PIN(19, "PMCALERTB"),
     77	PINCTRL_PIN(20, "SLP_S0B"),
     78	PINCTRL_PIN(21, "PLTRSTB"),
     79	PINCTRL_PIN(22, "SPKR"),
     80	PINCTRL_PIN(23, "GSPI0_CS0B"),
     81	PINCTRL_PIN(24, "GSPI0_CLK"),
     82	PINCTRL_PIN(25, "GSPI0_MISO"),
     83	PINCTRL_PIN(26, "GSPI0_MOSI"),
     84	PINCTRL_PIN(27, "GSPI1_CS0B"),
     85	PINCTRL_PIN(28, "GSPI1_CLK"),
     86	PINCTRL_PIN(29, "GSPI1_MISO"),
     87	PINCTRL_PIN(30, "GSPI1_MOSI"),
     88	PINCTRL_PIN(31, "SML1ALERTB"),
     89	PINCTRL_PIN(32, "GSPI0_CLK_LOOPBK"),
     90	PINCTRL_PIN(33, "GSPI1_CLK_LOOPBK"),
     91	/* GPP_A */
     92	PINCTRL_PIN(34, "ESPI_IO_0"),
     93	PINCTRL_PIN(35, "ESPI_IO_1"),
     94	PINCTRL_PIN(36, "ESPI_IO_2"),
     95	PINCTRL_PIN(37, "ESPI_IO_3"),
     96	PINCTRL_PIN(38, "ESPI_CSB"),
     97	PINCTRL_PIN(39, "ESPI_CLK"),
     98	PINCTRL_PIN(40, "ESPI_RESETB"),
     99	PINCTRL_PIN(41, "I2S2_SCLK"),
    100	PINCTRL_PIN(42, "I2S2_SFRM"),
    101	PINCTRL_PIN(43, "I2S2_TXD"),
    102	PINCTRL_PIN(44, "I2S2_RXD"),
    103	PINCTRL_PIN(45, "SATA_DEVSLP_2"),
    104	PINCTRL_PIN(46, "SATAXPCIE_1"),
    105	PINCTRL_PIN(47, "SATAXPCIE_2"),
    106	PINCTRL_PIN(48, "USB2_OCB_1"),
    107	PINCTRL_PIN(49, "USB2_OCB_2"),
    108	PINCTRL_PIN(50, "USB2_OCB_3"),
    109	PINCTRL_PIN(51, "DDSP_HPD_C"),
    110	PINCTRL_PIN(52, "DDSP_HPD_B"),
    111	PINCTRL_PIN(53, "DDSP_HPD_1"),
    112	PINCTRL_PIN(54, "DDSP_HPD_2"),
    113	PINCTRL_PIN(55, "I2S5_TXD"),
    114	PINCTRL_PIN(56, "I2S5_RXD"),
    115	PINCTRL_PIN(57, "I2S1_SCLK"),
    116	PINCTRL_PIN(58, "ESPI_CLK_LOOPBK"),
    117	/* GPP_H */
    118	PINCTRL_PIN(59, "SD_1P8_SEL"),
    119	PINCTRL_PIN(60, "SD_PWR_EN_B"),
    120	PINCTRL_PIN(61, "GPPC_H_2"),
    121	PINCTRL_PIN(62, "SX_EXIT_HOLDOFFB"),
    122	PINCTRL_PIN(63, "I2C2_SDA"),
    123	PINCTRL_PIN(64, "I2C2_SCL"),
    124	PINCTRL_PIN(65, "I2C3_SDA"),
    125	PINCTRL_PIN(66, "I2C3_SCL"),
    126	PINCTRL_PIN(67, "I2C4_SDA"),
    127	PINCTRL_PIN(68, "I2C4_SCL"),
    128	PINCTRL_PIN(69, "SRCCLKREQB_4"),
    129	PINCTRL_PIN(70, "SRCCLKREQB_5"),
    130	PINCTRL_PIN(71, "M2_SKT2_CFG_0"),
    131	PINCTRL_PIN(72, "M2_SKT2_CFG_1"),
    132	PINCTRL_PIN(73, "M2_SKT2_CFG_2"),
    133	PINCTRL_PIN(74, "M2_SKT2_CFG_3"),
    134	PINCTRL_PIN(75, "DDPB_CTRLCLK"),
    135	PINCTRL_PIN(76, "DDPB_CTRLDATA"),
    136	PINCTRL_PIN(77, "CPU_VCCIO_PWR_GATEB"),
    137	PINCTRL_PIN(78, "TIME_SYNC_0"),
    138	PINCTRL_PIN(79, "IMGCLKOUT_1"),
    139	PINCTRL_PIN(80, "IMGCLKOUT_2"),
    140	PINCTRL_PIN(81, "IMGCLKOUT_3"),
    141	PINCTRL_PIN(82, "IMGCLKOUT_4"),
    142	/* GPP_D */
    143	PINCTRL_PIN(83, "ISH_GP_0"),
    144	PINCTRL_PIN(84, "ISH_GP_1"),
    145	PINCTRL_PIN(85, "ISH_GP_2"),
    146	PINCTRL_PIN(86, "ISH_GP_3"),
    147	PINCTRL_PIN(87, "IMGCLKOUT_0"),
    148	PINCTRL_PIN(88, "SRCCLKREQB_0"),
    149	PINCTRL_PIN(89, "SRCCLKREQB_1"),
    150	PINCTRL_PIN(90, "SRCCLKREQB_2"),
    151	PINCTRL_PIN(91, "SRCCLKREQB_3"),
    152	PINCTRL_PIN(92, "ISH_SPI_CSB"),
    153	PINCTRL_PIN(93, "ISH_SPI_CLK"),
    154	PINCTRL_PIN(94, "ISH_SPI_MISO"),
    155	PINCTRL_PIN(95, "ISH_SPI_MOSI"),
    156	PINCTRL_PIN(96, "ISH_UART0_RXD"),
    157	PINCTRL_PIN(97, "ISH_UART0_TXD"),
    158	PINCTRL_PIN(98, "ISH_UART0_RTSB"),
    159	PINCTRL_PIN(99, "ISH_UART0_CTSB"),
    160	PINCTRL_PIN(100, "ISH_GP_4"),
    161	PINCTRL_PIN(101, "ISH_GP_5"),
    162	PINCTRL_PIN(102, "I2S_MCLK"),
    163	PINCTRL_PIN(103, "GSPI2_CLK_LOOPBK"),
    164	/* GPP_F */
    165	PINCTRL_PIN(104, "CNV_BRI_DT"),
    166	PINCTRL_PIN(105, "CNV_BRI_RSP"),
    167	PINCTRL_PIN(106, "CNV_RGI_DT"),
    168	PINCTRL_PIN(107, "CNV_RGI_RSP"),
    169	PINCTRL_PIN(108, "CNV_RF_RESET_B"),
    170	PINCTRL_PIN(109, "EMMC_HIP_MON"),
    171	PINCTRL_PIN(110, "CNV_PA_BLANKING"),
    172	PINCTRL_PIN(111, "EMMC_CMD"),
    173	PINCTRL_PIN(112, "EMMC_DATA0"),
    174	PINCTRL_PIN(113, "EMMC_DATA1"),
    175	PINCTRL_PIN(114, "EMMC_DATA2"),
    176	PINCTRL_PIN(115, "EMMC_DATA3"),
    177	PINCTRL_PIN(116, "EMMC_DATA4"),
    178	PINCTRL_PIN(117, "EMMC_DATA5"),
    179	PINCTRL_PIN(118, "EMMC_DATA6"),
    180	PINCTRL_PIN(119, "EMMC_DATA7"),
    181	PINCTRL_PIN(120, "EMMC_RCLK"),
    182	PINCTRL_PIN(121, "EMMC_CLK"),
    183	PINCTRL_PIN(122, "EMMC_RESETB"),
    184	PINCTRL_PIN(123, "A4WP_PRESENT"),
    185	/* vGPIO */
    186	PINCTRL_PIN(124, "CNV_BTEN"),
    187	PINCTRL_PIN(125, "CNV_WCEN"),
    188	PINCTRL_PIN(126, "CNV_BT_HOST_WAKEB"),
    189	PINCTRL_PIN(127, "CNV_BT_IF_SELECT"),
    190	PINCTRL_PIN(128, "vCNV_BT_UART_TXD"),
    191	PINCTRL_PIN(129, "vCNV_BT_UART_RXD"),
    192	PINCTRL_PIN(130, "vCNV_BT_UART_CTS_B"),
    193	PINCTRL_PIN(131, "vCNV_BT_UART_RTS_B"),
    194	PINCTRL_PIN(132, "vCNV_MFUART1_TXD"),
    195	PINCTRL_PIN(133, "vCNV_MFUART1_RXD"),
    196	PINCTRL_PIN(134, "vCNV_MFUART1_CTS_B"),
    197	PINCTRL_PIN(135, "vCNV_MFUART1_RTS_B"),
    198	PINCTRL_PIN(136, "vUART0_TXD"),
    199	PINCTRL_PIN(137, "vUART0_RXD"),
    200	PINCTRL_PIN(138, "vUART0_CTS_B"),
    201	PINCTRL_PIN(139, "vUART0_RTS_B"),
    202	PINCTRL_PIN(140, "vISH_UART0_TXD"),
    203	PINCTRL_PIN(141, "vISH_UART0_RXD"),
    204	PINCTRL_PIN(142, "vISH_UART0_CTS_B"),
    205	PINCTRL_PIN(143, "vISH_UART0_RTS_B"),
    206	PINCTRL_PIN(144, "vCNV_BT_I2S_BCLK"),
    207	PINCTRL_PIN(145, "vCNV_BT_I2S_WS_SYNC"),
    208	PINCTRL_PIN(146, "vCNV_BT_I2S_SDO"),
    209	PINCTRL_PIN(147, "vCNV_BT_I2S_SDI"),
    210	PINCTRL_PIN(148, "vI2S2_SCLK"),
    211	PINCTRL_PIN(149, "vI2S2_SFRM"),
    212	PINCTRL_PIN(150, "vI2S2_TXD"),
    213	PINCTRL_PIN(151, "vI2S2_RXD"),
    214	PINCTRL_PIN(152, "vSD3_CD_B"),
    215	/* GPP_C */
    216	PINCTRL_PIN(153, "SMBCLK"),
    217	PINCTRL_PIN(154, "SMBDATA"),
    218	PINCTRL_PIN(155, "SMBALERTB"),
    219	PINCTRL_PIN(156, "SML0CLK"),
    220	PINCTRL_PIN(157, "SML0DATA"),
    221	PINCTRL_PIN(158, "SML0ALERTB"),
    222	PINCTRL_PIN(159, "SML1CLK"),
    223	PINCTRL_PIN(160, "SML1DATA"),
    224	PINCTRL_PIN(161, "UART0_RXD"),
    225	PINCTRL_PIN(162, "UART0_TXD"),
    226	PINCTRL_PIN(163, "UART0_RTSB"),
    227	PINCTRL_PIN(164, "UART0_CTSB"),
    228	PINCTRL_PIN(165, "UART1_RXD"),
    229	PINCTRL_PIN(166, "UART1_TXD"),
    230	PINCTRL_PIN(167, "UART1_RTSB"),
    231	PINCTRL_PIN(168, "UART1_CTSB"),
    232	PINCTRL_PIN(169, "I2C0_SDA"),
    233	PINCTRL_PIN(170, "I2C0_SCL"),
    234	PINCTRL_PIN(171, "I2C1_SDA"),
    235	PINCTRL_PIN(172, "I2C1_SCL"),
    236	PINCTRL_PIN(173, "UART2_RXD"),
    237	PINCTRL_PIN(174, "UART2_TXD"),
    238	PINCTRL_PIN(175, "UART2_RTSB"),
    239	PINCTRL_PIN(176, "UART2_CTSB"),
    240	/* HVCMOS */
    241	PINCTRL_PIN(177, "L_BKLTEN"),
    242	PINCTRL_PIN(178, "L_BKLTCTL"),
    243	PINCTRL_PIN(179, "L_VDDEN"),
    244	PINCTRL_PIN(180, "SYS_PWROK"),
    245	PINCTRL_PIN(181, "SYS_RESETB"),
    246	PINCTRL_PIN(182, "MLK_RSTB"),
    247	/* GPP_E */
    248	PINCTRL_PIN(183, "SATAXPCIE_0"),
    249	PINCTRL_PIN(184, "SPI1_IO_2"),
    250	PINCTRL_PIN(185, "SPI1_IO_3"),
    251	PINCTRL_PIN(186, "CPU_GP_0"),
    252	PINCTRL_PIN(187, "SATA_DEVSLP_0"),
    253	PINCTRL_PIN(188, "SATA_DEVSLP_1"),
    254	PINCTRL_PIN(189, "GPPC_E_6"),
    255	PINCTRL_PIN(190, "CPU_GP_1"),
    256	PINCTRL_PIN(191, "SATA_LEDB"),
    257	PINCTRL_PIN(192, "USB2_OCB_0"),
    258	PINCTRL_PIN(193, "SPI1_CSB"),
    259	PINCTRL_PIN(194, "SPI1_CLK"),
    260	PINCTRL_PIN(195, "SPI1_MISO_IO_1"),
    261	PINCTRL_PIN(196, "SPI1_MOSI_IO_0"),
    262	PINCTRL_PIN(197, "DDSP_HPD_A"),
    263	PINCTRL_PIN(198, "ISH_GP_6"),
    264	PINCTRL_PIN(199, "ISH_GP_7"),
    265	PINCTRL_PIN(200, "DISP_MISC_4"),
    266	PINCTRL_PIN(201, "DDP1_CTRLCLK"),
    267	PINCTRL_PIN(202, "DDP1_CTRLDATA"),
    268	PINCTRL_PIN(203, "DDP2_CTRLCLK"),
    269	PINCTRL_PIN(204, "DDP2_CTRLDATA"),
    270	PINCTRL_PIN(205, "DDPA_CTRLCLK"),
    271	PINCTRL_PIN(206, "DDPA_CTRLDATA"),
    272	/* JTAG */
    273	PINCTRL_PIN(207, "JTAG_TDO"),
    274	PINCTRL_PIN(208, "JTAGX"),
    275	PINCTRL_PIN(209, "PRDYB"),
    276	PINCTRL_PIN(210, "PREQB"),
    277	PINCTRL_PIN(211, "CPU_TRSTB"),
    278	PINCTRL_PIN(212, "JTAG_TDI"),
    279	PINCTRL_PIN(213, "JTAG_TMS"),
    280	PINCTRL_PIN(214, "JTAG_TCK"),
    281	PINCTRL_PIN(215, "ITP_PMODE"),
    282	/* GPP_R */
    283	PINCTRL_PIN(216, "HDA_BCLK"),
    284	PINCTRL_PIN(217, "HDA_SYNC"),
    285	PINCTRL_PIN(218, "HDA_SDO"),
    286	PINCTRL_PIN(219, "HDA_SDI_0"),
    287	PINCTRL_PIN(220, "HDA_RSTB"),
    288	PINCTRL_PIN(221, "HDA_SDI_1"),
    289	PINCTRL_PIN(222, "I2S1_TXD"),
    290	PINCTRL_PIN(223, "I2S1_RXD"),
    291	/* GPP_S */
    292	PINCTRL_PIN(224, "SNDW1_CLK"),
    293	PINCTRL_PIN(225, "SNDW1_DATA"),
    294	PINCTRL_PIN(226, "SNDW2_CLK"),
    295	PINCTRL_PIN(227, "SNDW2_DATA"),
    296	PINCTRL_PIN(228, "SNDW3_CLK"),
    297	PINCTRL_PIN(229, "SNDW3_DATA"),
    298	PINCTRL_PIN(230, "SNDW4_CLK"),
    299	PINCTRL_PIN(231, "SNDW4_DATA"),
    300	/* SPI */
    301	PINCTRL_PIN(232, "SPI0_IO_2"),
    302	PINCTRL_PIN(233, "SPI0_IO_3"),
    303	PINCTRL_PIN(234, "SPI0_MOSI_IO_0"),
    304	PINCTRL_PIN(235, "SPI0_MISO_IO_1"),
    305	PINCTRL_PIN(236, "SPI0_TPM_CSB"),
    306	PINCTRL_PIN(237, "SPI0_FLASH_0_CSB"),
    307	PINCTRL_PIN(238, "SPI0_FLASH_1_CSB"),
    308	PINCTRL_PIN(239, "SPI0_CLK"),
    309	PINCTRL_PIN(240, "SPI0_CLK_LOOPBK"),
    310};
    311
    312static const struct intel_padgroup icllp_community0_gpps[] = {
    313	ICL_GPP(0, 0, 7, 0),				/* GPP_G */
    314	ICL_GPP(1, 8, 33, 32),				/* GPP_B */
    315	ICL_GPP(2, 34, 58, 64),				/* GPP_A */
    316};
    317
    318static const struct intel_padgroup icllp_community1_gpps[] = {
    319	ICL_GPP(0, 59, 82, 96),				/* GPP_H */
    320	ICL_GPP(1, 83, 103, 128),			/* GPP_D */
    321	ICL_GPP(2, 104, 123, 160),			/* GPP_F */
    322	ICL_GPP(3, 124, 152, 192),			/* vGPIO */
    323};
    324
    325static const struct intel_padgroup icllp_community4_gpps[] = {
    326	ICL_GPP(0, 153, 176, 224),			/* GPP_C */
    327	ICL_GPP(1, 177, 182, INTEL_GPIO_BASE_NOMAP),	/* HVCMOS */
    328	ICL_GPP(2, 183, 206, 256),			/* GPP_E */
    329	ICL_GPP(3, 207, 215, INTEL_GPIO_BASE_NOMAP),	/* JTAG */
    330};
    331
    332static const struct intel_padgroup icllp_community5_gpps[] = {
    333	ICL_GPP(0, 216, 223, 288),			/* GPP_R */
    334	ICL_GPP(1, 224, 231, 320),			/* GPP_S */
    335	ICL_GPP(2, 232, 240, INTEL_GPIO_BASE_NOMAP),	/* SPI */
    336};
    337
    338static const struct intel_community icllp_communities[] = {
    339	ICL_LP_COMMUNITY(0, 0, 58, icllp_community0_gpps),
    340	ICL_LP_COMMUNITY(1, 59, 152, icllp_community1_gpps),
    341	ICL_LP_COMMUNITY(2, 153, 215, icllp_community4_gpps),
    342	ICL_LP_COMMUNITY(3, 216, 240, icllp_community5_gpps),
    343};
    344
    345static const unsigned int icllp_spi0_pins[] = { 22, 23, 24, 25, 26 };
    346static const unsigned int icllp_spi0_modes[] = { 3, 1, 1, 1, 1 };
    347static const unsigned int icllp_spi1_pins[] = { 27, 28, 29, 30, 31 };
    348static const unsigned int icllp_spi1_modes[] = { 1, 1, 1, 1, 3 };
    349static const unsigned int icllp_spi2_pins[] = { 92, 93, 94, 95, 98 };
    350static const unsigned int icllp_spi2_modes[] = { 3, 3, 3, 3, 2 };
    351
    352static const unsigned int icllp_i2c0_pins[] = { 169, 170 };
    353static const unsigned int icllp_i2c1_pins[] = { 171, 172 };
    354static const unsigned int icllp_i2c2_pins[] = { 63, 64 };
    355static const unsigned int icllp_i2c3_pins[] = { 65, 66 };
    356static const unsigned int icllp_i2c4_pins[] = { 67, 68 };
    357
    358static const unsigned int icllp_uart0_pins[] = { 161, 162, 163, 164 };
    359static const unsigned int icllp_uart1_pins[] = { 165, 166, 167, 168 };
    360static const unsigned int icllp_uart2_pins[] = { 173, 174, 175, 176 };
    361
    362static const struct intel_pingroup icllp_groups[] = {
    363	PIN_GROUP("spi0_grp", icllp_spi0_pins, icllp_spi0_modes),
    364	PIN_GROUP("spi1_grp", icllp_spi1_pins, icllp_spi1_modes),
    365	PIN_GROUP("spi2_grp", icllp_spi2_pins, icllp_spi2_modes),
    366	PIN_GROUP("i2c0_grp", icllp_i2c0_pins, 1),
    367	PIN_GROUP("i2c1_grp", icllp_i2c1_pins, 1),
    368	PIN_GROUP("i2c2_grp", icllp_i2c2_pins, 1),
    369	PIN_GROUP("i2c3_grp", icllp_i2c3_pins, 1),
    370	PIN_GROUP("i2c4_grp", icllp_i2c4_pins, 1),
    371	PIN_GROUP("uart0_grp", icllp_uart0_pins, 1),
    372	PIN_GROUP("uart1_grp", icllp_uart1_pins, 1),
    373	PIN_GROUP("uart2_grp", icllp_uart2_pins, 1),
    374};
    375
    376static const char * const icllp_spi0_groups[] = { "spi0_grp" };
    377static const char * const icllp_spi1_groups[] = { "spi1_grp" };
    378static const char * const icllp_spi2_groups[] = { "spi2_grp" };
    379static const char * const icllp_i2c0_groups[] = { "i2c0_grp" };
    380static const char * const icllp_i2c1_groups[] = { "i2c1_grp" };
    381static const char * const icllp_i2c2_groups[] = { "i2c2_grp" };
    382static const char * const icllp_i2c3_groups[] = { "i2c3_grp" };
    383static const char * const icllp_i2c4_groups[] = { "i2c4_grp" };
    384static const char * const icllp_uart0_groups[] = { "uart0_grp" };
    385static const char * const icllp_uart1_groups[] = { "uart1_grp" };
    386static const char * const icllp_uart2_groups[] = { "uart2_grp" };
    387
    388static const struct intel_function icllp_functions[] = {
    389	FUNCTION("spi0", icllp_spi0_groups),
    390	FUNCTION("spi1", icllp_spi1_groups),
    391	FUNCTION("spi2", icllp_spi2_groups),
    392	FUNCTION("i2c0", icllp_i2c0_groups),
    393	FUNCTION("i2c1", icllp_i2c1_groups),
    394	FUNCTION("i2c2", icllp_i2c2_groups),
    395	FUNCTION("i2c3", icllp_i2c3_groups),
    396	FUNCTION("i2c4", icllp_i2c4_groups),
    397	FUNCTION("uart0", icllp_uart0_groups),
    398	FUNCTION("uart1", icllp_uart1_groups),
    399	FUNCTION("uart2", icllp_uart2_groups),
    400};
    401
    402static const struct intel_pinctrl_soc_data icllp_soc_data = {
    403	.pins = icllp_pins,
    404	.npins = ARRAY_SIZE(icllp_pins),
    405	.groups = icllp_groups,
    406	.ngroups = ARRAY_SIZE(icllp_groups),
    407	.functions = icllp_functions,
    408	.nfunctions = ARRAY_SIZE(icllp_functions),
    409	.communities = icllp_communities,
    410	.ncommunities = ARRAY_SIZE(icllp_communities),
    411};
    412
    413/* Ice Lake-N */
    414static const struct pinctrl_pin_desc icln_pins[] = {
    415	/* SPI */
    416	PINCTRL_PIN(0, "SPI0_IO_2"),
    417	PINCTRL_PIN(1, "SPI0_IO_3"),
    418	PINCTRL_PIN(2, "SPI0_MOSI_IO_0"),
    419	PINCTRL_PIN(3, "SPI0_MISO_IO_1"),
    420	PINCTRL_PIN(4, "SPI0_TPM_CSB"),
    421	PINCTRL_PIN(5, "SPI0_FLASH_0_CSB"),
    422	PINCTRL_PIN(6, "SPI0_FLASH_1_CSB"),
    423	PINCTRL_PIN(7, "SPI0_CLK"),
    424	PINCTRL_PIN(8, "SPI0_CLK_LOOPBK"),
    425	/* GPP_B */
    426	PINCTRL_PIN(9, "CORE_VID_0"),
    427	PINCTRL_PIN(10, "CORE_VID_1"),
    428	PINCTRL_PIN(11, "VRALERTB"),
    429	PINCTRL_PIN(12, "CPU_GP_2"),
    430	PINCTRL_PIN(13, "CPU_GP_3"),
    431	PINCTRL_PIN(14, "SRCCLKREQB_0"),
    432	PINCTRL_PIN(15, "SRCCLKREQB_1"),
    433	PINCTRL_PIN(16, "SRCCLKREQB_2"),
    434	PINCTRL_PIN(17, "SRCCLKREQB_3"),
    435	PINCTRL_PIN(18, "SRCCLKREQB_4"),
    436	PINCTRL_PIN(19, "SRCCLKREQB_5"),
    437	PINCTRL_PIN(20, "EXT_PWR_GATEB"),
    438	PINCTRL_PIN(21, "SLP_S0B"),
    439	PINCTRL_PIN(22, "PLTRSTB"),
    440	PINCTRL_PIN(23, "SPKR_GSPI0_CS1B"),
    441	PINCTRL_PIN(24, "GSPI0_CS0B"),
    442	PINCTRL_PIN(25, "GSPI0_CLK"),
    443	PINCTRL_PIN(26, "GSPI0_MISO_TBT_LSX3_A"),
    444	PINCTRL_PIN(27, "GSPI0_MOSI_TBT_LSX3_B"),
    445	PINCTRL_PIN(28, "GSPI1_CS0B"),
    446	PINCTRL_PIN(29, "GSPI1_CLK_NFC_CLK"),
    447	PINCTRL_PIN(30, "GSPI1_MISO_NFC_CLKREQ"),
    448	PINCTRL_PIN(31, "GSPI1_MOSI"),
    449	PINCTRL_PIN(32, "GSPI1_CS1B"),
    450	PINCTRL_PIN(33, "GSPI0_CLK_LOOPBK"),
    451	PINCTRL_PIN(34, "GSPI1_CLK_LOOPBK"),
    452	/* GPP_A */
    453	PINCTRL_PIN(35, "ESPI_IO_0"),
    454	PINCTRL_PIN(36, "ESPI_IO_1"),
    455	PINCTRL_PIN(37, "ESPI_IO_2"),
    456	PINCTRL_PIN(38, "ESPI_IO_3"),
    457	PINCTRL_PIN(39, "ESPI_CSB"),
    458	PINCTRL_PIN(40, "ESPI_CLK"),
    459	PINCTRL_PIN(41, "ESPI_RESETB"),
    460	PINCTRL_PIN(42, "SMBCLK"),
    461	PINCTRL_PIN(43, "SMBDATA"),
    462	PINCTRL_PIN(44, "SMBALERTB"),
    463	PINCTRL_PIN(45, "CPU_GP_0"),
    464	PINCTRL_PIN(46, "CPU_GP_1"),
    465	PINCTRL_PIN(47, "USB2_OCB_1"),
    466	PINCTRL_PIN(48, "USB2_OCB_2"),
    467	PINCTRL_PIN(49, "USB2_OCB_3"),
    468	PINCTRL_PIN(50, "DDSP_HPD_A_TIME_SYNC_0"),
    469	PINCTRL_PIN(51, "DDSP_HPD_B_TIME_SYNC_1"),
    470	PINCTRL_PIN(52, "DDSP_HPD_C"),
    471	PINCTRL_PIN(53, "USB2_OCB_0"),
    472	PINCTRL_PIN(54, "PCHHOTB"),
    473	PINCTRL_PIN(55, "ESPI_CLK_LOOPBK"),
    474	/* GPP_S */
    475	PINCTRL_PIN(56, "SNDW1_CLK"),
    476	PINCTRL_PIN(57, "SNDW1_DATA"),
    477	PINCTRL_PIN(58, "SNDW2_CLK"),
    478	PINCTRL_PIN(59, "SNDW2_DATA"),
    479	PINCTRL_PIN(60, "SNDW3_CLK_DMIC_CLK_1"),
    480	PINCTRL_PIN(61, "SNDW3_DATA_DMIC_DATA_1"),
    481	PINCTRL_PIN(62, "SNDW4_CLK_DMIC_CLK_0"),
    482	PINCTRL_PIN(63, "SNDW4_DATA_DMIC_DATA_0"),
    483	/* GPP_R */
    484	PINCTRL_PIN(64, "HDA_BCLK"),
    485	PINCTRL_PIN(65, "HDA_SYNC"),
    486	PINCTRL_PIN(66, "HDA_SDO"),
    487	PINCTRL_PIN(67, "HDA_SDI_0"),
    488	PINCTRL_PIN(68, "HDA_RSTB"),
    489	PINCTRL_PIN(69, "HDA_SDI_1_I2S1_RXD"),
    490	PINCTRL_PIN(70, "I2S1_SFRM"),
    491	PINCTRL_PIN(71, "I2S1_TXD"),
    492	/* GPP_H */
    493	PINCTRL_PIN(72, "GPPC_H_0"),
    494	PINCTRL_PIN(73, "CNV_RF_RESET_B"),
    495	PINCTRL_PIN(74, "MODEM_CLKREQ"),
    496	PINCTRL_PIN(75, "SX_EXIT_HOLDOFFB"),
    497	PINCTRL_PIN(76, "I2C2_SDA"),
    498	PINCTRL_PIN(77, "I2C2_SCL"),
    499	PINCTRL_PIN(78, "I2C3_SDA"),
    500	PINCTRL_PIN(79, "I2C3_SCL"),
    501	PINCTRL_PIN(80, "I2C4_SDA"),
    502	PINCTRL_PIN(81, "I2C4_SCL"),
    503	PINCTRL_PIN(82, "CPU_VCCIO_PWR_GATEB"),
    504	PINCTRL_PIN(83, "I2S2_SCLK"),
    505	PINCTRL_PIN(84, "CNV_RF_RESET_B"),
    506	PINCTRL_PIN(85, "MODEM_CLKREQ"),
    507	PINCTRL_PIN(86, "I2S2_RXD"),
    508	PINCTRL_PIN(87, "I2S1_SCLK"),
    509	PINCTRL_PIN(88, "GPPC_H_16"),
    510	PINCTRL_PIN(89, "GPPC_H_17"),
    511	PINCTRL_PIN(90, "GPPC_H_18"),
    512	PINCTRL_PIN(91, "GPPC_H_19"),
    513	PINCTRL_PIN(92, "GPPC_H_20"),
    514	PINCTRL_PIN(93, "GPPC_H_21"),
    515	PINCTRL_PIN(94, "GPPC_H_22"),
    516	PINCTRL_PIN(95, "GPPC_H_23"),
    517	/* GPP_D */
    518	PINCTRL_PIN(96, "SPI1_CSB_BK_0_SBK_0"),
    519	PINCTRL_PIN(97, "SPI1_CLK_BK_1_SBK_1"),
    520	PINCTRL_PIN(98, "SPI1_MISO_IO_1_BK_2_SBK_2"),
    521	PINCTRL_PIN(99, "SPI1_MOSI_IO_0_BK_3_SBK_3"),
    522	PINCTRL_PIN(100, "ISH_I2C0_SDA"),
    523	PINCTRL_PIN(101, "ISH_I2C0_SCL"),
    524	PINCTRL_PIN(102, "ISH_I2C1_SDA"),
    525	PINCTRL_PIN(103, "ISH_I2C1_SCL"),
    526	PINCTRL_PIN(104, "ISH_SPI_CSB_GSPI2_CS0B_TBT_LSX4_A"),
    527	PINCTRL_PIN(105, "ISH_SPI_CLK_GSPI2_CLK_TBT_LSX4_B"),
    528	PINCTRL_PIN(106, "ISH_SPI_MISO_GSPI2_MISO_TBT_LSX5_A"),
    529	PINCTRL_PIN(107, "ISH_SPI_MOSI_GSPI2_MOSI_TBT_LSX5_B"),
    530	PINCTRL_PIN(108, "ISH_UART0_RXD_I2C4B_SDA"),
    531	PINCTRL_PIN(109, "ISH_UART0_TXD_I2C4B_SCL"),
    532	PINCTRL_PIN(110, "ISH_UART0_RTSB_GSPI2_CS1B"),
    533	PINCTRL_PIN(111, "ISH_UART0_CTSB_CNV_WCEN"),
    534	PINCTRL_PIN(112, "SPI1_IO_2"),
    535	PINCTRL_PIN(113, "SPI1_IO_3"),
    536	PINCTRL_PIN(114, "I2S_MCLK"),
    537	PINCTRL_PIN(115, "CNV_MFUART2_RXD"),
    538	PINCTRL_PIN(116, "CNV_MFUART2_TXD"),
    539	PINCTRL_PIN(117, "CNV_PA_BLANKING"),
    540	PINCTRL_PIN(118, "I2C5_SDA_ISH_I2C2_SDA"),
    541	PINCTRL_PIN(119, "I2C5_SCL_ISH_I2C2_SCL"),
    542	PINCTRL_PIN(120, "GSPI2_CLK_LOOPBK"),
    543	PINCTRL_PIN(121, "SPI1_CLK_LOOPBK"),
    544	/* vGPIO */
    545	PINCTRL_PIN(122, "CNV_BTEN"),
    546	PINCTRL_PIN(123, "CNV_WCEN"),
    547	PINCTRL_PIN(124, "CNV_BT_HOST_WAKEB"),
    548	PINCTRL_PIN(125, "CNV_BT_IF_SELECT"),
    549	PINCTRL_PIN(126, "vCNV_BT_UART_TXD"),
    550	PINCTRL_PIN(127, "vCNV_BT_UART_RXD"),
    551	PINCTRL_PIN(128, "vCNV_BT_UART_CTS_B"),
    552	PINCTRL_PIN(129, "vCNV_BT_UART_RTS_B"),
    553	PINCTRL_PIN(130, "vCNV_MFUART1_TXD"),
    554	PINCTRL_PIN(131, "vCNV_MFUART1_RXD"),
    555	PINCTRL_PIN(132, "vCNV_MFUART1_CTS_B"),
    556	PINCTRL_PIN(133, "vCNV_MFUART1_RTS_B"),
    557	PINCTRL_PIN(134, "vUART0_TXD"),
    558	PINCTRL_PIN(135, "vUART0_RXD"),
    559	PINCTRL_PIN(136, "vUART0_CTS_B"),
    560	PINCTRL_PIN(137, "vUART0_RTS_B"),
    561	PINCTRL_PIN(138, "vISH_UART0_TXD"),
    562	PINCTRL_PIN(139, "vISH_UART0_RXD"),
    563	PINCTRL_PIN(140, "vISH_UART0_CTS_B"),
    564	PINCTRL_PIN(141, "vISH_UART0_RTS_B"),
    565	PINCTRL_PIN(142, "vCNV_BT_I2S_BCLK"),
    566	PINCTRL_PIN(143, "vCNV_BT_I2S_WS_SYNC"),
    567	PINCTRL_PIN(144, "vCNV_BT_I2S_SDO"),
    568	PINCTRL_PIN(145, "vCNV_BT_I2S_SDI"),
    569	PINCTRL_PIN(146, "vI2S2_SCLK"),
    570	PINCTRL_PIN(147, "vI2S2_SFRM"),
    571	PINCTRL_PIN(148, "vI2S2_TXD"),
    572	PINCTRL_PIN(149, "vI2S2_RXD"),
    573	PINCTRL_PIN(150, "vSD3_CD_B"),
    574	/* GPP_C */
    575	PINCTRL_PIN(151, "GPPC_C_0"),
    576	PINCTRL_PIN(152, "GPPC_C_1"),
    577	PINCTRL_PIN(153, "GPPC_C_2"),
    578	PINCTRL_PIN(154, "GPPC_C_3"),
    579	PINCTRL_PIN(155, "GPPC_C_4"),
    580	PINCTRL_PIN(156, "GPPC_C_5"),
    581	PINCTRL_PIN(157, "SUSWARNB_SUSPWRDNACK"),
    582	PINCTRL_PIN(158, "SUSACKB"),
    583	PINCTRL_PIN(159, "UART0_RXD"),
    584	PINCTRL_PIN(160, "UART0_TXD"),
    585	PINCTRL_PIN(161, "UART0_RTSB"),
    586	PINCTRL_PIN(162, "UART0_CTSB"),
    587	PINCTRL_PIN(163, "UART1_RXD_ISH_UART1_RXD"),
    588	PINCTRL_PIN(164, "UART1_TXD_ISH_UART1_TXD"),
    589	PINCTRL_PIN(165, "UART1_RTSB_ISH_UART1_RTSB"),
    590	PINCTRL_PIN(166, "UART1_CTSB_ISH_UART1_CTSB"),
    591	PINCTRL_PIN(167, "I2C0_SDA"),
    592	PINCTRL_PIN(168, "I2C0_SCL"),
    593	PINCTRL_PIN(169, "I2C1_SDA"),
    594	PINCTRL_PIN(170, "I2C1_SCL"),
    595	PINCTRL_PIN(171, "UART2_RXD_CNV_MFUART0_RXD"),
    596	PINCTRL_PIN(172, "UART2_TXD_CNV_MFUART0_TXD"),
    597	PINCTRL_PIN(173, "UART2_RTSB_CNV_MFUART0_RTS_B"),
    598	PINCTRL_PIN(174, "UART2_CTSB_CNV_MFUART0_CTS_B"),
    599	/* HVCMOS */
    600	PINCTRL_PIN(175, "L_BKLTEN"),
    601	PINCTRL_PIN(176, "L_BKLTCTL"),
    602	PINCTRL_PIN(177, "L_VDDEN"),
    603	PINCTRL_PIN(178, "SYS_PWROK"),
    604	PINCTRL_PIN(179, "SYS_RESETB"),
    605	PINCTRL_PIN(180, "MLK_RSTB"),
    606	/* GPP_E */
    607	PINCTRL_PIN(181, "ISH_GP_0_IMGCLKOUT_0"),
    608	PINCTRL_PIN(182, "ISH_GP_1"),
    609	PINCTRL_PIN(183, "IMGCLKOUT_1"),
    610	PINCTRL_PIN(184, "ISH_GP_2_SATA_DEVSLP_0"),
    611	PINCTRL_PIN(185, "IMGCLKOUT_2"),
    612	PINCTRL_PIN(186, "SATA_LEDB_SPI1_CS1B"),
    613	PINCTRL_PIN(187, "IMGCLKOUT_3"),
    614	PINCTRL_PIN(188, "ISH_GP_3_SATA_DEVSLP_1"),
    615	PINCTRL_PIN(189, "FIVR_DIGPB_0"),
    616	PINCTRL_PIN(190, "SML0CLK"),
    617	PINCTRL_PIN(191, "SML0DATA"),
    618	PINCTRL_PIN(192, "BSSB_LS3_RX"),
    619	PINCTRL_PIN(193, "BSSB_LS3_TX"),
    620	PINCTRL_PIN(194, "BSSB_LS0_RX"),
    621	PINCTRL_PIN(195, "BSSB_LS0_TX"),
    622	PINCTRL_PIN(196, "BSSB_LS1_RX"),
    623	PINCTRL_PIN(197, "BSSB_LS1_TX"),
    624	PINCTRL_PIN(198, "BSSB_LS2_RX"),
    625	PINCTRL_PIN(199, "BSSB_LS2_TX"),
    626	PINCTRL_PIN(200, "FIVR_DIGPB_1"),
    627	PINCTRL_PIN(201, "CNV_BRI_DT"),
    628	PINCTRL_PIN(202, "CNV_BRI_RSP"),
    629	PINCTRL_PIN(203, "CNV_RGI_DT"),
    630	PINCTRL_PIN(204, "CNV_RGI_RSP"),
    631	/* GPP_G */
    632	PINCTRL_PIN(205, "SD3_CMD"),
    633	PINCTRL_PIN(206, "SD3_D0"),
    634	PINCTRL_PIN(207, "SD3_D1"),
    635	PINCTRL_PIN(208, "SD3_D2"),
    636	PINCTRL_PIN(209, "SD3_D3"),
    637	PINCTRL_PIN(210, "SD3_CDB"),
    638	PINCTRL_PIN(211, "SD3_CLK"),
    639	PINCTRL_PIN(212, "SD3_WP"),
    640};
    641
    642static const struct intel_padgroup icln_community0_gpps[] = {
    643	ICL_GPP(0, 0, 8, INTEL_GPIO_BASE_NOMAP),	/* SPI */
    644	ICL_GPP(1, 9, 34, 32),				/* GPP_B */
    645	ICL_GPP(2, 35, 55, 64),				/* GPP_A */
    646	ICL_GPP(3, 56, 63, 96),				/* GPP_S */
    647	ICL_GPP(4, 64, 71, 128),			/* GPP_R */
    648};
    649
    650static const struct intel_padgroup icln_community1_gpps[] = {
    651	ICL_GPP(0, 72, 95, 160),			/* GPP_H */
    652	ICL_GPP(1, 96, 121, 192),			/* GPP_D */
    653	ICL_GPP(2, 122, 150, 224),			/* vGPIO */
    654	ICL_GPP(3, 151, 174, 256),			/* GPP_C */
    655};
    656
    657static const struct intel_padgroup icln_community4_gpps[] = {
    658	ICL_GPP(0, 175, 180, INTEL_GPIO_BASE_NOMAP),	/* HVCMOS */
    659	ICL_GPP(1, 181, 204, 288),			/* GPP_E */
    660};
    661
    662static const struct intel_padgroup icln_community5_gpps[] = {
    663	ICL_GPP(0, 205, 212, INTEL_GPIO_BASE_ZERO),	/* GPP_G */
    664};
    665
    666static const struct intel_community icln_communities[] = {
    667	ICL_N_COMMUNITY(0, 0, 71, icln_community0_gpps),
    668	ICL_N_COMMUNITY(1, 72, 174, icln_community1_gpps),
    669	ICL_N_COMMUNITY(2, 175, 204, icln_community4_gpps),
    670	ICL_N_COMMUNITY(3, 205, 212, icln_community5_gpps),
    671};
    672
    673static const struct intel_pinctrl_soc_data icln_soc_data = {
    674	.pins = icln_pins,
    675	.npins = ARRAY_SIZE(icln_pins),
    676	.communities = icln_communities,
    677	.ncommunities = ARRAY_SIZE(icln_communities),
    678};
    679
    680static INTEL_PINCTRL_PM_OPS(icl_pinctrl_pm_ops);
    681
    682static const struct acpi_device_id icl_pinctrl_acpi_match[] = {
    683	{ "INT3455", (kernel_ulong_t)&icllp_soc_data },
    684	{ "INT34C3", (kernel_ulong_t)&icln_soc_data },
    685	{ }
    686};
    687MODULE_DEVICE_TABLE(acpi, icl_pinctrl_acpi_match);
    688
    689static struct platform_driver icl_pinctrl_driver = {
    690	.probe = intel_pinctrl_probe_by_hid,
    691	.driver = {
    692		.name = "icelake-pinctrl",
    693		.acpi_match_table = icl_pinctrl_acpi_match,
    694		.pm = &icl_pinctrl_pm_ops,
    695	},
    696};
    697
    698module_platform_driver(icl_pinctrl_driver);
    699
    700MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
    701MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
    702MODULE_DESCRIPTION("Intel Ice Lake PCH pinctrl/GPIO driver");
    703MODULE_LICENSE("GPL v2");