cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pinctrl-mt6797.c (2216B)

      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Based on pinctrl-mt6765.c
      4 *
      5 * Copyright (C) 2018 MediaTek Inc.
      6 *
      7 * Author: ZH Chen <zh.chen@mediatek.com>
      8 *
      9 * Copyright (C) Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
     10 *
     11 */
     12
     13#include "pinctrl-mtk-mt6797.h"
     14#include "pinctrl-paris.h"
     15
     16/*
     17 * MT6797 have multiple bases to program pin configuration listed as the below:
     18 * gpio:0x10005000, iocfg[l]:0x10002000, iocfg[b]:0x10002400,
     19 * iocfg[r]:0x10002800, iocfg[t]:0x10002C00.
     20 * _i_base could be used to indicate what base the pin should be mapped into.
     21 */
     22
     23static const struct mtk_pin_field_calc mt6797_pin_mode_range[] = {
     24	PIN_FIELD(0, 261, 0x300, 0x10, 0, 4),
     25};
     26
     27static const struct mtk_pin_field_calc mt6797_pin_dir_range[] = {
     28	PIN_FIELD(0, 261, 0x0, 0x10, 0, 1),
     29};
     30
     31static const struct mtk_pin_field_calc mt6797_pin_di_range[] = {
     32	PIN_FIELD(0, 261, 0x200, 0x10, 0, 1),
     33};
     34
     35static const struct mtk_pin_field_calc mt6797_pin_do_range[] = {
     36	PIN_FIELD(0, 261, 0x100, 0x10, 0, 1),
     37};
     38
     39static const struct mtk_pin_reg_calc mt6797_reg_cals[PINCTRL_PIN_REG_MAX] = {
     40	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6797_pin_mode_range),
     41	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6797_pin_dir_range),
     42	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6797_pin_di_range),
     43	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6797_pin_do_range),
     44};
     45
     46static const char * const mt6797_pinctrl_register_base_names[] = {
     47	"gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt",
     48};
     49
     50static const struct mtk_pin_soc mt6797_data = {
     51	.reg_cal = mt6797_reg_cals,
     52	.pins = mtk_pins_mt6797,
     53	.npins = ARRAY_SIZE(mtk_pins_mt6797),
     54	.ngrps = ARRAY_SIZE(mtk_pins_mt6797),
     55	.gpio_m = 0,
     56	.base_names = mt6797_pinctrl_register_base_names,
     57	.nbase_names = ARRAY_SIZE(mt6797_pinctrl_register_base_names),
     58};
     59
     60static const struct of_device_id mt6797_pinctrl_of_match[] = {
     61	{ .compatible = "mediatek,mt6797-pinctrl", .data = &mt6797_data },
     62	{ }
     63};
     64
     65static struct platform_driver mt6797_pinctrl_driver = {
     66	.driver = {
     67		.name = "mt6797-pinctrl",
     68		.of_match_table = mt6797_pinctrl_of_match,
     69	},
     70	.probe = mtk_paris_pinctrl_probe,
     71};
     72
     73static int __init mt6797_pinctrl_init(void)
     74{
     75	return platform_driver_register(&mt6797_pinctrl_driver);
     76}
     77arch_initcall(mt6797_pinctrl_init);