pinctrl-mt7629.c (17031B)
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * The MT7629 driver based on Linux generic pinctrl binding. 4 * 5 * Copyright (C) 2018 MediaTek Inc. 6 * Author: Ryder Lee <ryder.lee@mediatek.com> 7 */ 8 9#include "pinctrl-moore.h" 10 11#define MT7629_PIN(_number, _name, _eint_n) \ 12 MTK_PIN(_number, _name, 0, _eint_n, DRV_GRP1) 13 14static const struct mtk_pin_field_calc mt7629_pin_mode_range[] = { 15 PIN_FIELD(0, 78, 0x300, 0x10, 0, 4), 16}; 17 18static const struct mtk_pin_field_calc mt7629_pin_dir_range[] = { 19 PIN_FIELD(0, 78, 0x0, 0x10, 0, 1), 20}; 21 22static const struct mtk_pin_field_calc mt7629_pin_di_range[] = { 23 PIN_FIELD(0, 78, 0x200, 0x10, 0, 1), 24}; 25 26static const struct mtk_pin_field_calc mt7629_pin_do_range[] = { 27 PIN_FIELD(0, 78, 0x100, 0x10, 0, 1), 28}; 29 30static const struct mtk_pin_field_calc mt7629_pin_ies_range[] = { 31 PIN_FIELD(0, 10, 0x1000, 0x10, 0, 1), 32 PIN_FIELD(11, 18, 0x2000, 0x10, 0, 1), 33 PIN_FIELD(19, 32, 0x3000, 0x10, 0, 1), 34 PIN_FIELD(33, 48, 0x4000, 0x10, 0, 1), 35 PIN_FIELD(49, 50, 0x5000, 0x10, 0, 1), 36 PIN_FIELD(51, 69, 0x6000, 0x10, 0, 1), 37 PIN_FIELD(70, 78, 0x7000, 0x10, 0, 1), 38}; 39 40static const struct mtk_pin_field_calc mt7629_pin_smt_range[] = { 41 PIN_FIELD(0, 10, 0x1100, 0x10, 0, 1), 42 PIN_FIELD(11, 18, 0x2100, 0x10, 0, 1), 43 PIN_FIELD(19, 32, 0x3100, 0x10, 0, 1), 44 PIN_FIELD(33, 48, 0x4100, 0x10, 0, 1), 45 PIN_FIELD(49, 50, 0x5100, 0x10, 0, 1), 46 PIN_FIELD(51, 69, 0x6100, 0x10, 0, 1), 47 PIN_FIELD(70, 78, 0x7100, 0x10, 0, 1), 48}; 49 50static const struct mtk_pin_field_calc mt7629_pin_pullen_range[] = { 51 PIN_FIELD(0, 10, 0x1400, 0x10, 0, 1), 52 PIN_FIELD(11, 18, 0x2400, 0x10, 0, 1), 53 PIN_FIELD(19, 32, 0x3400, 0x10, 0, 1), 54 PIN_FIELD(33, 48, 0x4400, 0x10, 0, 1), 55 PIN_FIELD(49, 50, 0x5400, 0x10, 0, 1), 56 PIN_FIELD(51, 69, 0x6400, 0x10, 0, 1), 57 PIN_FIELD(70, 78, 0x7400, 0x10, 0, 1), 58}; 59 60static const struct mtk_pin_field_calc mt7629_pin_pullsel_range[] = { 61 PIN_FIELD(0, 10, 0x1500, 0x10, 0, 1), 62 PIN_FIELD(11, 18, 0x2500, 0x10, 0, 1), 63 PIN_FIELD(19, 32, 0x3500, 0x10, 0, 1), 64 PIN_FIELD(33, 48, 0x4500, 0x10, 0, 1), 65 PIN_FIELD(49, 50, 0x5500, 0x10, 0, 1), 66 PIN_FIELD(51, 69, 0x6500, 0x10, 0, 1), 67 PIN_FIELD(70, 78, 0x7500, 0x10, 0, 1), 68}; 69 70static const struct mtk_pin_field_calc mt7629_pin_drv_range[] = { 71 PIN_FIELD(0, 10, 0x1600, 0x10, 0, 4), 72 PIN_FIELD(11, 18, 0x2600, 0x10, 0, 4), 73 PIN_FIELD(19, 32, 0x3600, 0x10, 0, 4), 74 PIN_FIELD(33, 48, 0x4600, 0x10, 0, 4), 75 PIN_FIELD(49, 50, 0x5600, 0x10, 0, 4), 76 PIN_FIELD(51, 69, 0x6600, 0x10, 0, 4), 77 PIN_FIELD(70, 78, 0x7600, 0x10, 0, 4), 78}; 79 80static const struct mtk_pin_field_calc mt7629_pin_tdsel_range[] = { 81 PIN_FIELD(0, 10, 0x1200, 0x10, 0, 4), 82 PIN_FIELD(11, 18, 0x2200, 0x10, 0, 4), 83 PIN_FIELD(19, 32, 0x3200, 0x10, 0, 4), 84 PIN_FIELD(33, 48, 0x4200, 0x10, 0, 4), 85 PIN_FIELD(49, 50, 0x5200, 0x10, 0, 4), 86 PIN_FIELD(51, 69, 0x6200, 0x10, 0, 4), 87 PIN_FIELD(70, 78, 0x7200, 0x10, 0, 4), 88}; 89 90static const struct mtk_pin_field_calc mt7629_pin_rdsel_range[] = { 91 PIN_FIELD(0, 10, 0x1300, 0x10, 0, 4), 92 PIN_FIELD(11, 18, 0x2300, 0x10, 0, 4), 93 PIN_FIELD(19, 32, 0x3300, 0x10, 0, 4), 94 PIN_FIELD(33, 48, 0x4300, 0x10, 0, 4), 95 PIN_FIELD(49, 50, 0x5300, 0x10, 0, 4), 96 PIN_FIELD(51, 69, 0x6300, 0x10, 0, 4), 97 PIN_FIELD(70, 78, 0x7300, 0x10, 0, 4), 98}; 99 100static const struct mtk_pin_reg_calc mt7629_reg_cals[] = { 101 [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7629_pin_mode_range), 102 [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7629_pin_dir_range), 103 [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7629_pin_di_range), 104 [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7629_pin_do_range), 105 [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7629_pin_ies_range), 106 [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7629_pin_smt_range), 107 [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt7629_pin_pullsel_range), 108 [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt7629_pin_pullen_range), 109 [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7629_pin_drv_range), 110 [PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt7629_pin_tdsel_range), 111 [PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt7629_pin_rdsel_range), 112}; 113 114static const struct mtk_pin_desc mt7629_pins[] = { 115 MT7629_PIN(0, "TOP_5G_CLK", 53), 116 MT7629_PIN(1, "TOP_5G_DATA", 54), 117 MT7629_PIN(2, "WF0_5G_HB0", 55), 118 MT7629_PIN(3, "WF0_5G_HB1", 56), 119 MT7629_PIN(4, "WF0_5G_HB2", 57), 120 MT7629_PIN(5, "WF0_5G_HB3", 58), 121 MT7629_PIN(6, "WF0_5G_HB4", 59), 122 MT7629_PIN(7, "WF0_5G_HB5", 60), 123 MT7629_PIN(8, "WF0_5G_HB6", 61), 124 MT7629_PIN(9, "XO_REQ", 9), 125 MT7629_PIN(10, "TOP_RST_N", 10), 126 MT7629_PIN(11, "SYS_WATCHDOG", 11), 127 MT7629_PIN(12, "EPHY_LED0_N_JTDO", 12), 128 MT7629_PIN(13, "EPHY_LED1_N_JTDI", 13), 129 MT7629_PIN(14, "EPHY_LED2_N_JTMS", 14), 130 MT7629_PIN(15, "EPHY_LED3_N_JTCLK", 15), 131 MT7629_PIN(16, "EPHY_LED4_N_JTRST_N", 16), 132 MT7629_PIN(17, "WF2G_LED_N", 17), 133 MT7629_PIN(18, "WF5G_LED_N", 18), 134 MT7629_PIN(19, "I2C_SDA", 19), 135 MT7629_PIN(20, "I2C_SCL", 20), 136 MT7629_PIN(21, "GPIO_9", 21), 137 MT7629_PIN(22, "GPIO_10", 22), 138 MT7629_PIN(23, "GPIO_11", 23), 139 MT7629_PIN(24, "GPIO_12", 24), 140 MT7629_PIN(25, "UART1_TXD", 25), 141 MT7629_PIN(26, "UART1_RXD", 26), 142 MT7629_PIN(27, "UART1_CTS", 27), 143 MT7629_PIN(28, "UART1_RTS", 28), 144 MT7629_PIN(29, "UART2_TXD", 29), 145 MT7629_PIN(30, "UART2_RXD", 30), 146 MT7629_PIN(31, "UART2_CTS", 31), 147 MT7629_PIN(32, "UART2_RTS", 32), 148 MT7629_PIN(33, "MDI_TP_P1", 33), 149 MT7629_PIN(34, "MDI_TN_P1", 34), 150 MT7629_PIN(35, "MDI_RP_P1", 35), 151 MT7629_PIN(36, "MDI_RN_P1", 36), 152 MT7629_PIN(37, "MDI_RP_P2", 37), 153 MT7629_PIN(38, "MDI_RN_P2", 38), 154 MT7629_PIN(39, "MDI_TP_P2", 39), 155 MT7629_PIN(40, "MDI_TN_P2", 40), 156 MT7629_PIN(41, "MDI_TP_P3", 41), 157 MT7629_PIN(42, "MDI_TN_P3", 42), 158 MT7629_PIN(43, "MDI_RP_P3", 43), 159 MT7629_PIN(44, "MDI_RN_P3", 44), 160 MT7629_PIN(45, "MDI_RP_P4", 45), 161 MT7629_PIN(46, "MDI_RN_P4", 46), 162 MT7629_PIN(47, "MDI_TP_P4", 47), 163 MT7629_PIN(48, "MDI_TN_P4", 48), 164 MT7629_PIN(49, "SMI_MDC", 49), 165 MT7629_PIN(50, "SMI_MDIO", 50), 166 MT7629_PIN(51, "PCIE_PERESET_N", 51), 167 MT7629_PIN(52, "PWM_0", 52), 168 MT7629_PIN(53, "GPIO_0", 0), 169 MT7629_PIN(54, "GPIO_1", 1), 170 MT7629_PIN(55, "GPIO_2", 2), 171 MT7629_PIN(56, "GPIO_3", 3), 172 MT7629_PIN(57, "GPIO_4", 4), 173 MT7629_PIN(58, "GPIO_5", 5), 174 MT7629_PIN(59, "GPIO_6", 6), 175 MT7629_PIN(60, "GPIO_7", 7), 176 MT7629_PIN(61, "GPIO_8", 8), 177 MT7629_PIN(62, "SPI_CLK", 62), 178 MT7629_PIN(63, "SPI_CS", 63), 179 MT7629_PIN(64, "SPI_MOSI", 64), 180 MT7629_PIN(65, "SPI_MISO", 65), 181 MT7629_PIN(66, "SPI_WP", 66), 182 MT7629_PIN(67, "SPI_HOLD", 67), 183 MT7629_PIN(68, "UART0_TXD", 68), 184 MT7629_PIN(69, "UART0_RXD", 69), 185 MT7629_PIN(70, "TOP_2G_CLK", 70), 186 MT7629_PIN(71, "TOP_2G_DATA", 71), 187 MT7629_PIN(72, "WF0_2G_HB0", 72), 188 MT7629_PIN(73, "WF0_2G_HB1", 73), 189 MT7629_PIN(74, "WF0_2G_HB2", 74), 190 MT7629_PIN(75, "WF0_2G_HB3", 75), 191 MT7629_PIN(76, "WF0_2G_HB4", 76), 192 MT7629_PIN(77, "WF0_2G_HB5", 77), 193 MT7629_PIN(78, "WF0_2G_HB6", 78), 194}; 195 196/* List all groups consisting of these pins dedicated to the enablement of 197 * certain hardware block and the corresponding mode for all of the pins. 198 * The hardware probably has multiple combinations of these pinouts. 199 */ 200 201/* LED for EPHY */ 202static int mt7629_ephy_leds_pins[] = { 12, 13, 14, 15, 16, 17, 18, }; 203static int mt7629_ephy_leds_funcs[] = { 1, 1, 1, 1, 1, 1, 1, }; 204static int mt7629_ephy_led0_pins[] = { 12, }; 205static int mt7629_ephy_led0_funcs[] = { 1, }; 206static int mt7629_ephy_led1_pins[] = { 13, }; 207static int mt7629_ephy_led1_funcs[] = { 1, }; 208static int mt7629_ephy_led2_pins[] = { 14, }; 209static int mt7629_ephy_led2_funcs[] = { 1, }; 210static int mt7629_ephy_led3_pins[] = { 15, }; 211static int mt7629_ephy_led3_funcs[] = { 1, }; 212static int mt7629_ephy_led4_pins[] = { 16, }; 213static int mt7629_ephy_led4_funcs[] = { 1, }; 214static int mt7629_wf2g_led_pins[] = { 17, }; 215static int mt7629_wf2g_led_funcs[] = { 1, }; 216static int mt7629_wf5g_led_pins[] = { 18, }; 217static int mt7629_wf5g_led_funcs[] = { 1, }; 218 219/* Watchdog */ 220static int mt7629_watchdog_pins[] = { 11, }; 221static int mt7629_watchdog_funcs[] = { 1, }; 222 223/* LED for GPHY */ 224static int mt7629_gphy_leds_0_pins[] = { 21, 22, 23, }; 225static int mt7629_gphy_leds_0_funcs[] = { 2, 2, 2, }; 226static int mt7629_gphy_led1_0_pins[] = { 21, }; 227static int mt7629_gphy_led1_0_funcs[] = { 2, }; 228static int mt7629_gphy_led2_0_pins[] = { 22, }; 229static int mt7629_gphy_led2_0_funcs[] = { 2, }; 230static int mt7629_gphy_led3_0_pins[] = { 23, }; 231static int mt7629_gphy_led3_0_funcs[] = { 2, }; 232static int mt7629_gphy_leds_1_pins[] = { 57, 58, 59, }; 233static int mt7629_gphy_leds_1_funcs[] = { 1, 1, 1, }; 234static int mt7629_gphy_led1_1_pins[] = { 57, }; 235static int mt7629_gphy_led1_1_funcs[] = { 1, }; 236static int mt7629_gphy_led2_1_pins[] = { 58, }; 237static int mt7629_gphy_led2_1_funcs[] = { 1, }; 238static int mt7629_gphy_led3_1_pins[] = { 59, }; 239static int mt7629_gphy_led3_1_funcs[] = { 1, }; 240 241/* I2C */ 242static int mt7629_i2c_0_pins[] = { 19, 20, }; 243static int mt7629_i2c_0_funcs[] = { 1, 1, }; 244static int mt7629_i2c_1_pins[] = { 53, 54, }; 245static int mt7629_i2c_1_funcs[] = { 1, 1, }; 246 247/* SPI */ 248static int mt7629_spi_0_pins[] = { 21, 22, 23, 24, }; 249static int mt7629_spi_0_funcs[] = { 1, 1, 1, 1, }; 250static int mt7629_spi_1_pins[] = { 62, 63, 64, 65, }; 251static int mt7629_spi_1_funcs[] = { 1, 1, 1, 1, }; 252static int mt7629_spi_wp_pins[] = { 66, }; 253static int mt7629_spi_wp_funcs[] = { 1, }; 254static int mt7629_spi_hold_pins[] = { 67, }; 255static int mt7629_spi_hold_funcs[] = { 1, }; 256 257/* UART */ 258static int mt7629_uart1_0_txd_rxd_pins[] = { 25, 26, }; 259static int mt7629_uart1_0_txd_rxd_funcs[] = { 1, 1, }; 260static int mt7629_uart1_1_txd_rxd_pins[] = { 53, 54, }; 261static int mt7629_uart1_1_txd_rxd_funcs[] = { 2, 2, }; 262static int mt7629_uart2_0_txd_rxd_pins[] = { 29, 30, }; 263static int mt7629_uart2_0_txd_rxd_funcs[] = { 1, 1, }; 264static int mt7629_uart2_1_txd_rxd_pins[] = { 57, 58, }; 265static int mt7629_uart2_1_txd_rxd_funcs[] = { 2, 2, }; 266static int mt7629_uart1_0_cts_rts_pins[] = { 27, 28, }; 267static int mt7629_uart1_0_cts_rts_funcs[] = { 1, 1, }; 268static int mt7629_uart1_1_cts_rts_pins[] = { 55, 56, }; 269static int mt7629_uart1_1_cts_rts_funcs[] = { 2, 2, }; 270static int mt7629_uart2_0_cts_rts_pins[] = { 31, 32, }; 271static int mt7629_uart2_0_cts_rts_funcs[] = { 1, 1, }; 272static int mt7629_uart2_1_cts_rts_pins[] = { 59, 60, }; 273static int mt7629_uart2_1_cts_rts_funcs[] = { 2, 2, }; 274static int mt7629_uart0_txd_rxd_pins[] = { 68, 69, }; 275static int mt7629_uart0_txd_rxd_funcs[] = { 1, 1, }; 276 277/* MDC/MDIO */ 278static int mt7629_mdc_mdio_pins[] = { 49, 50, }; 279static int mt7629_mdc_mdio_funcs[] = { 1, 1, }; 280 281/* PCIE */ 282static int mt7629_pcie_pereset_pins[] = { 51, }; 283static int mt7629_pcie_pereset_funcs[] = { 1, }; 284static int mt7629_pcie_wake_pins[] = { 55, }; 285static int mt7629_pcie_wake_funcs[] = { 1, }; 286static int mt7629_pcie_clkreq_pins[] = { 56, }; 287static int mt7629_pcie_clkreq_funcs[] = { 1, }; 288 289/* PWM */ 290static int mt7629_pwm_0_pins[] = { 52, }; 291static int mt7629_pwm_0_funcs[] = { 1, }; 292static int mt7629_pwm_1_pins[] = { 61, }; 293static int mt7629_pwm_1_funcs[] = { 2, }; 294 295/* WF 2G */ 296static int mt7629_wf0_2g_pins[] = { 70, 71, 72, 73, 74, 75, 76, 77, 78, }; 297static int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, }; 298 299/* WF 5G */ 300static int mt7629_wf0_5g_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, }; 301static int mt7629_wf0_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; 302 303/* SNFI */ 304static int mt7629_snfi_pins[] = { 62, 63, 64, 65, 66, 67 }; 305static int mt7629_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 }; 306 307/* SPI NOR */ 308static int mt7629_snor_pins[] = { 62, 63, 64, 65, 66, 67 }; 309static int mt7629_snor_funcs[] = { 1, 1, 1, 1, 1, 1 }; 310 311static const struct group_desc mt7629_groups[] = { 312 PINCTRL_PIN_GROUP("ephy_leds", mt7629_ephy_leds), 313 PINCTRL_PIN_GROUP("ephy_led0", mt7629_ephy_led0), 314 PINCTRL_PIN_GROUP("ephy_led1", mt7629_ephy_led1), 315 PINCTRL_PIN_GROUP("ephy_led2", mt7629_ephy_led2), 316 PINCTRL_PIN_GROUP("ephy_led3", mt7629_ephy_led3), 317 PINCTRL_PIN_GROUP("ephy_led4", mt7629_ephy_led4), 318 PINCTRL_PIN_GROUP("wf2g_led", mt7629_wf2g_led), 319 PINCTRL_PIN_GROUP("wf5g_led", mt7629_wf5g_led), 320 PINCTRL_PIN_GROUP("watchdog", mt7629_watchdog), 321 PINCTRL_PIN_GROUP("gphy_leds_0", mt7629_gphy_leds_0), 322 PINCTRL_PIN_GROUP("gphy_led1_0", mt7629_gphy_led1_0), 323 PINCTRL_PIN_GROUP("gphy_led2_0", mt7629_gphy_led2_0), 324 PINCTRL_PIN_GROUP("gphy_led3_0", mt7629_gphy_led3_0), 325 PINCTRL_PIN_GROUP("gphy_leds_1", mt7629_gphy_leds_1), 326 PINCTRL_PIN_GROUP("gphy_led1_1", mt7629_gphy_led1_1), 327 PINCTRL_PIN_GROUP("gphy_led2_1", mt7629_gphy_led2_1), 328 PINCTRL_PIN_GROUP("gphy_led3_1", mt7629_gphy_led3_1), 329 PINCTRL_PIN_GROUP("i2c_0", mt7629_i2c_0), 330 PINCTRL_PIN_GROUP("i2c_1", mt7629_i2c_1), 331 PINCTRL_PIN_GROUP("spi_0", mt7629_spi_0), 332 PINCTRL_PIN_GROUP("spi_1", mt7629_spi_1), 333 PINCTRL_PIN_GROUP("spi_wp", mt7629_spi_wp), 334 PINCTRL_PIN_GROUP("spi_hold", mt7629_spi_hold), 335 PINCTRL_PIN_GROUP("uart1_0_txd_rxd", mt7629_uart1_0_txd_rxd), 336 PINCTRL_PIN_GROUP("uart1_1_txd_rxd", mt7629_uart1_1_txd_rxd), 337 PINCTRL_PIN_GROUP("uart2_0_txd_rxd", mt7629_uart2_0_txd_rxd), 338 PINCTRL_PIN_GROUP("uart2_1_txd_rxd", mt7629_uart2_1_txd_rxd), 339 PINCTRL_PIN_GROUP("uart1_0_cts_rts", mt7629_uart1_0_cts_rts), 340 PINCTRL_PIN_GROUP("uart1_1_cts_rts", mt7629_uart1_1_cts_rts), 341 PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7629_uart2_0_cts_rts), 342 PINCTRL_PIN_GROUP("uart2_1_cts_rts", mt7629_uart2_1_cts_rts), 343 PINCTRL_PIN_GROUP("uart0_txd_rxd", mt7629_uart0_txd_rxd), 344 PINCTRL_PIN_GROUP("mdc_mdio", mt7629_mdc_mdio), 345 PINCTRL_PIN_GROUP("pcie_pereset", mt7629_pcie_pereset), 346 PINCTRL_PIN_GROUP("pcie_wake", mt7629_pcie_wake), 347 PINCTRL_PIN_GROUP("pcie_clkreq", mt7629_pcie_clkreq), 348 PINCTRL_PIN_GROUP("pwm_0", mt7629_pwm_0), 349 PINCTRL_PIN_GROUP("pwm_1", mt7629_pwm_1), 350 PINCTRL_PIN_GROUP("wf0_5g", mt7629_wf0_5g), 351 PINCTRL_PIN_GROUP("wf0_2g", mt7629_wf0_2g), 352 PINCTRL_PIN_GROUP("snfi", mt7629_snfi), 353 PINCTRL_PIN_GROUP("spi_nor", mt7629_snor), 354}; 355 356/* Joint those groups owning the same capability in user point of view which 357 * allows that people tend to use through the device tree. 358 */ 359static const char *mt7629_ethernet_groups[] = { "mdc_mdio", }; 360static const char *mt7629_i2c_groups[] = { "i2c_0", "i2c_1", }; 361static const char *mt7629_led_groups[] = { "ephy_leds", "ephy_led0", 362 "ephy_led1", "ephy_led2", 363 "ephy_led3", "ephy_led4", 364 "wf2g_led", "wf5g_led", 365 "gphy_leds_0", "gphy_led1_0", 366 "gphy_led2_0", "gphy_led3_0", 367 "gphy_leds_1", "gphy_led1_1", 368 "gphy_led2_1", "gphy_led3_1",}; 369static const char *mt7629_pcie_groups[] = { "pcie_pereset", "pcie_wake", 370 "pcie_clkreq", }; 371static const char *mt7629_pwm_groups[] = { "pwm_0", "pwm_1", }; 372static const char *mt7629_spi_groups[] = { "spi_0", "spi_1", "spi_wp", 373 "spi_hold", }; 374static const char *mt7629_uart_groups[] = { "uart1_0_txd_rxd", 375 "uart1_1_txd_rxd", 376 "uart2_0_txd_rxd", 377 "uart2_1_txd_rxd", 378 "uart1_0_cts_rts", 379 "uart1_1_cts_rts", 380 "uart2_0_cts_rts", 381 "uart2_1_cts_rts", 382 "uart0_txd_rxd", }; 383static const char *mt7629_wdt_groups[] = { "watchdog", }; 384static const char *mt7629_wifi_groups[] = { "wf0_5g", "wf0_2g", }; 385static const char *mt7629_flash_groups[] = { "snfi", "spi_nor" }; 386 387static const struct function_desc mt7629_functions[] = { 388 {"eth", mt7629_ethernet_groups, ARRAY_SIZE(mt7629_ethernet_groups)}, 389 {"i2c", mt7629_i2c_groups, ARRAY_SIZE(mt7629_i2c_groups)}, 390 {"led", mt7629_led_groups, ARRAY_SIZE(mt7629_led_groups)}, 391 {"pcie", mt7629_pcie_groups, ARRAY_SIZE(mt7629_pcie_groups)}, 392 {"pwm", mt7629_pwm_groups, ARRAY_SIZE(mt7629_pwm_groups)}, 393 {"spi", mt7629_spi_groups, ARRAY_SIZE(mt7629_spi_groups)}, 394 {"uart", mt7629_uart_groups, ARRAY_SIZE(mt7629_uart_groups)}, 395 {"watchdog", mt7629_wdt_groups, ARRAY_SIZE(mt7629_wdt_groups)}, 396 {"wifi", mt7629_wifi_groups, ARRAY_SIZE(mt7629_wifi_groups)}, 397 {"flash", mt7629_flash_groups, ARRAY_SIZE(mt7629_flash_groups)}, 398}; 399 400static const struct mtk_eint_hw mt7629_eint_hw = { 401 .port_mask = 7, 402 .ports = 7, 403 .ap_num = ARRAY_SIZE(mt7629_pins), 404 .db_cnt = 16, 405}; 406 407static struct mtk_pin_soc mt7629_data = { 408 .reg_cal = mt7629_reg_cals, 409 .pins = mt7629_pins, 410 .npins = ARRAY_SIZE(mt7629_pins), 411 .grps = mt7629_groups, 412 .ngrps = ARRAY_SIZE(mt7629_groups), 413 .funcs = mt7629_functions, 414 .nfuncs = ARRAY_SIZE(mt7629_functions), 415 .eint_hw = &mt7629_eint_hw, 416 .gpio_m = 0, 417 .ies_present = true, 418 .base_names = mtk_default_register_base_names, 419 .nbase_names = ARRAY_SIZE(mtk_default_register_base_names), 420 .bias_disable_set = mtk_pinconf_bias_disable_set_rev1, 421 .bias_disable_get = mtk_pinconf_bias_disable_get_rev1, 422 .bias_set = mtk_pinconf_bias_set_rev1, 423 .bias_get = mtk_pinconf_bias_get_rev1, 424 .drive_set = mtk_pinconf_drive_set_rev1, 425 .drive_get = mtk_pinconf_drive_get_rev1, 426}; 427 428static const struct of_device_id mt7629_pinctrl_of_match[] = { 429 { .compatible = "mediatek,mt7629-pinctrl", }, 430 {} 431}; 432 433static int mt7629_pinctrl_probe(struct platform_device *pdev) 434{ 435 return mtk_moore_pinctrl_probe(pdev, &mt7629_data); 436} 437 438static struct platform_driver mt7629_pinctrl_driver = { 439 .driver = { 440 .name = "mt7629-pinctrl", 441 .of_match_table = mt7629_pinctrl_of_match, 442 }, 443 .probe = mt7629_pinctrl_probe, 444}; 445 446static int __init mt7629_pinctrl_init(void) 447{ 448 return platform_driver_register(&mt7629_pinctrl_driver); 449} 450arch_initcall(mt7629_pinctrl_init);