cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pinctrl-meson.h (4682B)


      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * Pin controller and GPIO driver for Amlogic Meson SoCs
      4 *
      5 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
      6 */
      7
      8#include <linux/gpio/driver.h>
      9#include <linux/pinctrl/pinctrl.h>
     10#include <linux/platform_device.h>
     11#include <linux/regmap.h>
     12#include <linux/types.h>
     13#include <linux/module.h>
     14
     15struct meson_pinctrl;
     16
     17/**
     18 * struct meson_pmx_group - a pinmux group
     19 *
     20 * @name:	group name
     21 * @pins:	pins in the group
     22 * @num_pins:	number of pins in the group
     23 * @is_gpio:	whether the group is a single GPIO group
     24 * @reg:	register offset for the group in the domain mux registers
     25 * @bit		bit index enabling the group
     26 * @domain:	index of the domain this group belongs to
     27 */
     28struct meson_pmx_group {
     29	const char *name;
     30	const unsigned int *pins;
     31	unsigned int num_pins;
     32	const void *data;
     33};
     34
     35/**
     36 * struct meson_pmx_func - a pinmux function
     37 *
     38 * @name:	function name
     39 * @groups:	groups in the function
     40 * @num_groups:	number of groups in the function
     41 */
     42struct meson_pmx_func {
     43	const char *name;
     44	const char * const *groups;
     45	unsigned int num_groups;
     46};
     47
     48/**
     49 * struct meson_reg_desc - a register descriptor
     50 *
     51 * @reg:	register offset in the regmap
     52 * @bit:	bit index in register
     53 *
     54 * The structure describes the information needed to control pull,
     55 * pull-enable, direction, etc. for a single pin
     56 */
     57struct meson_reg_desc {
     58	unsigned int reg;
     59	unsigned int bit;
     60};
     61
     62/**
     63 * enum meson_reg_type - type of registers encoded in @meson_reg_desc
     64 */
     65enum meson_reg_type {
     66	MESON_REG_PULLEN,
     67	MESON_REG_PULL,
     68	MESON_REG_DIR,
     69	MESON_REG_OUT,
     70	MESON_REG_IN,
     71	MESON_REG_DS,
     72	MESON_NUM_REG,
     73};
     74
     75/**
     76 * enum meson_pinconf_drv - value of drive-strength supported
     77 */
     78enum meson_pinconf_drv {
     79	MESON_PINCONF_DRV_500UA,
     80	MESON_PINCONF_DRV_2500UA,
     81	MESON_PINCONF_DRV_3000UA,
     82	MESON_PINCONF_DRV_4000UA,
     83};
     84
     85/**
     86 * struct meson bank
     87 *
     88 * @name:	bank name
     89 * @first:	first pin of the bank
     90 * @last:	last pin of the bank
     91 * @irq:	hwirq base number of the bank
     92 * @regs:	array of register descriptors
     93 *
     94 * A bank represents a set of pins controlled by a contiguous set of
     95 * bits in the domain registers. The structure specifies which bits in
     96 * the regmap control the different functionalities. Each member of
     97 * the @regs array refers to the first pin of the bank.
     98 */
     99struct meson_bank {
    100	const char *name;
    101	unsigned int first;
    102	unsigned int last;
    103	int irq_first;
    104	int irq_last;
    105	struct meson_reg_desc regs[MESON_NUM_REG];
    106};
    107
    108struct meson_pinctrl_data {
    109	const char *name;
    110	const struct pinctrl_pin_desc *pins;
    111	struct meson_pmx_group *groups;
    112	struct meson_pmx_func *funcs;
    113	unsigned int num_pins;
    114	unsigned int num_groups;
    115	unsigned int num_funcs;
    116	struct meson_bank *banks;
    117	unsigned int num_banks;
    118	const struct pinmux_ops *pmx_ops;
    119	void *pmx_data;
    120	int (*parse_dt)(struct meson_pinctrl *pc);
    121};
    122
    123struct meson_pinctrl {
    124	struct device *dev;
    125	struct pinctrl_dev *pcdev;
    126	struct pinctrl_desc desc;
    127	struct meson_pinctrl_data *data;
    128	struct regmap *reg_mux;
    129	struct regmap *reg_pullen;
    130	struct regmap *reg_pull;
    131	struct regmap *reg_gpio;
    132	struct regmap *reg_ds;
    133	struct gpio_chip chip;
    134	struct device_node *of_node;
    135};
    136
    137#define FUNCTION(fn)							\
    138	{								\
    139		.name = #fn,						\
    140		.groups = fn ## _groups,				\
    141		.num_groups = ARRAY_SIZE(fn ## _groups),		\
    142	}
    143
    144#define BANK_DS(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib,     \
    145		dsr, dsb)                                                      \
    146	{								\
    147		.name		= n,					\
    148		.first		= f,					\
    149		.last		= l,					\
    150		.irq_first	= fi,					\
    151		.irq_last	= li,					\
    152		.regs = {						\
    153			[MESON_REG_PULLEN]	= { per, peb },		\
    154			[MESON_REG_PULL]	= { pr, pb },		\
    155			[MESON_REG_DIR]		= { dr, db },		\
    156			[MESON_REG_OUT]		= { or, ob },		\
    157			[MESON_REG_IN]		= { ir, ib },		\
    158			[MESON_REG_DS]		= { dsr, dsb },		\
    159		},							\
    160	 }
    161
    162#define BANK(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib) \
    163	BANK_DS(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib, 0, 0)
    164
    165#define MESON_PIN(x) PINCTRL_PIN(x, #x)
    166
    167/* Common pmx functions */
    168int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev);
    169const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev,
    170				    unsigned selector);
    171int meson_pmx_get_groups(struct pinctrl_dev *pcdev,
    172			 unsigned selector,
    173			 const char * const **groups,
    174			 unsigned * const num_groups);
    175
    176/* Common probe function */
    177int meson_pinctrl_probe(struct platform_device *pdev);
    178/* Common ao groups extra dt parse function for SoCs before g12a  */
    179int meson8_aobus_parse_dt_extra(struct meson_pinctrl *pc);
    180/* Common extra dt parse function for SoCs like A1  */
    181int meson_a1_parse_dt_extra(struct meson_pinctrl *pc);