cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pinctrl-pic32.h (2708B)


      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * PIC32 pinctrl driver
      4 *
      5 * Joshua Henderson, <joshua.henderson@microchip.com>
      6 * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
      7 */
      8#ifndef PINCTRL_PINCTRL_PIC32_H
      9#define PINCTRL_PINCTRL_PIC32_H
     10
     11/* PORT Registers */
     12#define ANSEL_REG	0x00
     13#define TRIS_REG	0x10
     14#define PORT_REG	0x20
     15#define LAT_REG		0x30
     16#define ODCU_REG	0x40
     17#define CNPU_REG	0x50
     18#define CNPD_REG	0x60
     19#define CNCON_REG	0x70
     20#define CNEN_REG	0x80
     21#define CNSTAT_REG	0x90
     22#define CNNE_REG	0xA0
     23#define CNF_REG		0xB0
     24
     25/* Input PPS Registers */
     26#define INT1R 0x04
     27#define INT2R 0x08
     28#define INT3R 0x0C
     29#define INT4R 0x10
     30#define T2CKR 0x18
     31#define T3CKR 0x1C
     32#define T4CKR 0x20
     33#define T5CKR 0x24
     34#define T6CKR 0x28
     35#define T7CKR 0x2C
     36#define T8CKR 0x30
     37#define T9CKR 0x34
     38#define IC1R 0x38
     39#define IC2R 0x3C
     40#define IC3R 0x40
     41#define IC4R 0x44
     42#define IC5R 0x48
     43#define IC6R 0x4C
     44#define IC7R 0x50
     45#define IC8R 0x54
     46#define IC9R 0x58
     47#define OCFAR 0x60
     48#define U1RXR 0x68
     49#define U1CTSR 0x6C
     50#define U2RXR 0x70
     51#define U2CTSR 0x74
     52#define U3RXR 0x78
     53#define U3CTSR 0x7C
     54#define U4RXR 0x80
     55#define U4CTSR 0x84
     56#define U5RXR 0x88
     57#define U5CTSR 0x8C
     58#define U6RXR 0x90
     59#define U6CTSR 0x94
     60#define SDI1R 0x9C
     61#define SS1INR 0xA0
     62#define SDI2R 0xA8
     63#define SS2INR 0xAC
     64#define SDI3R 0xB4
     65#define SS3INR 0xB8
     66#define SDI4R 0xC0
     67#define SS4INR 0xC4
     68#define SDI5R 0xCC
     69#define SS5INR 0xD0
     70#define SDI6R 0xD8
     71#define SS6INR 0xDC
     72#define C1RXR 0xE0
     73#define C2RXR 0xE4
     74#define REFCLKI1R 0xE8
     75#define REFCLKI3R 0xF0
     76#define REFCLKI4R 0xF4
     77
     78/* Output PPS Registers */
     79#define RPA14R 0x138
     80#define RPA15R 0x13C
     81#define RPB0R 0x140
     82#define RPB1R 0x144
     83#define RPB2R 0x148
     84#define RPB3R 0x14C
     85#define RPB5R 0x154
     86#define RPB6R 0x158
     87#define RPB7R 0x15C
     88#define RPB8R 0x160
     89#define RPB9R 0x164
     90#define RPB10R 0x168
     91#define RPB14R 0x178
     92#define RPB15R 0x17C
     93#define RPC1R 0x184
     94#define RPC2R 0x188
     95#define RPC3R 0x18C
     96#define RPC4R 0x190
     97#define RPC13R 0x1B4
     98#define RPC14R 0x1B8
     99#define RPD0R 0x1C0
    100#define RPD1R 0x1C4
    101#define RPD2R 0x1C8
    102#define RPD3R 0x1CC
    103#define RPD4R 0x1D0
    104#define RPD5R 0x1D4
    105#define RPD6R 0x1D8
    106#define RPD7R 0x1DC
    107#define RPD9R 0x1E4
    108#define RPD10R 0x1E8
    109#define RPD11R 0x1EC
    110#define RPD12R 0x1F0
    111#define RPD14R 0x1F8
    112#define RPD15R 0x1FC
    113#define RPE3R 0x20C
    114#define RPE5R 0x214
    115#define RPE8R 0x220
    116#define RPE9R 0x224
    117#define RPF0R 0x240
    118#define RPF1R 0x244
    119#define RPF2R 0x248
    120#define RPF3R 0x24C
    121#define RPF4R 0x250
    122#define RPF5R 0x254
    123#define RPF8R 0x260
    124#define RPF12R 0x270
    125#define RPF13R 0x274
    126#define RPG0R 0x280
    127#define RPG1R 0x284
    128#define RPG6R 0x298
    129#define RPG7R 0x29C
    130#define RPG8R 0x2A0
    131#define RPG9R 0x2A4
    132
    133#endif  /* PINCTRL_PINCTRL_PIC32_H */