pinctrl-starfive.c (41928B)
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Pinctrl / GPIO driver for StarFive JH7100 SoC 4 * 5 * Copyright (C) 2020 Shanghai StarFive Technology Co., Ltd. 6 * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk> 7 */ 8 9#include <linux/bits.h> 10#include <linux/clk.h> 11#include <linux/gpio/driver.h> 12#include <linux/io.h> 13#include <linux/mod_devicetable.h> 14#include <linux/module.h> 15#include <linux/of.h> 16#include <linux/platform_device.h> 17#include <linux/reset.h> 18#include <linux/spinlock.h> 19 20#include <linux/pinctrl/pinctrl.h> 21#include <linux/pinctrl/pinmux.h> 22 23#include <dt-bindings/pinctrl/pinctrl-starfive.h> 24 25#include "core.h" 26#include "pinctrl-utils.h" 27#include "pinmux.h" 28#include "pinconf.h" 29 30#define DRIVER_NAME "pinctrl-starfive" 31 32/* 33 * Refer to Section 12. GPIO Registers in the JH7100 data sheet: 34 * https://github.com/starfive-tech/JH7100_Docs 35 */ 36#define NR_GPIOS 64 37 38/* 39 * Global enable for GPIO interrupts. If bit 0 is set to 1 the GPIO interrupts 40 * are enabled. If set to 0 the GPIO interrupts are disabled. 41 */ 42#define GPIOEN 0x000 43 44/* 45 * The following 32-bit registers come in pairs, but only the offset of the 46 * first register is defined. The first controls (interrupts for) GPIO 0-31 and 47 * the second GPIO 32-63. 48 */ 49 50/* 51 * Interrupt Type. If set to 1 the interrupt is edge-triggered. If set to 0 the 52 * interrupt is level-triggered. 53 */ 54#define GPIOIS 0x010 55 56/* 57 * Edge-Trigger Interrupt Type. If set to 1 the interrupt gets triggered on 58 * both positive and negative edges. If set to 0 the interrupt is triggered by a 59 * single edge. 60 */ 61#define GPIOIBE 0x018 62 63/* 64 * Interrupt Trigger Polarity. If set to 1 the interrupt is triggered on a 65 * rising edge (edge-triggered) or high level (level-triggered). If set to 0 the 66 * interrupt is triggered on a falling edge (edge-triggered) or low level 67 * (level-triggered). 68 */ 69#define GPIOIEV 0x020 70 71/* 72 * Interrupt Mask. If set to 1 the interrupt is enabled (unmasked). If set to 0 73 * the interrupt is disabled (masked). Note that the current documentation is 74 * wrong and says the exct opposite of this. 75 */ 76#define GPIOIE 0x028 77 78/* 79 * Clear Edge-Triggered Interrupts. Write a 1 to clear the edge-triggered 80 * interrupt. 81 */ 82#define GPIOIC 0x030 83 84/* 85 * Edge-Triggered Interrupt Status. A 1 means the configured edge was detected. 86 */ 87#define GPIORIS 0x038 88 89/* 90 * Interrupt Status after Masking. A 1 means the configured edge or level was 91 * detected and not masked. 92 */ 93#define GPIOMIS 0x040 94 95/* 96 * Data Value. Dynamically reflects the value of the GPIO pin. If 1 the pin is 97 * a digital 1 and if 0 the pin is a digital 0. 98 */ 99#define GPIODIN 0x048 100 101/* 102 * From the data sheet section 12.2, there are 64 32-bit output data registers 103 * and 64 output enable registers. Output data and output enable registers for 104 * a given GPIO are contiguous. Eg. GPO0_DOUT_CFG is 0x50 and GPO0_DOEN_CFG is 105 * 0x54 while GPO1_DOUT_CFG is 0x58 and GPO1_DOEN_CFG is 0x5c. The stride 106 * between GPIO registers is effectively 8, thus: GPOn_DOUT_CFG is 0x50 + 8n 107 * and GPOn_DOEN_CFG is 0x54 + 8n. 108 */ 109#define GPON_DOUT_CFG 0x050 110#define GPON_DOEN_CFG 0x054 111 112/* 113 * From Section 12.3, there are 75 input signal configuration registers which 114 * are 4 bytes wide starting with GPI_CPU_JTAG_TCK_CFG at 0x250 and ending with 115 * GPI_USB_OVER_CURRENT_CFG 0x378 116 */ 117#define GPI_CFG_OFFSET 0x250 118 119/* 120 * Pad Control Bits. There are 16 pad control bits for each pin located in 103 121 * 32-bit registers controlling PAD_GPIO[0] to PAD_GPIO[63] followed by 122 * PAD_FUNC_SHARE[0] to PAD_FUNC_SHARE[141]. Odd numbered pins use the upper 16 123 * bit of each register. 124 */ 125#define PAD_SLEW_RATE_MASK GENMASK(11, 9) 126#define PAD_SLEW_RATE_POS 9 127#define PAD_BIAS_STRONG_PULL_UP BIT(8) 128#define PAD_INPUT_ENABLE BIT(7) 129#define PAD_INPUT_SCHMITT_ENABLE BIT(6) 130#define PAD_BIAS_DISABLE BIT(5) 131#define PAD_BIAS_PULL_DOWN BIT(4) 132#define PAD_BIAS_MASK \ 133 (PAD_BIAS_STRONG_PULL_UP | \ 134 PAD_BIAS_DISABLE | \ 135 PAD_BIAS_PULL_DOWN) 136#define PAD_DRIVE_STRENGTH_MASK GENMASK(3, 0) 137#define PAD_DRIVE_STRENGTH_POS 0 138 139/* 140 * From Section 11, the IO_PADSHARE_SEL register can be programmed to select 141 * one of seven pre-defined multiplexed signal groups on PAD_FUNC_SHARE and 142 * PAD_GPIO pads. This is a global setting. 143 */ 144#define IO_PADSHARE_SEL 0x1a0 145 146/* 147 * This just needs to be some number such that when 148 * sfp->gpio.pin_base = PAD_INVALID_GPIO then 149 * starfive_pin_to_gpio(sfp, validpin) is never a valid GPIO number. 150 * That is it should underflow and return something >= NR_GPIOS. 151 */ 152#define PAD_INVALID_GPIO 0x10000 153 154/* 155 * The packed pinmux values from the device tree look like this: 156 * 157 * | 31 - 24 | 23 - 16 | 15 - 8 | 7 | 6 | 5 - 0 | 158 * | dout | doen | din | dout rev | doen rev | gpio nr | 159 * 160 * ..but the GPOn_DOUT_CFG and GPOn_DOEN_CFG registers look like this: 161 * 162 * | 31 | 30 - 8 | 7 - 0 | 163 * | dout/doen rev | unused | dout/doen | 164 */ 165static unsigned int starfive_pinmux_to_gpio(u32 v) 166{ 167 return v & (NR_GPIOS - 1); 168} 169 170static u32 starfive_pinmux_to_dout(u32 v) 171{ 172 return ((v & BIT(7)) << (31 - 7)) | ((v >> 24) & GENMASK(7, 0)); 173} 174 175static u32 starfive_pinmux_to_doen(u32 v) 176{ 177 return ((v & BIT(6)) << (31 - 6)) | ((v >> 16) & GENMASK(7, 0)); 178} 179 180static u32 starfive_pinmux_to_din(u32 v) 181{ 182 return (v >> 8) & GENMASK(7, 0); 183} 184 185/* 186 * The maximum GPIO output current depends on the chosen drive strength: 187 * 188 * DS: 0 1 2 3 4 5 6 7 189 * mA: 14.2 21.2 28.2 35.2 42.2 49.1 56.0 62.8 190 * 191 * After rounding that is 7*DS + 14 mA 192 */ 193static u32 starfive_drive_strength_to_max_mA(u16 ds) 194{ 195 return 7 * ds + 14; 196} 197 198static u16 starfive_drive_strength_from_max_mA(u32 i) 199{ 200 return (clamp(i, 14U, 63U) - 14) / 7; 201} 202 203struct starfive_pinctrl { 204 struct gpio_chip gc; 205 struct pinctrl_gpio_range gpios; 206 raw_spinlock_t lock; 207 void __iomem *base; 208 void __iomem *padctl; 209 struct pinctrl_dev *pctl; 210}; 211 212static inline unsigned int starfive_pin_to_gpio(const struct starfive_pinctrl *sfp, 213 unsigned int pin) 214{ 215 return pin - sfp->gpios.pin_base; 216} 217 218static inline unsigned int starfive_gpio_to_pin(const struct starfive_pinctrl *sfp, 219 unsigned int gpio) 220{ 221 return sfp->gpios.pin_base + gpio; 222} 223 224static struct starfive_pinctrl *starfive_from_irq_data(struct irq_data *d) 225{ 226 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 227 228 return container_of(gc, struct starfive_pinctrl, gc); 229} 230 231static struct starfive_pinctrl *starfive_from_irq_desc(struct irq_desc *desc) 232{ 233 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 234 235 return container_of(gc, struct starfive_pinctrl, gc); 236} 237 238static const struct pinctrl_pin_desc starfive_pins[] = { 239 PINCTRL_PIN(PAD_GPIO(0), "GPIO[0]"), 240 PINCTRL_PIN(PAD_GPIO(1), "GPIO[1]"), 241 PINCTRL_PIN(PAD_GPIO(2), "GPIO[2]"), 242 PINCTRL_PIN(PAD_GPIO(3), "GPIO[3]"), 243 PINCTRL_PIN(PAD_GPIO(4), "GPIO[4]"), 244 PINCTRL_PIN(PAD_GPIO(5), "GPIO[5]"), 245 PINCTRL_PIN(PAD_GPIO(6), "GPIO[6]"), 246 PINCTRL_PIN(PAD_GPIO(7), "GPIO[7]"), 247 PINCTRL_PIN(PAD_GPIO(8), "GPIO[8]"), 248 PINCTRL_PIN(PAD_GPIO(9), "GPIO[9]"), 249 PINCTRL_PIN(PAD_GPIO(10), "GPIO[10]"), 250 PINCTRL_PIN(PAD_GPIO(11), "GPIO[11]"), 251 PINCTRL_PIN(PAD_GPIO(12), "GPIO[12]"), 252 PINCTRL_PIN(PAD_GPIO(13), "GPIO[13]"), 253 PINCTRL_PIN(PAD_GPIO(14), "GPIO[14]"), 254 PINCTRL_PIN(PAD_GPIO(15), "GPIO[15]"), 255 PINCTRL_PIN(PAD_GPIO(16), "GPIO[16]"), 256 PINCTRL_PIN(PAD_GPIO(17), "GPIO[17]"), 257 PINCTRL_PIN(PAD_GPIO(18), "GPIO[18]"), 258 PINCTRL_PIN(PAD_GPIO(19), "GPIO[19]"), 259 PINCTRL_PIN(PAD_GPIO(20), "GPIO[20]"), 260 PINCTRL_PIN(PAD_GPIO(21), "GPIO[21]"), 261 PINCTRL_PIN(PAD_GPIO(22), "GPIO[22]"), 262 PINCTRL_PIN(PAD_GPIO(23), "GPIO[23]"), 263 PINCTRL_PIN(PAD_GPIO(24), "GPIO[24]"), 264 PINCTRL_PIN(PAD_GPIO(25), "GPIO[25]"), 265 PINCTRL_PIN(PAD_GPIO(26), "GPIO[26]"), 266 PINCTRL_PIN(PAD_GPIO(27), "GPIO[27]"), 267 PINCTRL_PIN(PAD_GPIO(28), "GPIO[28]"), 268 PINCTRL_PIN(PAD_GPIO(29), "GPIO[29]"), 269 PINCTRL_PIN(PAD_GPIO(30), "GPIO[30]"), 270 PINCTRL_PIN(PAD_GPIO(31), "GPIO[31]"), 271 PINCTRL_PIN(PAD_GPIO(32), "GPIO[32]"), 272 PINCTRL_PIN(PAD_GPIO(33), "GPIO[33]"), 273 PINCTRL_PIN(PAD_GPIO(34), "GPIO[34]"), 274 PINCTRL_PIN(PAD_GPIO(35), "GPIO[35]"), 275 PINCTRL_PIN(PAD_GPIO(36), "GPIO[36]"), 276 PINCTRL_PIN(PAD_GPIO(37), "GPIO[37]"), 277 PINCTRL_PIN(PAD_GPIO(38), "GPIO[38]"), 278 PINCTRL_PIN(PAD_GPIO(39), "GPIO[39]"), 279 PINCTRL_PIN(PAD_GPIO(40), "GPIO[40]"), 280 PINCTRL_PIN(PAD_GPIO(41), "GPIO[41]"), 281 PINCTRL_PIN(PAD_GPIO(42), "GPIO[42]"), 282 PINCTRL_PIN(PAD_GPIO(43), "GPIO[43]"), 283 PINCTRL_PIN(PAD_GPIO(44), "GPIO[44]"), 284 PINCTRL_PIN(PAD_GPIO(45), "GPIO[45]"), 285 PINCTRL_PIN(PAD_GPIO(46), "GPIO[46]"), 286 PINCTRL_PIN(PAD_GPIO(47), "GPIO[47]"), 287 PINCTRL_PIN(PAD_GPIO(48), "GPIO[48]"), 288 PINCTRL_PIN(PAD_GPIO(49), "GPIO[49]"), 289 PINCTRL_PIN(PAD_GPIO(50), "GPIO[50]"), 290 PINCTRL_PIN(PAD_GPIO(51), "GPIO[51]"), 291 PINCTRL_PIN(PAD_GPIO(52), "GPIO[52]"), 292 PINCTRL_PIN(PAD_GPIO(53), "GPIO[53]"), 293 PINCTRL_PIN(PAD_GPIO(54), "GPIO[54]"), 294 PINCTRL_PIN(PAD_GPIO(55), "GPIO[55]"), 295 PINCTRL_PIN(PAD_GPIO(56), "GPIO[56]"), 296 PINCTRL_PIN(PAD_GPIO(57), "GPIO[57]"), 297 PINCTRL_PIN(PAD_GPIO(58), "GPIO[58]"), 298 PINCTRL_PIN(PAD_GPIO(59), "GPIO[59]"), 299 PINCTRL_PIN(PAD_GPIO(60), "GPIO[60]"), 300 PINCTRL_PIN(PAD_GPIO(61), "GPIO[61]"), 301 PINCTRL_PIN(PAD_GPIO(62), "GPIO[62]"), 302 PINCTRL_PIN(PAD_GPIO(63), "GPIO[63]"), 303 PINCTRL_PIN(PAD_FUNC_SHARE(0), "FUNC_SHARE[0]"), 304 PINCTRL_PIN(PAD_FUNC_SHARE(1), "FUNC_SHARE[1]"), 305 PINCTRL_PIN(PAD_FUNC_SHARE(2), "FUNC_SHARE[2]"), 306 PINCTRL_PIN(PAD_FUNC_SHARE(3), "FUNC_SHARE[3]"), 307 PINCTRL_PIN(PAD_FUNC_SHARE(4), "FUNC_SHARE[4]"), 308 PINCTRL_PIN(PAD_FUNC_SHARE(5), "FUNC_SHARE[5]"), 309 PINCTRL_PIN(PAD_FUNC_SHARE(6), "FUNC_SHARE[6]"), 310 PINCTRL_PIN(PAD_FUNC_SHARE(7), "FUNC_SHARE[7]"), 311 PINCTRL_PIN(PAD_FUNC_SHARE(8), "FUNC_SHARE[8]"), 312 PINCTRL_PIN(PAD_FUNC_SHARE(9), "FUNC_SHARE[9]"), 313 PINCTRL_PIN(PAD_FUNC_SHARE(10), "FUNC_SHARE[10]"), 314 PINCTRL_PIN(PAD_FUNC_SHARE(11), "FUNC_SHARE[11]"), 315 PINCTRL_PIN(PAD_FUNC_SHARE(12), "FUNC_SHARE[12]"), 316 PINCTRL_PIN(PAD_FUNC_SHARE(13), "FUNC_SHARE[13]"), 317 PINCTRL_PIN(PAD_FUNC_SHARE(14), "FUNC_SHARE[14]"), 318 PINCTRL_PIN(PAD_FUNC_SHARE(15), "FUNC_SHARE[15]"), 319 PINCTRL_PIN(PAD_FUNC_SHARE(16), "FUNC_SHARE[16]"), 320 PINCTRL_PIN(PAD_FUNC_SHARE(17), "FUNC_SHARE[17]"), 321 PINCTRL_PIN(PAD_FUNC_SHARE(18), "FUNC_SHARE[18]"), 322 PINCTRL_PIN(PAD_FUNC_SHARE(19), "FUNC_SHARE[19]"), 323 PINCTRL_PIN(PAD_FUNC_SHARE(20), "FUNC_SHARE[20]"), 324 PINCTRL_PIN(PAD_FUNC_SHARE(21), "FUNC_SHARE[21]"), 325 PINCTRL_PIN(PAD_FUNC_SHARE(22), "FUNC_SHARE[22]"), 326 PINCTRL_PIN(PAD_FUNC_SHARE(23), "FUNC_SHARE[23]"), 327 PINCTRL_PIN(PAD_FUNC_SHARE(24), "FUNC_SHARE[24]"), 328 PINCTRL_PIN(PAD_FUNC_SHARE(25), "FUNC_SHARE[25]"), 329 PINCTRL_PIN(PAD_FUNC_SHARE(26), "FUNC_SHARE[26]"), 330 PINCTRL_PIN(PAD_FUNC_SHARE(27), "FUNC_SHARE[27]"), 331 PINCTRL_PIN(PAD_FUNC_SHARE(28), "FUNC_SHARE[28]"), 332 PINCTRL_PIN(PAD_FUNC_SHARE(29), "FUNC_SHARE[29]"), 333 PINCTRL_PIN(PAD_FUNC_SHARE(30), "FUNC_SHARE[30]"), 334 PINCTRL_PIN(PAD_FUNC_SHARE(31), "FUNC_SHARE[31]"), 335 PINCTRL_PIN(PAD_FUNC_SHARE(32), "FUNC_SHARE[32]"), 336 PINCTRL_PIN(PAD_FUNC_SHARE(33), "FUNC_SHARE[33]"), 337 PINCTRL_PIN(PAD_FUNC_SHARE(34), "FUNC_SHARE[34]"), 338 PINCTRL_PIN(PAD_FUNC_SHARE(35), "FUNC_SHARE[35]"), 339 PINCTRL_PIN(PAD_FUNC_SHARE(36), "FUNC_SHARE[36]"), 340 PINCTRL_PIN(PAD_FUNC_SHARE(37), "FUNC_SHARE[37]"), 341 PINCTRL_PIN(PAD_FUNC_SHARE(38), "FUNC_SHARE[38]"), 342 PINCTRL_PIN(PAD_FUNC_SHARE(39), "FUNC_SHARE[39]"), 343 PINCTRL_PIN(PAD_FUNC_SHARE(40), "FUNC_SHARE[40]"), 344 PINCTRL_PIN(PAD_FUNC_SHARE(41), "FUNC_SHARE[41]"), 345 PINCTRL_PIN(PAD_FUNC_SHARE(42), "FUNC_SHARE[42]"), 346 PINCTRL_PIN(PAD_FUNC_SHARE(43), "FUNC_SHARE[43]"), 347 PINCTRL_PIN(PAD_FUNC_SHARE(44), "FUNC_SHARE[44]"), 348 PINCTRL_PIN(PAD_FUNC_SHARE(45), "FUNC_SHARE[45]"), 349 PINCTRL_PIN(PAD_FUNC_SHARE(46), "FUNC_SHARE[46]"), 350 PINCTRL_PIN(PAD_FUNC_SHARE(47), "FUNC_SHARE[47]"), 351 PINCTRL_PIN(PAD_FUNC_SHARE(48), "FUNC_SHARE[48]"), 352 PINCTRL_PIN(PAD_FUNC_SHARE(49), "FUNC_SHARE[49]"), 353 PINCTRL_PIN(PAD_FUNC_SHARE(50), "FUNC_SHARE[50]"), 354 PINCTRL_PIN(PAD_FUNC_SHARE(51), "FUNC_SHARE[51]"), 355 PINCTRL_PIN(PAD_FUNC_SHARE(52), "FUNC_SHARE[52]"), 356 PINCTRL_PIN(PAD_FUNC_SHARE(53), "FUNC_SHARE[53]"), 357 PINCTRL_PIN(PAD_FUNC_SHARE(54), "FUNC_SHARE[54]"), 358 PINCTRL_PIN(PAD_FUNC_SHARE(55), "FUNC_SHARE[55]"), 359 PINCTRL_PIN(PAD_FUNC_SHARE(56), "FUNC_SHARE[56]"), 360 PINCTRL_PIN(PAD_FUNC_SHARE(57), "FUNC_SHARE[57]"), 361 PINCTRL_PIN(PAD_FUNC_SHARE(58), "FUNC_SHARE[58]"), 362 PINCTRL_PIN(PAD_FUNC_SHARE(59), "FUNC_SHARE[59]"), 363 PINCTRL_PIN(PAD_FUNC_SHARE(60), "FUNC_SHARE[60]"), 364 PINCTRL_PIN(PAD_FUNC_SHARE(61), "FUNC_SHARE[61]"), 365 PINCTRL_PIN(PAD_FUNC_SHARE(62), "FUNC_SHARE[62]"), 366 PINCTRL_PIN(PAD_FUNC_SHARE(63), "FUNC_SHARE[63]"), 367 PINCTRL_PIN(PAD_FUNC_SHARE(64), "FUNC_SHARE[64]"), 368 PINCTRL_PIN(PAD_FUNC_SHARE(65), "FUNC_SHARE[65]"), 369 PINCTRL_PIN(PAD_FUNC_SHARE(66), "FUNC_SHARE[66]"), 370 PINCTRL_PIN(PAD_FUNC_SHARE(67), "FUNC_SHARE[67]"), 371 PINCTRL_PIN(PAD_FUNC_SHARE(68), "FUNC_SHARE[68]"), 372 PINCTRL_PIN(PAD_FUNC_SHARE(69), "FUNC_SHARE[69]"), 373 PINCTRL_PIN(PAD_FUNC_SHARE(70), "FUNC_SHARE[70]"), 374 PINCTRL_PIN(PAD_FUNC_SHARE(71), "FUNC_SHARE[71]"), 375 PINCTRL_PIN(PAD_FUNC_SHARE(72), "FUNC_SHARE[72]"), 376 PINCTRL_PIN(PAD_FUNC_SHARE(73), "FUNC_SHARE[73]"), 377 PINCTRL_PIN(PAD_FUNC_SHARE(74), "FUNC_SHARE[74]"), 378 PINCTRL_PIN(PAD_FUNC_SHARE(75), "FUNC_SHARE[75]"), 379 PINCTRL_PIN(PAD_FUNC_SHARE(76), "FUNC_SHARE[76]"), 380 PINCTRL_PIN(PAD_FUNC_SHARE(77), "FUNC_SHARE[77]"), 381 PINCTRL_PIN(PAD_FUNC_SHARE(78), "FUNC_SHARE[78]"), 382 PINCTRL_PIN(PAD_FUNC_SHARE(79), "FUNC_SHARE[79]"), 383 PINCTRL_PIN(PAD_FUNC_SHARE(80), "FUNC_SHARE[80]"), 384 PINCTRL_PIN(PAD_FUNC_SHARE(81), "FUNC_SHARE[81]"), 385 PINCTRL_PIN(PAD_FUNC_SHARE(82), "FUNC_SHARE[82]"), 386 PINCTRL_PIN(PAD_FUNC_SHARE(83), "FUNC_SHARE[83]"), 387 PINCTRL_PIN(PAD_FUNC_SHARE(84), "FUNC_SHARE[84]"), 388 PINCTRL_PIN(PAD_FUNC_SHARE(85), "FUNC_SHARE[85]"), 389 PINCTRL_PIN(PAD_FUNC_SHARE(86), "FUNC_SHARE[86]"), 390 PINCTRL_PIN(PAD_FUNC_SHARE(87), "FUNC_SHARE[87]"), 391 PINCTRL_PIN(PAD_FUNC_SHARE(88), "FUNC_SHARE[88]"), 392 PINCTRL_PIN(PAD_FUNC_SHARE(89), "FUNC_SHARE[89]"), 393 PINCTRL_PIN(PAD_FUNC_SHARE(90), "FUNC_SHARE[90]"), 394 PINCTRL_PIN(PAD_FUNC_SHARE(91), "FUNC_SHARE[91]"), 395 PINCTRL_PIN(PAD_FUNC_SHARE(92), "FUNC_SHARE[92]"), 396 PINCTRL_PIN(PAD_FUNC_SHARE(93), "FUNC_SHARE[93]"), 397 PINCTRL_PIN(PAD_FUNC_SHARE(94), "FUNC_SHARE[94]"), 398 PINCTRL_PIN(PAD_FUNC_SHARE(95), "FUNC_SHARE[95]"), 399 PINCTRL_PIN(PAD_FUNC_SHARE(96), "FUNC_SHARE[96]"), 400 PINCTRL_PIN(PAD_FUNC_SHARE(97), "FUNC_SHARE[97]"), 401 PINCTRL_PIN(PAD_FUNC_SHARE(98), "FUNC_SHARE[98]"), 402 PINCTRL_PIN(PAD_FUNC_SHARE(99), "FUNC_SHARE[99]"), 403 PINCTRL_PIN(PAD_FUNC_SHARE(100), "FUNC_SHARE[100]"), 404 PINCTRL_PIN(PAD_FUNC_SHARE(101), "FUNC_SHARE[101]"), 405 PINCTRL_PIN(PAD_FUNC_SHARE(102), "FUNC_SHARE[102]"), 406 PINCTRL_PIN(PAD_FUNC_SHARE(103), "FUNC_SHARE[103]"), 407 PINCTRL_PIN(PAD_FUNC_SHARE(104), "FUNC_SHARE[104]"), 408 PINCTRL_PIN(PAD_FUNC_SHARE(105), "FUNC_SHARE[105]"), 409 PINCTRL_PIN(PAD_FUNC_SHARE(106), "FUNC_SHARE[106]"), 410 PINCTRL_PIN(PAD_FUNC_SHARE(107), "FUNC_SHARE[107]"), 411 PINCTRL_PIN(PAD_FUNC_SHARE(108), "FUNC_SHARE[108]"), 412 PINCTRL_PIN(PAD_FUNC_SHARE(109), "FUNC_SHARE[109]"), 413 PINCTRL_PIN(PAD_FUNC_SHARE(110), "FUNC_SHARE[110]"), 414 PINCTRL_PIN(PAD_FUNC_SHARE(111), "FUNC_SHARE[111]"), 415 PINCTRL_PIN(PAD_FUNC_SHARE(112), "FUNC_SHARE[112]"), 416 PINCTRL_PIN(PAD_FUNC_SHARE(113), "FUNC_SHARE[113]"), 417 PINCTRL_PIN(PAD_FUNC_SHARE(114), "FUNC_SHARE[114]"), 418 PINCTRL_PIN(PAD_FUNC_SHARE(115), "FUNC_SHARE[115]"), 419 PINCTRL_PIN(PAD_FUNC_SHARE(116), "FUNC_SHARE[116]"), 420 PINCTRL_PIN(PAD_FUNC_SHARE(117), "FUNC_SHARE[117]"), 421 PINCTRL_PIN(PAD_FUNC_SHARE(118), "FUNC_SHARE[118]"), 422 PINCTRL_PIN(PAD_FUNC_SHARE(119), "FUNC_SHARE[119]"), 423 PINCTRL_PIN(PAD_FUNC_SHARE(120), "FUNC_SHARE[120]"), 424 PINCTRL_PIN(PAD_FUNC_SHARE(121), "FUNC_SHARE[121]"), 425 PINCTRL_PIN(PAD_FUNC_SHARE(122), "FUNC_SHARE[122]"), 426 PINCTRL_PIN(PAD_FUNC_SHARE(123), "FUNC_SHARE[123]"), 427 PINCTRL_PIN(PAD_FUNC_SHARE(124), "FUNC_SHARE[124]"), 428 PINCTRL_PIN(PAD_FUNC_SHARE(125), "FUNC_SHARE[125]"), 429 PINCTRL_PIN(PAD_FUNC_SHARE(126), "FUNC_SHARE[126]"), 430 PINCTRL_PIN(PAD_FUNC_SHARE(127), "FUNC_SHARE[127]"), 431 PINCTRL_PIN(PAD_FUNC_SHARE(128), "FUNC_SHARE[128]"), 432 PINCTRL_PIN(PAD_FUNC_SHARE(129), "FUNC_SHARE[129]"), 433 PINCTRL_PIN(PAD_FUNC_SHARE(130), "FUNC_SHARE[130]"), 434 PINCTRL_PIN(PAD_FUNC_SHARE(131), "FUNC_SHARE[131]"), 435 PINCTRL_PIN(PAD_FUNC_SHARE(132), "FUNC_SHARE[132]"), 436 PINCTRL_PIN(PAD_FUNC_SHARE(133), "FUNC_SHARE[133]"), 437 PINCTRL_PIN(PAD_FUNC_SHARE(134), "FUNC_SHARE[134]"), 438 PINCTRL_PIN(PAD_FUNC_SHARE(135), "FUNC_SHARE[135]"), 439 PINCTRL_PIN(PAD_FUNC_SHARE(136), "FUNC_SHARE[136]"), 440 PINCTRL_PIN(PAD_FUNC_SHARE(137), "FUNC_SHARE[137]"), 441 PINCTRL_PIN(PAD_FUNC_SHARE(138), "FUNC_SHARE[138]"), 442 PINCTRL_PIN(PAD_FUNC_SHARE(139), "FUNC_SHARE[139]"), 443 PINCTRL_PIN(PAD_FUNC_SHARE(140), "FUNC_SHARE[140]"), 444 PINCTRL_PIN(PAD_FUNC_SHARE(141), "FUNC_SHARE[141]"), 445}; 446 447#ifdef CONFIG_DEBUG_FS 448static void starfive_pin_dbg_show(struct pinctrl_dev *pctldev, 449 struct seq_file *s, 450 unsigned int pin) 451{ 452 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); 453 unsigned int gpio = starfive_pin_to_gpio(sfp, pin); 454 void __iomem *reg; 455 u32 dout, doen; 456 457 if (gpio >= NR_GPIOS) 458 return; 459 460 reg = sfp->base + GPON_DOUT_CFG + 8 * gpio; 461 dout = readl_relaxed(reg + 0x000); 462 doen = readl_relaxed(reg + 0x004); 463 464 seq_printf(s, "dout=%lu%s doen=%lu%s", 465 dout & GENMASK(7, 0), (dout & BIT(31)) ? "r" : "", 466 doen & GENMASK(7, 0), (doen & BIT(31)) ? "r" : ""); 467} 468#else 469#define starfive_pin_dbg_show NULL 470#endif 471 472static int starfive_dt_node_to_map(struct pinctrl_dev *pctldev, 473 struct device_node *np, 474 struct pinctrl_map **maps, 475 unsigned int *num_maps) 476{ 477 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); 478 struct device *dev = sfp->gc.parent; 479 struct device_node *child; 480 struct pinctrl_map *map; 481 const char **pgnames; 482 const char *grpname; 483 u32 *pinmux; 484 int ngroups; 485 int *pins; 486 int nmaps; 487 int ret; 488 489 nmaps = 0; 490 ngroups = 0; 491 for_each_child_of_node(np, child) { 492 int npinmux = of_property_count_u32_elems(child, "pinmux"); 493 int npins = of_property_count_u32_elems(child, "pins"); 494 495 if (npinmux > 0 && npins > 0) { 496 dev_err(dev, "invalid pinctrl group %pOFn.%pOFn: both pinmux and pins set\n", 497 np, child); 498 of_node_put(child); 499 return -EINVAL; 500 } 501 if (npinmux == 0 && npins == 0) { 502 dev_err(dev, "invalid pinctrl group %pOFn.%pOFn: neither pinmux nor pins set\n", 503 np, child); 504 of_node_put(child); 505 return -EINVAL; 506 } 507 508 if (npinmux > 0) 509 nmaps += 2; 510 else 511 nmaps += 1; 512 ngroups += 1; 513 } 514 515 pgnames = devm_kcalloc(dev, ngroups, sizeof(*pgnames), GFP_KERNEL); 516 if (!pgnames) 517 return -ENOMEM; 518 519 map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL); 520 if (!map) 521 return -ENOMEM; 522 523 nmaps = 0; 524 ngroups = 0; 525 for_each_child_of_node(np, child) { 526 int npins; 527 int i; 528 529 grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", np, child); 530 if (!grpname) { 531 ret = -ENOMEM; 532 goto put_child; 533 } 534 535 pgnames[ngroups++] = grpname; 536 537 if ((npins = of_property_count_u32_elems(child, "pinmux")) > 0) { 538 pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL); 539 if (!pins) { 540 ret = -ENOMEM; 541 goto put_child; 542 } 543 544 pinmux = devm_kcalloc(dev, npins, sizeof(*pinmux), GFP_KERNEL); 545 if (!pinmux) { 546 ret = -ENOMEM; 547 goto put_child; 548 } 549 550 ret = of_property_read_u32_array(child, "pinmux", pinmux, npins); 551 if (ret) 552 goto put_child; 553 554 for (i = 0; i < npins; i++) { 555 unsigned int gpio = starfive_pinmux_to_gpio(pinmux[i]); 556 557 pins[i] = starfive_gpio_to_pin(sfp, gpio); 558 } 559 560 map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP; 561 map[nmaps].data.mux.function = np->name; 562 map[nmaps].data.mux.group = grpname; 563 nmaps += 1; 564 } else if ((npins = of_property_count_u32_elems(child, "pins")) > 0) { 565 pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL); 566 if (!pins) { 567 ret = -ENOMEM; 568 goto put_child; 569 } 570 571 pinmux = NULL; 572 573 for (i = 0; i < npins; i++) { 574 u32 v; 575 576 ret = of_property_read_u32_index(child, "pins", i, &v); 577 if (ret) 578 goto put_child; 579 pins[i] = v; 580 } 581 } else { 582 ret = -EINVAL; 583 goto put_child; 584 } 585 586 ret = pinctrl_generic_add_group(pctldev, grpname, pins, npins, pinmux); 587 if (ret < 0) { 588 dev_err(dev, "error adding group %s: %d\n", grpname, ret); 589 goto put_child; 590 } 591 592 ret = pinconf_generic_parse_dt_config(child, pctldev, 593 &map[nmaps].data.configs.configs, 594 &map[nmaps].data.configs.num_configs); 595 if (ret) { 596 dev_err(dev, "error parsing pin config of group %s: %d\n", 597 grpname, ret); 598 goto put_child; 599 } 600 601 /* don't create a map if there are no pinconf settings */ 602 if (map[nmaps].data.configs.num_configs == 0) 603 continue; 604 605 map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP; 606 map[nmaps].data.configs.group_or_pin = grpname; 607 nmaps += 1; 608 } 609 610 ret = pinmux_generic_add_function(pctldev, np->name, pgnames, ngroups, NULL); 611 if (ret < 0) { 612 dev_err(dev, "error adding function %s: %d\n", np->name, ret); 613 goto free_map; 614 } 615 616 *maps = map; 617 *num_maps = nmaps; 618 return 0; 619 620put_child: 621 of_node_put(child); 622free_map: 623 pinctrl_utils_free_map(pctldev, map, nmaps); 624 return ret; 625} 626 627static const struct pinctrl_ops starfive_pinctrl_ops = { 628 .get_groups_count = pinctrl_generic_get_group_count, 629 .get_group_name = pinctrl_generic_get_group_name, 630 .get_group_pins = pinctrl_generic_get_group_pins, 631 .pin_dbg_show = starfive_pin_dbg_show, 632 .dt_node_to_map = starfive_dt_node_to_map, 633 .dt_free_map = pinctrl_utils_free_map, 634}; 635 636static int starfive_set_mux(struct pinctrl_dev *pctldev, 637 unsigned int fsel, unsigned int gsel) 638{ 639 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); 640 struct device *dev = sfp->gc.parent; 641 const struct group_desc *group; 642 const u32 *pinmux; 643 unsigned int i; 644 645 group = pinctrl_generic_get_group(pctldev, gsel); 646 if (!group) 647 return -EINVAL; 648 649 pinmux = group->data; 650 for (i = 0; i < group->num_pins; i++) { 651 u32 v = pinmux[i]; 652 unsigned int gpio = starfive_pinmux_to_gpio(v); 653 u32 dout = starfive_pinmux_to_dout(v); 654 u32 doen = starfive_pinmux_to_doen(v); 655 u32 din = starfive_pinmux_to_din(v); 656 void __iomem *reg_dout; 657 void __iomem *reg_doen; 658 void __iomem *reg_din; 659 unsigned long flags; 660 661 dev_dbg(dev, "GPIO%u: dout=0x%x doen=0x%x din=0x%x\n", 662 gpio, dout, doen, din); 663 664 reg_dout = sfp->base + GPON_DOUT_CFG + 8 * gpio; 665 reg_doen = sfp->base + GPON_DOEN_CFG + 8 * gpio; 666 if (din != GPI_NONE) 667 reg_din = sfp->base + GPI_CFG_OFFSET + 4 * din; 668 else 669 reg_din = NULL; 670 671 raw_spin_lock_irqsave(&sfp->lock, flags); 672 writel_relaxed(dout, reg_dout); 673 writel_relaxed(doen, reg_doen); 674 if (reg_din) 675 writel_relaxed(gpio + 2, reg_din); 676 raw_spin_unlock_irqrestore(&sfp->lock, flags); 677 } 678 679 return 0; 680} 681 682static const struct pinmux_ops starfive_pinmux_ops = { 683 .get_functions_count = pinmux_generic_get_function_count, 684 .get_function_name = pinmux_generic_get_function_name, 685 .get_function_groups = pinmux_generic_get_function_groups, 686 .set_mux = starfive_set_mux, 687 .strict = true, 688}; 689 690static u16 starfive_padctl_get(struct starfive_pinctrl *sfp, 691 unsigned int pin) 692{ 693 void __iomem *reg = sfp->padctl + 4 * (pin / 2); 694 int shift = 16 * (pin % 2); 695 696 return readl_relaxed(reg) >> shift; 697} 698 699static void starfive_padctl_rmw(struct starfive_pinctrl *sfp, 700 unsigned int pin, 701 u16 _mask, u16 _value) 702{ 703 void __iomem *reg = sfp->padctl + 4 * (pin / 2); 704 int shift = 16 * (pin % 2); 705 u32 mask = (u32)_mask << shift; 706 u32 value = (u32)_value << shift; 707 unsigned long flags; 708 709 dev_dbg(sfp->gc.parent, "padctl_rmw(%u, 0x%03x, 0x%03x)\n", pin, _mask, _value); 710 711 raw_spin_lock_irqsave(&sfp->lock, flags); 712 value |= readl_relaxed(reg) & ~mask; 713 writel_relaxed(value, reg); 714 raw_spin_unlock_irqrestore(&sfp->lock, flags); 715} 716 717#define PIN_CONFIG_STARFIVE_STRONG_PULL_UP (PIN_CONFIG_END + 1) 718 719static const struct pinconf_generic_params starfive_pinconf_custom_params[] = { 720 { "starfive,strong-pull-up", PIN_CONFIG_STARFIVE_STRONG_PULL_UP, 1 }, 721}; 722 723#ifdef CONFIG_DEBUG_FS 724static const struct pin_config_item starfive_pinconf_custom_conf_items[] = { 725 PCONFDUMP(PIN_CONFIG_STARFIVE_STRONG_PULL_UP, "input bias strong pull-up", NULL, false), 726}; 727 728static_assert(ARRAY_SIZE(starfive_pinconf_custom_conf_items) == 729 ARRAY_SIZE(starfive_pinconf_custom_params)); 730#else 731#define starfive_pinconf_custom_conf_items NULL 732#endif 733 734static int starfive_pinconf_get(struct pinctrl_dev *pctldev, 735 unsigned int pin, unsigned long *config) 736{ 737 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); 738 int param = pinconf_to_config_param(*config); 739 u16 value = starfive_padctl_get(sfp, pin); 740 bool enabled; 741 u32 arg; 742 743 switch (param) { 744 case PIN_CONFIG_BIAS_DISABLE: 745 enabled = value & PAD_BIAS_DISABLE; 746 arg = 0; 747 break; 748 case PIN_CONFIG_BIAS_PULL_DOWN: 749 enabled = value & PAD_BIAS_PULL_DOWN; 750 arg = 1; 751 break; 752 case PIN_CONFIG_BIAS_PULL_UP: 753 enabled = !(value & PAD_BIAS_MASK); 754 arg = 1; 755 break; 756 case PIN_CONFIG_DRIVE_STRENGTH: 757 enabled = value & PAD_DRIVE_STRENGTH_MASK; 758 arg = starfive_drive_strength_to_max_mA(value & PAD_DRIVE_STRENGTH_MASK); 759 break; 760 case PIN_CONFIG_INPUT_ENABLE: 761 enabled = value & PAD_INPUT_ENABLE; 762 arg = enabled; 763 break; 764 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 765 enabled = value & PAD_INPUT_SCHMITT_ENABLE; 766 arg = enabled; 767 break; 768 case PIN_CONFIG_SLEW_RATE: 769 enabled = value & PAD_SLEW_RATE_MASK; 770 arg = (value & PAD_SLEW_RATE_MASK) >> PAD_SLEW_RATE_POS; 771 break; 772 case PIN_CONFIG_STARFIVE_STRONG_PULL_UP: 773 enabled = value & PAD_BIAS_STRONG_PULL_UP; 774 arg = enabled; 775 break; 776 default: 777 return -ENOTSUPP; 778 } 779 780 *config = pinconf_to_config_packed(param, arg); 781 return enabled ? 0 : -EINVAL; 782} 783 784static int starfive_pinconf_group_get(struct pinctrl_dev *pctldev, 785 unsigned int gsel, unsigned long *config) 786{ 787 const struct group_desc *group; 788 789 group = pinctrl_generic_get_group(pctldev, gsel); 790 if (!group) 791 return -EINVAL; 792 793 return starfive_pinconf_get(pctldev, group->pins[0], config); 794} 795 796static int starfive_pinconf_group_set(struct pinctrl_dev *pctldev, 797 unsigned int gsel, 798 unsigned long *configs, 799 unsigned int num_configs) 800{ 801 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); 802 const struct group_desc *group; 803 u16 mask, value; 804 int i; 805 806 group = pinctrl_generic_get_group(pctldev, gsel); 807 if (!group) 808 return -EINVAL; 809 810 mask = 0; 811 value = 0; 812 for (i = 0; i < num_configs; i++) { 813 int param = pinconf_to_config_param(configs[i]); 814 u32 arg = pinconf_to_config_argument(configs[i]); 815 816 switch (param) { 817 case PIN_CONFIG_BIAS_DISABLE: 818 mask |= PAD_BIAS_MASK; 819 value = (value & ~PAD_BIAS_MASK) | PAD_BIAS_DISABLE; 820 break; 821 case PIN_CONFIG_BIAS_PULL_DOWN: 822 if (arg == 0) 823 return -ENOTSUPP; 824 mask |= PAD_BIAS_MASK; 825 value = (value & ~PAD_BIAS_MASK) | PAD_BIAS_PULL_DOWN; 826 break; 827 case PIN_CONFIG_BIAS_PULL_UP: 828 if (arg == 0) 829 return -ENOTSUPP; 830 mask |= PAD_BIAS_MASK; 831 value = value & ~PAD_BIAS_MASK; 832 break; 833 case PIN_CONFIG_DRIVE_STRENGTH: 834 mask |= PAD_DRIVE_STRENGTH_MASK; 835 value = (value & ~PAD_DRIVE_STRENGTH_MASK) | 836 starfive_drive_strength_from_max_mA(arg); 837 break; 838 case PIN_CONFIG_INPUT_ENABLE: 839 mask |= PAD_INPUT_ENABLE; 840 if (arg) 841 value |= PAD_INPUT_ENABLE; 842 else 843 value &= ~PAD_INPUT_ENABLE; 844 break; 845 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 846 mask |= PAD_INPUT_SCHMITT_ENABLE; 847 if (arg) 848 value |= PAD_INPUT_SCHMITT_ENABLE; 849 else 850 value &= ~PAD_INPUT_SCHMITT_ENABLE; 851 break; 852 case PIN_CONFIG_SLEW_RATE: 853 mask |= PAD_SLEW_RATE_MASK; 854 value = (value & ~PAD_SLEW_RATE_MASK) | 855 ((arg << PAD_SLEW_RATE_POS) & PAD_SLEW_RATE_MASK); 856 break; 857 case PIN_CONFIG_STARFIVE_STRONG_PULL_UP: 858 if (arg) { 859 mask |= PAD_BIAS_MASK; 860 value = (value & ~PAD_BIAS_MASK) | 861 PAD_BIAS_STRONG_PULL_UP; 862 } else { 863 mask |= PAD_BIAS_STRONG_PULL_UP; 864 value = value & ~PAD_BIAS_STRONG_PULL_UP; 865 } 866 break; 867 default: 868 return -ENOTSUPP; 869 } 870 } 871 872 for (i = 0; i < group->num_pins; i++) 873 starfive_padctl_rmw(sfp, group->pins[i], mask, value); 874 875 return 0; 876} 877 878#ifdef CONFIG_DEBUG_FS 879static void starfive_pinconf_dbg_show(struct pinctrl_dev *pctldev, 880 struct seq_file *s, unsigned int pin) 881{ 882 struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); 883 u16 value = starfive_padctl_get(sfp, pin); 884 885 seq_printf(s, " (0x%03x)", value); 886} 887#else 888#define starfive_pinconf_dbg_show NULL 889#endif 890 891static const struct pinconf_ops starfive_pinconf_ops = { 892 .pin_config_get = starfive_pinconf_get, 893 .pin_config_group_get = starfive_pinconf_group_get, 894 .pin_config_group_set = starfive_pinconf_group_set, 895 .pin_config_dbg_show = starfive_pinconf_dbg_show, 896 .is_generic = true, 897}; 898 899static struct pinctrl_desc starfive_desc = { 900 .name = DRIVER_NAME, 901 .pins = starfive_pins, 902 .npins = ARRAY_SIZE(starfive_pins), 903 .pctlops = &starfive_pinctrl_ops, 904 .pmxops = &starfive_pinmux_ops, 905 .confops = &starfive_pinconf_ops, 906 .owner = THIS_MODULE, 907 .num_custom_params = ARRAY_SIZE(starfive_pinconf_custom_params), 908 .custom_params = starfive_pinconf_custom_params, 909 .custom_conf_items = starfive_pinconf_custom_conf_items, 910}; 911 912static int starfive_gpio_request(struct gpio_chip *gc, unsigned int gpio) 913{ 914 return pinctrl_gpio_request(gc->base + gpio); 915} 916 917static void starfive_gpio_free(struct gpio_chip *gc, unsigned int gpio) 918{ 919 pinctrl_gpio_free(gc->base + gpio); 920} 921 922static int starfive_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio) 923{ 924 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc); 925 void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio; 926 927 if (readl_relaxed(doen) == GPO_ENABLE) 928 return GPIO_LINE_DIRECTION_OUT; 929 930 return GPIO_LINE_DIRECTION_IN; 931} 932 933static int starfive_gpio_direction_input(struct gpio_chip *gc, 934 unsigned int gpio) 935{ 936 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc); 937 void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio; 938 unsigned long flags; 939 940 /* enable input and schmitt trigger */ 941 starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio), 942 PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE, 943 PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE); 944 945 raw_spin_lock_irqsave(&sfp->lock, flags); 946 writel_relaxed(GPO_DISABLE, doen); 947 raw_spin_unlock_irqrestore(&sfp->lock, flags); 948 return 0; 949} 950 951static int starfive_gpio_direction_output(struct gpio_chip *gc, 952 unsigned int gpio, int value) 953{ 954 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc); 955 void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio; 956 void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio; 957 unsigned long flags; 958 959 raw_spin_lock_irqsave(&sfp->lock, flags); 960 writel_relaxed(value, dout); 961 writel_relaxed(GPO_ENABLE, doen); 962 raw_spin_unlock_irqrestore(&sfp->lock, flags); 963 964 /* disable input, schmitt trigger and bias */ 965 starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio), 966 PAD_BIAS_MASK | PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE, 967 PAD_BIAS_DISABLE); 968 969 return 0; 970} 971 972static int starfive_gpio_get(struct gpio_chip *gc, unsigned int gpio) 973{ 974 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc); 975 void __iomem *din = sfp->base + GPIODIN + 4 * (gpio / 32); 976 977 return !!(readl_relaxed(din) & BIT(gpio % 32)); 978} 979 980static void starfive_gpio_set(struct gpio_chip *gc, unsigned int gpio, 981 int value) 982{ 983 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc); 984 void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio; 985 unsigned long flags; 986 987 raw_spin_lock_irqsave(&sfp->lock, flags); 988 writel_relaxed(value, dout); 989 raw_spin_unlock_irqrestore(&sfp->lock, flags); 990} 991 992static int starfive_gpio_set_config(struct gpio_chip *gc, unsigned int gpio, 993 unsigned long config) 994{ 995 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc); 996 u32 arg = pinconf_to_config_argument(config); 997 u16 value; 998 u16 mask; 999 1000 switch (pinconf_to_config_param(config)) { 1001 case PIN_CONFIG_BIAS_DISABLE: 1002 mask = PAD_BIAS_MASK; 1003 value = PAD_BIAS_DISABLE; 1004 break; 1005 case PIN_CONFIG_BIAS_PULL_DOWN: 1006 if (arg == 0) 1007 return -ENOTSUPP; 1008 mask = PAD_BIAS_MASK; 1009 value = PAD_BIAS_PULL_DOWN; 1010 break; 1011 case PIN_CONFIG_BIAS_PULL_UP: 1012 if (arg == 0) 1013 return -ENOTSUPP; 1014 mask = PAD_BIAS_MASK; 1015 value = 0; 1016 break; 1017 case PIN_CONFIG_DRIVE_PUSH_PULL: 1018 return 0; 1019 case PIN_CONFIG_INPUT_ENABLE: 1020 mask = PAD_INPUT_ENABLE; 1021 value = arg ? PAD_INPUT_ENABLE : 0; 1022 break; 1023 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1024 mask = PAD_INPUT_SCHMITT_ENABLE; 1025 value = arg ? PAD_INPUT_SCHMITT_ENABLE : 0; 1026 break; 1027 default: 1028 return -ENOTSUPP; 1029 } 1030 1031 starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio), mask, value); 1032 return 0; 1033} 1034 1035static int starfive_gpio_add_pin_ranges(struct gpio_chip *gc) 1036{ 1037 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc); 1038 1039 sfp->gpios.name = sfp->gc.label; 1040 sfp->gpios.base = sfp->gc.base; 1041 /* 1042 * sfp->gpios.pin_base depends on the chosen signal group 1043 * and is set in starfive_probe() 1044 */ 1045 sfp->gpios.npins = NR_GPIOS; 1046 sfp->gpios.gc = &sfp->gc; 1047 pinctrl_add_gpio_range(sfp->pctl, &sfp->gpios); 1048 return 0; 1049} 1050 1051static void starfive_irq_ack(struct irq_data *d) 1052{ 1053 struct starfive_pinctrl *sfp = starfive_from_irq_data(d); 1054 irq_hw_number_t gpio = irqd_to_hwirq(d); 1055 void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32); 1056 u32 mask = BIT(gpio % 32); 1057 unsigned long flags; 1058 1059 raw_spin_lock_irqsave(&sfp->lock, flags); 1060 writel_relaxed(mask, ic); 1061 raw_spin_unlock_irqrestore(&sfp->lock, flags); 1062} 1063 1064static void starfive_irq_mask(struct irq_data *d) 1065{ 1066 struct starfive_pinctrl *sfp = starfive_from_irq_data(d); 1067 irq_hw_number_t gpio = irqd_to_hwirq(d); 1068 void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32); 1069 u32 mask = BIT(gpio % 32); 1070 unsigned long flags; 1071 u32 value; 1072 1073 raw_spin_lock_irqsave(&sfp->lock, flags); 1074 value = readl_relaxed(ie) & ~mask; 1075 writel_relaxed(value, ie); 1076 raw_spin_unlock_irqrestore(&sfp->lock, flags); 1077 1078 gpiochip_disable_irq(&sfp->gc, d->hwirq); 1079} 1080 1081static void starfive_irq_mask_ack(struct irq_data *d) 1082{ 1083 struct starfive_pinctrl *sfp = starfive_from_irq_data(d); 1084 irq_hw_number_t gpio = irqd_to_hwirq(d); 1085 void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32); 1086 void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32); 1087 u32 mask = BIT(gpio % 32); 1088 unsigned long flags; 1089 u32 value; 1090 1091 raw_spin_lock_irqsave(&sfp->lock, flags); 1092 value = readl_relaxed(ie) & ~mask; 1093 writel_relaxed(value, ie); 1094 writel_relaxed(mask, ic); 1095 raw_spin_unlock_irqrestore(&sfp->lock, flags); 1096} 1097 1098static void starfive_irq_unmask(struct irq_data *d) 1099{ 1100 struct starfive_pinctrl *sfp = starfive_from_irq_data(d); 1101 irq_hw_number_t gpio = irqd_to_hwirq(d); 1102 void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32); 1103 u32 mask = BIT(gpio % 32); 1104 unsigned long flags; 1105 u32 value; 1106 1107 gpiochip_enable_irq(&sfp->gc, d->hwirq); 1108 1109 raw_spin_lock_irqsave(&sfp->lock, flags); 1110 value = readl_relaxed(ie) | mask; 1111 writel_relaxed(value, ie); 1112 raw_spin_unlock_irqrestore(&sfp->lock, flags); 1113} 1114 1115static int starfive_irq_set_type(struct irq_data *d, unsigned int trigger) 1116{ 1117 struct starfive_pinctrl *sfp = starfive_from_irq_data(d); 1118 irq_hw_number_t gpio = irqd_to_hwirq(d); 1119 void __iomem *base = sfp->base + 4 * (gpio / 32); 1120 u32 mask = BIT(gpio % 32); 1121 u32 irq_type, edge_both, polarity; 1122 unsigned long flags; 1123 1124 switch (trigger) { 1125 case IRQ_TYPE_EDGE_RISING: 1126 irq_type = mask; /* 1: edge triggered */ 1127 edge_both = 0; /* 0: single edge */ 1128 polarity = mask; /* 1: rising edge */ 1129 break; 1130 case IRQ_TYPE_EDGE_FALLING: 1131 irq_type = mask; /* 1: edge triggered */ 1132 edge_both = 0; /* 0: single edge */ 1133 polarity = 0; /* 0: falling edge */ 1134 break; 1135 case IRQ_TYPE_EDGE_BOTH: 1136 irq_type = mask; /* 1: edge triggered */ 1137 edge_both = mask; /* 1: both edges */ 1138 polarity = 0; /* 0: ignored */ 1139 break; 1140 case IRQ_TYPE_LEVEL_HIGH: 1141 irq_type = 0; /* 0: level triggered */ 1142 edge_both = 0; /* 0: ignored */ 1143 polarity = mask; /* 1: high level */ 1144 break; 1145 case IRQ_TYPE_LEVEL_LOW: 1146 irq_type = 0; /* 0: level triggered */ 1147 edge_both = 0; /* 0: ignored */ 1148 polarity = 0; /* 0: low level */ 1149 break; 1150 default: 1151 return -EINVAL; 1152 } 1153 1154 if (trigger & IRQ_TYPE_EDGE_BOTH) 1155 irq_set_handler_locked(d, handle_edge_irq); 1156 else 1157 irq_set_handler_locked(d, handle_level_irq); 1158 1159 raw_spin_lock_irqsave(&sfp->lock, flags); 1160 irq_type |= readl_relaxed(base + GPIOIS) & ~mask; 1161 writel_relaxed(irq_type, base + GPIOIS); 1162 edge_both |= readl_relaxed(base + GPIOIBE) & ~mask; 1163 writel_relaxed(edge_both, base + GPIOIBE); 1164 polarity |= readl_relaxed(base + GPIOIEV) & ~mask; 1165 writel_relaxed(polarity, base + GPIOIEV); 1166 raw_spin_unlock_irqrestore(&sfp->lock, flags); 1167 return 0; 1168} 1169 1170static const struct irq_chip starfive_irq_chip = { 1171 .name = "StarFive GPIO", 1172 .irq_ack = starfive_irq_ack, 1173 .irq_mask = starfive_irq_mask, 1174 .irq_mask_ack = starfive_irq_mask_ack, 1175 .irq_unmask = starfive_irq_unmask, 1176 .irq_set_type = starfive_irq_set_type, 1177 .flags = IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED, 1178 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1179}; 1180 1181static void starfive_gpio_irq_handler(struct irq_desc *desc) 1182{ 1183 struct starfive_pinctrl *sfp = starfive_from_irq_desc(desc); 1184 struct irq_chip *chip = irq_desc_get_chip(desc); 1185 unsigned long mis; 1186 unsigned int pin; 1187 1188 chained_irq_enter(chip, desc); 1189 1190 mis = readl_relaxed(sfp->base + GPIOMIS + 0); 1191 for_each_set_bit(pin, &mis, 32) 1192 generic_handle_domain_irq(sfp->gc.irq.domain, pin); 1193 1194 mis = readl_relaxed(sfp->base + GPIOMIS + 4); 1195 for_each_set_bit(pin, &mis, 32) 1196 generic_handle_domain_irq(sfp->gc.irq.domain, pin + 32); 1197 1198 chained_irq_exit(chip, desc); 1199} 1200 1201static int starfive_gpio_init_hw(struct gpio_chip *gc) 1202{ 1203 struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc); 1204 1205 /* mask all GPIO interrupts */ 1206 writel(0, sfp->base + GPIOIE + 0); 1207 writel(0, sfp->base + GPIOIE + 4); 1208 /* clear edge interrupt flags */ 1209 writel(~0U, sfp->base + GPIOIC + 0); 1210 writel(~0U, sfp->base + GPIOIC + 4); 1211 /* enable GPIO interrupts */ 1212 writel(1, sfp->base + GPIOEN); 1213 return 0; 1214} 1215 1216static void starfive_disable_clock(void *data) 1217{ 1218 clk_disable_unprepare(data); 1219} 1220 1221static int starfive_probe(struct platform_device *pdev) 1222{ 1223 struct device *dev = &pdev->dev; 1224 struct starfive_pinctrl *sfp; 1225 struct reset_control *rst; 1226 struct clk *clk; 1227 u32 value; 1228 int ret; 1229 1230 sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL); 1231 if (!sfp) 1232 return -ENOMEM; 1233 1234 sfp->base = devm_platform_ioremap_resource_byname(pdev, "gpio"); 1235 if (IS_ERR(sfp->base)) 1236 return PTR_ERR(sfp->base); 1237 1238 sfp->padctl = devm_platform_ioremap_resource_byname(pdev, "padctl"); 1239 if (IS_ERR(sfp->padctl)) 1240 return PTR_ERR(sfp->padctl); 1241 1242 clk = devm_clk_get(dev, NULL); 1243 if (IS_ERR(clk)) 1244 return dev_err_probe(dev, PTR_ERR(clk), "could not get clock\n"); 1245 1246 rst = devm_reset_control_get_exclusive(dev, NULL); 1247 if (IS_ERR(rst)) 1248 return dev_err_probe(dev, PTR_ERR(rst), "could not get reset\n"); 1249 1250 ret = clk_prepare_enable(clk); 1251 if (ret) 1252 return dev_err_probe(dev, ret, "could not enable clock\n"); 1253 1254 ret = devm_add_action_or_reset(dev, starfive_disable_clock, clk); 1255 if (ret) 1256 return ret; 1257 1258 /* 1259 * We don't want to assert reset and risk undoing pin muxing for the 1260 * early boot serial console, but let's make sure the reset line is 1261 * deasserted in case someone runs a really minimal bootloader. 1262 */ 1263 ret = reset_control_deassert(rst); 1264 if (ret) 1265 return dev_err_probe(dev, ret, "could not deassert reset\n"); 1266 1267 platform_set_drvdata(pdev, sfp); 1268 sfp->gc.parent = dev; 1269 raw_spin_lock_init(&sfp->lock); 1270 1271 ret = devm_pinctrl_register_and_init(dev, &starfive_desc, sfp, &sfp->pctl); 1272 if (ret) 1273 return dev_err_probe(dev, ret, "could not register pinctrl driver\n"); 1274 1275 if (!of_property_read_u32(dev->of_node, "starfive,signal-group", &value)) { 1276 if (value > 6) 1277 return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value); 1278 writel(value, sfp->padctl + IO_PADSHARE_SEL); 1279 } 1280 1281 value = readl(sfp->padctl + IO_PADSHARE_SEL); 1282 switch (value) { 1283 case 0: 1284 sfp->gpios.pin_base = PAD_INVALID_GPIO; 1285 goto out_pinctrl_enable; 1286 case 1: 1287 sfp->gpios.pin_base = PAD_GPIO(0); 1288 break; 1289 case 2: 1290 sfp->gpios.pin_base = PAD_FUNC_SHARE(72); 1291 break; 1292 case 3: 1293 sfp->gpios.pin_base = PAD_FUNC_SHARE(70); 1294 break; 1295 case 4: case 5: case 6: 1296 sfp->gpios.pin_base = PAD_FUNC_SHARE(0); 1297 break; 1298 default: 1299 return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value); 1300 } 1301 1302 sfp->gc.label = dev_name(dev); 1303 sfp->gc.owner = THIS_MODULE; 1304 sfp->gc.request = starfive_gpio_request; 1305 sfp->gc.free = starfive_gpio_free; 1306 sfp->gc.get_direction = starfive_gpio_get_direction; 1307 sfp->gc.direction_input = starfive_gpio_direction_input; 1308 sfp->gc.direction_output = starfive_gpio_direction_output; 1309 sfp->gc.get = starfive_gpio_get; 1310 sfp->gc.set = starfive_gpio_set; 1311 sfp->gc.set_config = starfive_gpio_set_config; 1312 sfp->gc.add_pin_ranges = starfive_gpio_add_pin_ranges; 1313 sfp->gc.base = -1; 1314 sfp->gc.ngpio = NR_GPIOS; 1315 1316 gpio_irq_chip_set_chip(&sfp->gc.irq, &starfive_irq_chip); 1317 sfp->gc.irq.parent_handler = starfive_gpio_irq_handler; 1318 sfp->gc.irq.num_parents = 1; 1319 sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents, 1320 sizeof(*sfp->gc.irq.parents), GFP_KERNEL); 1321 if (!sfp->gc.irq.parents) 1322 return -ENOMEM; 1323 sfp->gc.irq.default_type = IRQ_TYPE_NONE; 1324 sfp->gc.irq.handler = handle_bad_irq; 1325 sfp->gc.irq.init_hw = starfive_gpio_init_hw; 1326 1327 ret = platform_get_irq(pdev, 0); 1328 if (ret < 0) 1329 return ret; 1330 sfp->gc.irq.parents[0] = ret; 1331 1332 ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp); 1333 if (ret) 1334 return dev_err_probe(dev, ret, "could not register gpiochip\n"); 1335 1336 irq_domain_set_pm_device(sfp->gc.irq.domain, dev); 1337 1338out_pinctrl_enable: 1339 return pinctrl_enable(sfp->pctl); 1340} 1341 1342static const struct of_device_id starfive_of_match[] = { 1343 { .compatible = "starfive,jh7100-pinctrl" }, 1344 { /* sentinel */ } 1345}; 1346MODULE_DEVICE_TABLE(of, starfive_of_match); 1347 1348static struct platform_driver starfive_pinctrl_driver = { 1349 .probe = starfive_probe, 1350 .driver = { 1351 .name = DRIVER_NAME, 1352 .of_match_table = starfive_of_match, 1353 }, 1354}; 1355module_platform_driver(starfive_pinctrl_driver); 1356 1357MODULE_DESCRIPTION("Pinctrl driver for StarFive SoCs"); 1358MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>"); 1359MODULE_LICENSE("GPL v2");